Tcwg-commits July 2019

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap updated (74887405157 -> 0240c270776)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap in repository toolchain/ci/gcc. from 74887405157 Daily bump. adds 2ffd3486ab4 Daily bump. adds 4b1059d63af Backport r272992 adds ffc7eb0bf98 [MIPS][Testsuite] Specify msa-fmadd.c abis. adds 2052a2bc9ff Daily bump. adds 83cfdc89abe Daily bump. adds a1425c004e8 Daily bump. adds 0240c270776 2019-07-07 Paul Thomas <pault(a)gcc.gnu.org> No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 9 +++ gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 7 ++ gcc/fortran/trans-array.c | 6 +- gcc/multiple_target.c | 3 +- gcc/testsuite/ChangeLog | 21 +++++ gcc/testsuite/gcc.target/i386/pr90899.c | 6 ++ .../mips/{msa-fmadd.c => msa-fmadd-n64.c} | 36 ++++----- .../mips/{msa-fmadd.c => msa-fmadd-o32.c} | 2 +- gcc/testsuite/gfortran.dg/pointer_array_11.f90 | 90 ++++++++++++++++++++++ 10 files changed, 157 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr90899.c copy gcc/testsuite/gcc.target/mips/{msa-fmadd.c => msa-fmadd-n64.c} (50%) rename gcc/testsuite/gcc.target/mips/{msa-fmadd.c => msa-fmadd-o32.c} (96%) create mode 100644 gcc/testsuite/gfortran.dg/pointer_array_11.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap updated (3f8dabb -> 17a53c3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap in repository toolchain/ci/base-artifacts. discards 3f8dabb 0: update: gcc-74887405157f5d692b98f01190e00cde70206e15: -5 new 17a53c3 0: update: gcc-0240c270776948b7b8a50380af246b4aae4857c5: -5 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (3f8dabb) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-arm-boot [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 330 +- 03-build_abe-bootstrap/console.log | 86718 +++++++++++++++++----------------- console.log | 87178 ++++++++++++++++++----------------- jenkins/manifest.sh | 10 +- 5 files changed, 87193 insertions(+), 87173 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (e753247b061 -> 842f55f3efe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/llvm-project. from e753247b061 [X86] Add PS<->PD domain changing support for MOVH/MOVL loa [...] adds 9c68aa33e3b [DAGCombine] convertBuildVecZextToZext - remove duplicate g [...] adds 01f1bad6182 [X86] LowerBuildVectorv16i8 - pull out repeated getOperand( [...] adds a7145c45a7e [X86] SimplifyDemandedVectorEltsForTargetNode - fix shadow [...] adds 9e52c43090f Treat the range of representable values of floating-point t [...] adds 8baf83839e9 Fix PR27658 - Make ~mutex trivial when possible. adds 617df204b5b [CodeGen] Add larger vector types for i32 and f32 adds ac744d5a864 [X86] Make sure load isn't volatile before shrinking it in [...] adds 3e9ef48440a gn build: Merge r365258 and follow-ups r365263, r365264 adds d22fd0e4ecc gn build: Sort cxx_sources in libcxx build file adds 7e063620611 gn build: Sort sync script output adds 18d138e6acc gn build: Merge r365273 adds 87210015581 gn build: Merge r355546 adds 8cedf04a6c8 Make ~mutex and ~condition_variable trivial on Windows. new 842f55f3efe Process: generalise Windows thread setup The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/docs/UndefinedBehaviorSanitizer.rst | 18 +- clang/include/clang/Basic/Sanitizers.def | 2 +- clang/lib/AST/ExprConstant.cpp | 22 +- clang/lib/CodeGen/CGExprScalar.cpp | 178 +++++-------- clang/test/CXX/expr/expr.const/p2-0x.cpp | 28 ++- clang/test/CodeGen/catch-undef-behavior.c | 42 +--- clang/test/Driver/fsanitize.c | 18 +- clang/test/SemaCXX/constant-expression-cxx1y.cpp | 5 +- libcxx/include/__config | 17 ++ libcxx/include/__mutex_base | 42 ++-- libcxx/src/CMakeLists.txt | 2 + libcxx/src/condition_variable.cpp | 5 +- libcxx/src/condition_variable_destructor.cpp | 46 ++++ libcxx/src/mutex.cpp | 5 +- libcxx/src/mutex_destructor.cpp | 51 ++++ .../thread.mutex.class/default.pass.cpp | 6 +- .../Process/Windows/Common/TargetThreadWindows.cpp | 30 ++- llvm/include/llvm/CodeGen/ValueTypes.td | 186 +++++++------- llvm/include/llvm/Support/MachineValueType.h | 274 +++++++++++++-------- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- llvm/lib/CodeGen/ValueTypes.cpp | 26 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 12 +- llvm/lib/Target/X86/X86InstrAVX512.td | 6 +- llvm/lib/Target/X86/X86InstrSSE.td | 4 +- llvm/test/TableGen/intrinsic-varargs.td | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 12 + .../utils/gn/build/sync_source_lists_from_cmake.py | 4 +- .../gn/secondary/clang/unittests/Rewrite/BUILD.gn | 4 + llvm/utils/gn/secondary/libcxx/src/BUILD.gn | 69 +++--- 29 files changed, 639 insertions(+), 479 deletions(-) create mode 100644 libcxx/src/condition_variable_destructor.cpp create mode 100644 libcxx/src/mutex_destructor.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (67f5b19 -> 13881ea)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/base-artifacts. discards 67f5b19 0: update: llvm-linux: all new 13881ea 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (67f5b19) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 70 +- 02-build_llvm/console.log | 11980 +++++++++++++++++------------------ 03-build_linux/console.log | 808 +-- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 6 +- 06-update_baseline/console.log | 25 - console.log | 12891 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 12870 insertions(+), 12920 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-Oz updated (f35a3456eaf -> fb133b0aabe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-Oz in repository toolchain/ci/llvm-project. from f35a3456eaf [NFC] Return early for types with size zero adds 490bc46541c [NFC][PowerPC] Improve the for loop in Early Return adds 9f69052394a [InstCombine][NFCI] Fix test comments. adds 9ea5a322518 [X86] Teach selectScalarSSELoad to not narrow volatile loads. adds 9153501f074 [X86] Remove (vzext_movl (scalar_to_vector (load))) matchin [...] adds 59b39faa183 [IR] Add DISuprogram and DIE for a func decl adds 852f45ba88a gn build: Follow-up to r364491 "[GN] Update build files" adds 0f651685667 [clang] Add DISuprogram and DIE for a func decl adds e62456b3537 [lldb] [Plugins/SysV-x86_64] NetBSD is also using SysV ABI adds bfcc9968109 Fix GCC 4 build after r364464 adds 41825040f62 Fix -Wunused-variable warnings after r364464 adds a7cde103c18 [MachineFunction] Base support for call site info tracking adds 7b81b613686 Silence gcc warning after r364458 adds 8479240b0a6 [AMDGPU] Fix +DumpCode to print an entry label for the firs [...] adds 69ce1c13196 [GlobalISel] Allow multiple VRegs in ArgInfo. NFC adds c3dbe239779 [GlobalISel] Accept multiple vregs in lowerFormalArgs adds 8138996128c [GlobalISel] Accept multiple vregs for lowerCall's result adds 43fb5ae50c5 [GlobalISel] Accept multiple vregs for lowerCall's args adds 253b53b2ecf [AArch64 GlobalISel] Cleanup CallLowering. NFCI adds 74a50a723bf [GlobalISel] Remove [un]packRegs from IRTranslator adds d528bcd9657 [DebugInfo] Avoid register coalesing unsoundly changing DBG [...] adds 7eeeb5947ec [ISEL][X86] Tracking of registers that forward call arguments adds 687d47c2b0c [yaml2obj] - Allow overriding e_shentsize, e_shoff, e_shnum [...] adds 90e121fbe6b [X86][AVX] SimplifyDemandedVectorElts - combine PERMPD(x) - [...] adds 5cd77f98a1a [clangd] Address limitations in SelectionTree: adds d45b4f861e6 [X86][SSE] Regenerate v48 shuffle test on a variety of targets adds 5360589b7d0 [Attributor] Deducing existing nounwind attribute. adds cfe9d0fb2bb [Object/invalid.test] - Convert most of the sub tests to YAML. adds 22c96a966b1 IR: compare type attributes deeply when looking into functions. adds 3ca8f2b007c Add triple to a test I just added. adds 3b184cf7e10 [mips] Reformat MSA instruction definitions. NFC adds bf5fc620d95 [mips] Fix indentation and split long lines. NFC adds 8c35c438162 [mips] Add GPR_64 predicate to some mov[zn] instructions adds cbab10099d6 [clangd] No need to setTraversalScope in SemanticHighlighting. adds f4f608d1f49 [LLD][ELF] - Replace invalid-e_shnum.s with YAML based version. adds c5cff5d3d16 [X86] getFauxShuffle - add DemandedElts as a filter adds 02449f9c3cf [ARM] Tighten restrictions on use of SP in v8.1-M CSEL. adds e5ce56fb950 [ARM] Make coprocessor number restrictions consistent. adds ffb2b347ffb [ARM] Fix handling of zero offsets in LOB instructions. adds 1a3dc8f6784 [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases. adds 79dc930c131 [clang-tidy] Fix NDEBUG build [NFC] adds 71d3869f60c [Backend] Keep call site info valid through the backend adds 93a825c8fb9 [clangd] Fix a case where we fail to detect a header-declar [...] adds a056684c335 [docs][tools] Add missing "program" tags to rst files adds 7c83f0705a8 [mips] Add new items to the list of features unsupported by P5600 adds e9ec0b6f094 [mips] Mark pseudo select instructions by the `hasNoSchedul [...] adds c692a8dc51d [TargetLowering] SimplifyDemandedBits - use DemandedElts to [...] adds a0d45058ebb [DWARF] Handle the DW_OP_entry_value operand adds 408fc0849ea Revert r363658 "[SVE][IR] Scalable Vector IR Type with pr42 [...] adds 157b073fa54 [PowerPC][HTM] Fix disassembling buffer overflow for tabort [...] adds 93184302370 Provide hashers for string_view only if they are using the [...] adds d0e098696f9 [InstCombine] remove 'tmp' names and regenerate checks; NFC adds d44cb7a6567 [scudo][standalone] Introduce the C & C++ wrappers [fixed] adds 83e1a1e79b5 [TargetLowering] SimplifyDemandedVectorElts - add shift/rot [...] adds 7a9ca67fd55 [LiveRangeEdit] Fix build failure caused by the rL364536 adds a4771e9dfdb Bitcode: derive all types used from records instead of Values. adds 6b8a2515baa [clangd] Emit semantic highlighting tokens when the main AS [...] adds 92b32a90870 [docs][llvm-nm][llvm-objdump] Improve "See Also" section adds d6a46aff591 [LiveDebugValues] Emit the debug entry values adds 7d8274d54d0 Followup to revision 364545: Turns out that clang issues di [...] adds 3b77583e952 [Attr] Add "willreturn" function attribute adds 1339f74b8a3 [debug-info] Make a couple of tests more robust. adds 9f7f5858fe4 Recommit [PowerPC] Update P9 vector costs for insert/extrac [...] adds c3ab38eaa97 Revert Add github lockdown app to auto-close pull requests. adds 41e20d21015 [llvm-nm] Fix for BZ41711 - Class character for a symbol wi [...] adds 8747c5f4828 [ARM] Fix formatting issue in ARMISelLowering.cpp adds 74343eba37c [X86] getTargetVShiftByConstNode - reduce variable scope. NFCI. adds 3b4a667854e Add a sanity check to the domain socket tests. adds 0627b09863b [CodeGen] [SelectionDAG] More efficient code for X % C == 0 [...] adds e9a2f4fe2ca Use getConstantOperandAPInt instead of getConstantOperandVa [...] adds 152dd3b8542 [ARM] Move low overhead loop codegen tests into a separate [...] adds 32ef9292bea AMDGPU: Make fixing i1 copies robust against re-ordering adds a166b903d0e Fix lld build on Windows with MSVC due to C2461 adds 0a2b7b79fac Revert "[CodeGen] [SelectionDAG] More efficient code for X [...] adds 1fd1c609795 [X86] combineX86ShufflesRecursively - merge shuffles with m [...] adds 6b3f56b65fa [WebAssembly] Fix p2align in assembler. adds 774eabd0978 Revert "[LiveDebugValues] Emit the debug entry values" adds bb55ece2692 [OPENMP][NVPTX]Relax flush directive. adds 2dcd2c2493b [llvm-objdump] Update the doc for --disassemble-functions. adds 954014a0fac Add a missing '__uncvref_t' to the SFINAE constraints for o [...] adds f288cf9dfa1 [OPENMP]Generate correctly implicit flags for mapped data. adds bfd3f694805 [WebAssembly] AsmParser: better atomic inst detection adds c5486b23bc7 Correct the file path. NFC. adds bd34e50cf0a [NFC][CodeGen] Add negative test for X u% C == 0 fold (D63391) adds 1cf9e72cbc0 Update -analyze -scalar-evolution output for multiple exit [...] adds 6ed459fd41c Use "willreturn" in isGuaranteedToTransferExecutionToSuccessor adds c627aa2fa9c [PowerPC][NFC] Remove unused (and unsupported) fusion featu [...] adds f7a19f684bd [GN] Set exit code to 1 if changes are needed adds 564b03729b2 [GN] Update build file adds a95ca2b5ff1 [x86] prevent crashing from select narrowing with AVX512 adds 223df5b5402 [libcxxabi] Use an explicit list to export symbols from the dylib adds 22afca2ce02 [NFC][GVN] Pre-commit unary FNeg tests to fpmath.ll adds 7ecf1ec49a8 [x86] remove whitespace; NFC adds 559c6e17cd8 Make nrvo-string test more robust. adds fa36593f4c0 Convert line endings to LF. adds 8007ff1ab15 [compiler-rt] Rename lit.*.cfg.* -> lit.*.cfg.py.* adds 6e62a796d50 [GVN] Add support for unary FNeg to GVN pass adds 379a9f5e240 [sanitizer_common] Switch from zx_clock_get_new to zx_clock_get adds d9a59aeb049 [libFuzzer] Migrate to the new exception syscalls on Fuchsia adds 3b56e390dd1 Pattern match struct types in test case. adds 24dba1fe972 [WebAssembly] Enable an atomic.notify MC test adds 30cab5d6eef [NFC][GVNSink] Pre-commit unary FNeg test to fpmath.ll adds 4a8dc615346 [JITLink][MachO/x86-64] Add a testcase for X86_64_RELOC_GOT. adds a59cf878223 [NFC][APInt] Add (exhaustive) test for multiplicativeInverse() adds 29d05c005fa [CodeGen] [SelectionDAG] More efficient code for X % C == 0 [...] adds 13fde7a89a5 [analyzer] Fix clang-tidy crash on GCCAsmStmt adds c29abb50f29 Revert "[JITLink][MachO/x86-64] Add a testcase for X86_64_R [...] adds d11ea6518c1 hwasan: Teach the runtime to identify the local variable be [...] adds 5378afc02a3 hwasan: Use llvm.read_register intrinsic to read the PC on [...] adds 559b2e0187a hwasan: Fix an off-by-one error in PrintTagsAroundAddr. adds 4fcf0004fa7 [LangRef] Clarify codegen expectations for intrinsics with [...] adds ddc2804e1a5 Fix ASAN error caused by commit r364512. adds 92e625c2233 [InlineCost] make InlineCost assignable adds ecb7ac35f9d [GlobalISel][IRTranslator] Fix some PHI bugs related to jum [...] adds 9a89d657b1a Fixing a couple of wrong logical operator bugs. adds 5e66db6b8cd GlobalISel: Convert rest of MachineIRBuilder to using Register adds 1178dc3d0bf AMDGPU/GlobalISel: Convert to using Register adds c6fe8436e88 [PowerPC][NFC] Use `|=` to update `Simplified` flag adds 3018d1845b6 GlobalISel: Use Register adds 07fd88d7358 [AMDGPU] Packed thread ids in function call ABI adds 588a1709703 [NFC][PowerPC] Move XS*QP series instruction apart from XS* [...] adds 3b715d67dde [Support] Add fs::getUmask() function and change fs::setPer [...] adds 1c7aec1c936 [Support] Fix add fs::getUmask() patch adds e832adea0ff [X86] Remove some duplicate patterns that already exist as [...] adds 2adab5a1426 Silence gcc warning in testcase [NFC] adds cbb88a51699 [X86] Connect the output chain properly when combining vzex [...] adds 8be372b1901 [ARM] MVE vector shuffles adds be05b85db9f [ARM] Select MVE add and sub adds 9a92be1b355 [HardwareLoops] Loop counter guard intrinsic adds 62889b0ea54 [ARM] Select MVE fp add and sub adds 8ab8a60a1ec [CTU] Add missing statistics adds fc4102417b1 [ARM] Mark div and rem as expand for MVE adds 2bc48f503a1 [AVR] Don't look for the TargetFrameLowering in the FrameLo [...] adds 07e53fee145 [ARM] MVE loads and stores adds e662b6985a8 [DebugInfo] GSYM cleanups after D63104/r364427 adds 29ff1b4f465 [ARM] Fix integer UB in MVE load/store immediate handling. adds eb7080ac6e5 [ARM] Widening loads and narrowing stores adds 493a1202595 [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges adds 02e743586e9 [DebugInfo] Fix setStartAddress after r364637 adds fd0ad4b24d6 [ELF] Do not produce DT_JMPREL and DT_PLTGOT if .rela.plt i [...] adds ff70cbc8957 [ARM] MVE patterns for VABS and VNEG adds 28839440352 [ARM] Mark math routines as non-legal for MVE adds 9af44742538 [NFC][Codegen] Revisit test coverage for X % C == 0 fold adds 9dbdfe6b785 [ARM] Add MVE mul patterns adds a54e1a0f012 [X86] CombineShuffleWithExtract - only require 1 source to [...] adds 1d572ce3955 [AMDGPU][MC] Enabled constant expressions as operands of sendmsg adds 13d9c723c89 [NFC][NewGVN] Pre-commit unary FNeg test to fpmath.ll adds 405f8fc812c [OPENMP]Fix checks for DSA in simd constructs. adds 40b88e07e2d [Hexagon] driver uses out-of-date option name and binary name adds 9fab46ca0bd [NFC][Float2Int] Pre-commit unary FNeg test to basic.ll adds b7c31ff4a22 [OPENMP]Fix DSA for loop iteration variables in simd loops. adds d12966c0883 [AMDGPU][MC] Fix for sanitizer failure in 364645 adds 9f1dffdb024 [NFC][InstCombine] Shift amount reassociation: add flag pre [...] adds 176b9f65168 [llvm-cov[ Fix lcov coverage report contains functions from [...] adds e39e958da36 [ARM] Add support for the MVE long shift instructions adds 73f9d9aa64b [OPENMP]Fix top DSA for static members. adds e1eb25ff3e5 [AMDGPU][MC] Fix 2 for sanitizer failure in 364645 adds 3b4f086df4a [NFC][InstCombine] Shift amount reassociation: revisit flag [...] adds 633d222d30b [WebAssembly] Added visibility and ident directives to Wasm [...] adds 5cbff431782 [COFF] Fix .rsrc sections with differing permissions adds 0b8b4195371 [NFC][Codegen] Revisit test coverage for X % C == 0 fold on [...] adds 5be69ebe121 [TSan] Improve handling of stack pointer mangling in {set,l [...] adds 021d2f20933 Update CODE_OWNERS.txt for clang-doc adds 5f8b9092fff [ODRHash] Fix null pointer dereference for ObjC selectors w [...] adds 7108df964aa hwasan: Remove the old frame descriptor mechanism. adds 8864b4360aa Make sure the thread list is updated before you set the sto [...] adds 978a08c8854 [X86] CombineShuffleWithExtract - recurse through EXTRACT_S [...] adds 7d78e5cc811 [UpdateChecks] Add support for armv7-apple-darwin adds 9db6073381d [GDBRemote] Remove code that flushes GDB remote packets adds 93a290fdc97 [clang-doc] De-duplicate comments and locations adds 36c3d1312a0 [unittests][Support] Fix LLVM-Unit :: Support/./SupportTest [...] adds 62a627ae781 Re-apply r364600 with fixes. adds 70a8027c60f [llvm-ar] Document response file support in --help adds d900ef0a5b1 [clang-doc] Handle anonymous namespaces adds 4b733ca617e Default to Secure PLT on PPC for musl libc. adds 1c6337ca5ab [TSan] Fix build build breakage on Android adds 9a6cef74d8a [demangle] Support for C++2a char8_t adds ab4b2364e56 [GVNSink] Add unary FNeg support to GVNSink pass adds 642fe780abe Revert enabling frame pointer elimination on OpenBSD for now. adds 30e5cf1d8f3 [NewGVN] Add unary FNeg support to NewGVN pass adds 597ba180086 [WebAssembly] Assembler: Improve section parsing. adds fc222e23cae [WebAssembly] Assembler: Allow offsets and p2align in symbol load. adds 1242d8f333a [OPENMP]Improve analysis of implicit captures. adds 573b241c68a [Lanai] auto-generate complete test checks; NFC adds b671535983f [NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll adds f2128b28cdb Get the expression parser to handle missing weak symbols. M [...] adds 9126c84f50f [x86] remove stale comment about cmov; NFC adds 35bcba4fae8 [WebAssembly] Allow @object in .type directives. adds 319c87d94fd [WebAssembly] Assembler: support .int16/32/64 directives. adds caf4cee6fe8 [clang][test][NFC] Explicitly specify clang ABI in AST Dumper test adds 69d9c314337 AMDGPU: Add baseline test for packed shufflevector adds da47e2cac38 Revert "[clang][NewPM] Fix broken profile test" adds 1504b6ee7ea [IndVars] Remove a bit of manual constant folding [NFC] adds ade51624327 AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics adds 6aafb3068f9 AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas adds 5ea3c9adb27 AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics adds b416d5fc8b8 AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics adds adb1f21e521 AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics adds fd82cf4f4d0 AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec adds be4148062b1 [TSan] Attempt to fix linker error for Linux on AArch64 adds 0d452097571 AMDGPU/GlobalISel: RegBankSelect for update.dpp adds a83e94ebf26 Use const auto * adds 7889d4ce66f AMDGPU/GlobalISel: Add some more tests for icmp select adds 765eba38c8d [Driver] Fix style issues of --print-supported-cpus after D63105 adds b72664fd21c Partial revert of "[llvm-ar] Document response file support [...] adds 2d756c4feb6 [LFTR] Fix post-inc pointer IV with truncated exit count (PR41998) adds 9e9eb62f9fd [APInt] Fix getBitsNeeded for INT_MIN values adds fe107fcde4d [IR][Patternmatch] Add m_SpecificInt_ULT() predicate adds e3a94ba4a92 [InstCombine] Shift amount reassociation (PR42391) adds 61a8b62b4c9 [LFTR] Remove unnecessary latch check; NFCI adds 77dc1e85683 [InstCombine] canonicalize fmin/fmax to LLVM intrinsics min [...] adds 8023c844338 [LFTR] Rephrase getLoopTest into "based-on" check; NFCI adds 6293cd05045 Replace tabs with spaces. adds 4d0feb28ecb [SelectionDAG] Use the memory VT instead of result VT for F [...] adds 725a8a5dc43 [X86] Custom lower AVX masked loads to masked load and vsel [...] adds 2d2cb77e45d [ADT] Implement llvm::bsearch() with std::partition_point() adds 78ee2fbf984 Cleanup: llvm::bsearch -> llvm::partition_point after r364719 adds 706b48251f6 [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics adds 135cf982e8e Revert "[GDBRemote] Remove code that flushes GDB remote packets" adds bb0b44deaab Clean up MSVC visualization of LLVM pointer types adds fb133b0aabe Various tweaks to MSVC natvis visualizers No new revisions were added by this update. Summary of changes: .github/lockdown.yml | 33 - clang-tools-extra/CODE_OWNERS.TXT | 4 + clang-tools-extra/clang-doc/Representation.cpp | 39 + clang-tools-extra/clang-doc/Representation.h | 50 + clang-tools-extra/clang-doc/Serialize.cpp | 75 +- clang-tools-extra/clang-doc/tool/ClangDocMain.cpp | 7 +- .../clang-tidy/utils/TransformerClangTidyCheck.cpp | 2 + clang-tools-extra/clangd/ClangdServer.cpp | 19 +- clang-tools-extra/clangd/ClangdServer.h | 11 +- clang-tools-extra/clangd/Selection.cpp | 154 +- clang-tools-extra/clangd/SemanticHighlighting.cpp | 3 +- clang-tools-extra/clangd/SemanticHighlighting.h | 4 +- clang-tools-extra/clangd/index/Symbol.cpp | 4 +- clang-tools-extra/clangd/index/dex/PostingList.cpp | 8 +- clang-tools-extra/clangd/refactor/Rename.cpp | 25 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 41 +- .../clangd/unittests/SelectionTests.cpp | 61 +- .../clangd/unittests/SemanticHighlightingTests.cpp | 26 + .../unittests/clang-doc/MergeTest.cpp | 36 +- .../unittests/clang-doc/SerializeTest.cpp | 1 + clang/include/clang/AST/Decl.h | 2 + clang/include/clang/Driver/Options.td | 6 +- clang/lib/AST/ODRHash.cpp | 7 +- clang/lib/CodeGen/BackendUtil.cpp | 6 - clang/lib/CodeGen/CGDebugInfo.cpp | 38 +- clang/lib/CodeGen/CGDebugInfo.h | 10 +- clang/lib/CodeGen/CGExpr.cpp | 14 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 26 +- clang/lib/CrossTU/CrossTranslationUnit.cpp | 8 +- clang/lib/Driver/Driver.cpp | 20 +- clang/lib/Driver/ToolChains/Clang.cpp | 13 - clang/lib/Driver/ToolChains/Hexagon.cpp | 4 +- clang/lib/Frontend/CompilerInvocation.cpp | 2 +- clang/lib/Sema/SemaOpenMP.cpp | 82 +- clang/lib/StaticAnalyzer/Core/CoreEngine.cpp | 5 + clang/lib/Tooling/Syntax/Tokens.cpp | 8 +- .../AST/ast-dump-record-definition-data-json.cpp | 2 +- clang/test/Analysis/egraph-asm-goto-no-crash.cpp | 26 + clang/test/CodeGen/debug-info-extern-call.c | 15 + clang/test/CodeGenObjC/strong-in-c-struct.m | 28 +- clang/test/Driver/frame-pointer-elim.c | 13 - clang/test/Driver/print-supported-cpus.c | 36 +- clang/test/Modules/odr_hash.mm | 31 + .../distribute_parallel_for_default_messages.cpp | 8 +- ...stribute_parallel_for_simd_default_messages.cpp | 8 +- clang/test/OpenMP/nvptx_lambda_capturing.cpp | 4 +- clang/test/OpenMP/simd_loop_messages.cpp | 32 +- clang/test/OpenMP/target_codegen.cpp | 4 +- clang/test/OpenMP/target_firstprivate_codegen.cpp | 12 +- clang/test/OpenMP/target_map_codegen.cpp | 40 +- clang/test/OpenMP/target_parallel_codegen.cpp | 4 +- clang/test/OpenMP/target_parallel_for_codegen.cpp | 4 +- .../target_parallel_for_default_messages.cpp | 4 +- .../OpenMP/target_parallel_for_simd_codegen.cpp | 4 +- .../target_parallel_for_simd_default_messages.cpp | 4 +- clang/test/OpenMP/target_simd_codegen.cpp | 4 +- clang/test/OpenMP/target_teams_codegen.cpp | 6 +- .../OpenMP/target_teams_distribute_codegen.cpp | 6 +- ...rget_teams_distribute_firstprivate_messages.cpp | 2 +- .../target_teams_distribute_simd_codegen.cpp | 6 +- .../teams_distribute_firstprivate_messages.cpp | 2 +- .../teams_distribute_lastprivate_messages.cpp | 2 +- ...stribute_parallel_for_firstprivate_messages.cpp | 2 +- ...istribute_parallel_for_lastprivate_messages.cpp | 2 +- ..._distribute_parallel_for_reduction_messages.cpp | 4 +- ...stribute_parallel_for_simd_aligned_messages.cpp | 2 +- ...ute_parallel_for_simd_firstprivate_messages.cpp | 2 +- ...bute_parallel_for_simd_lastprivate_messages.cpp | 2 +- ...istribute_parallel_for_simd_linear_messages.cpp | 4 +- ...ribute_parallel_for_simd_reduction_messages.cpp | 4 +- .../OpenMP/teams_distribute_reduction_messages.cpp | 4 +- .../teams_distribute_simd_aligned_messages.cpp | 2 +- ...teams_distribute_simd_firstprivate_messages.cpp | 2 +- .../teams_distribute_simd_lastprivate_messages.cpp | 2 +- .../teams_distribute_simd_linear_messages.cpp | 4 +- .../teams_distribute_simd_reduction_messages.cpp | 4 +- clang/test/OpenMP/teams_firstprivate_messages.cpp | 2 +- clang/test/OpenMP/teams_reduction_messages.cpp | 4 +- clang/test/Profile/gcc-flag-compatibility.c | 12 +- clang/tools/driver/cc1_main.cpp | 9 +- clang/utils/ClangVisualizers/clang.natvis | 54 +- compiler-rt/lib/fuzzer/FuzzerUtilFuchsia.cpp | 54 +- compiler-rt/lib/hwasan/hwasan.cpp | 36 +- compiler-rt/lib/hwasan/hwasan.h | 8 +- compiler-rt/lib/hwasan/hwasan_report.cpp | 96 +- .../lib/sanitizer_common/sanitizer_fuchsia.cc | 2 +- .../lib/sanitizer_common/sanitizer_ring_buffer.h | 2 +- .../lib/sanitizer_common/sanitizer_symbolizer.cc | 10 + .../lib/sanitizer_common/sanitizer_symbolizer.h | 28 + .../sanitizer_symbolizer_internal.h | 12 +- .../sanitizer_symbolizer_libcdep.cc | 79 +- compiler-rt/lib/scudo/standalone/CMakeLists.txt | 75 +- compiler-rt/lib/scudo/standalone/flags_parser.cc | 1 + compiler-rt/lib/scudo/standalone/flags_parser.h | 1 - .../lib/scudo/standalone/tests/CMakeLists.txt | 44 +- .../lib/scudo/standalone/tests/wrappers_c_test.cc | 225 ++ .../scudo/standalone/tests/wrappers_cpp_test.cc | 117 + compiler-rt/lib/scudo/standalone/tsd.h | 5 + compiler-rt/lib/scudo/standalone/wrappers_c.cc | 39 + compiler-rt/lib/scudo/standalone/wrappers_c.h | 52 + compiler-rt/lib/scudo/standalone/wrappers_c.inc | 176 ++ .../lib/scudo/standalone/wrappers_c_bionic.cc | 49 + .../lib/scudo/standalone/wrappers_c_checks.h | 67 + compiler-rt/lib/scudo/standalone/wrappers_cpp.cc | 107 + compiler-rt/lib/tsan/rtl/tsan_interceptors.cc | 3 + compiler-rt/lib/tsan/rtl/tsan_platform.h | 1 + compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc | 34 + compiler-rt/lib/tsan/rtl/tsan_platform_mac.cc | 4 + compiler-rt/lib/tsan/rtl/tsan_rtl_aarch64.S | 8 - compiler-rt/test/asan/CMakeLists.txt | 24 +- .../Android/{lit.local.cfg => lit.local.cfg.py} | 0 .../Darwin/{lit.local.cfg => lit.local.cfg.py} | 0 .../Helpers/{lit.local.cfg => lit.local.cfg.py} | 0 .../Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Posix/{lit.local.cfg => lit.local.cfg.py} | 0 .../Windows/{lit.local.cfg => lit.local.cfg.py} | 0 .../Unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 compiler-rt/test/asan/{lit.cfg => lit.cfg.py} | 2 +- .../asan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/builtins/CMakeLists.txt | 8 +- .../Darwin/{lit.local.cfg => lit.local.cfg.py} | 0 .../test/builtins/Unit/{lit.cfg => lit.cfg.py} | 2 +- .../Unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/builtins/{lit.cfg => lit.cfg.py} | 0 .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/cfi/CMakeLists.txt | 8 +- .../icall/{lit.local.cfg => lit.local.cfg.py} | 0 .../cross-dso/{lit.local.cfg => lit.local.cfg.py} | 0 .../cfi/icall/{lit.local.cfg => lit.local.cfg.py} | 0 compiler-rt/test/cfi/{lit.cfg => lit.cfg.py} | 0 .../cfi/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/crt/CMakeLists.txt | 4 +- compiler-rt/test/crt/{lit.cfg => lit.cfg.py} | 0 .../crt/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/dfsan/CMakeLists.txt | 4 +- compiler-rt/test/dfsan/{lit.cfg => lit.cfg.py} | 0 .../dfsan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/fuzzer/CMakeLists.txt | 12 +- compiler-rt/test/fuzzer/{lit.cfg => lit.cfg.py} | 0 .../fuzzer/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- .../unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 compiler-rt/test/gwp_asan/CMakeLists.txt | 12 +- compiler-rt/test/gwp_asan/{lit.cfg => lit.cfg.py} | 0 .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- .../unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 compiler-rt/test/hwasan/CMakeLists.txt | 4 +- .../Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Posix/{lit.local.cfg => lit.local.cfg.py} | 0 .../test/hwasan/TestCases/stack-uar-dynamic.c | 23 + .../test/hwasan/TestCases/stack-uar-realign.c | 20 + compiler-rt/test/hwasan/TestCases/stack-uar.c | 23 +- compiler-rt/test/hwasan/{lit.cfg => lit.cfg.py} | 0 .../hwasan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/interception/CMakeLists.txt | 4 +- .../Unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 .../test/{lit.common.cfg => lit.common.cfg.py} | 2 +- compiler-rt/test/lit.common.configured.in | 2 +- compiler-rt/test/lsan/CMakeLists.txt | 8 +- .../Darwin/{lit.local.cfg => lit.local.cfg.py} | 0 .../Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Posix/{lit.local.cfg => lit.local.cfg.py} | 0 .../lsan/{lit.common.cfg => lit.common.cfg.py} | 2 +- .../lsan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/msan/CMakeLists.txt | 8 +- .../msan/Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 compiler-rt/test/msan/{lit.cfg => lit.cfg.py} | 0 .../msan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/profile/CMakeLists.txt | 4 +- .../Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Posix/{lit.local.cfg => lit.local.cfg.py} | 0 compiler-rt/test/profile/{lit.cfg => lit.cfg.py} | 2 +- .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/safestack/CMakeLists.txt | 4 +- compiler-rt/test/safestack/{lit.cfg => lit.cfg.py} | 0 .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/sanitizer_common/CMakeLists.txt | 8 +- .../Darwin/{lit.local.cfg => lit.local.cfg.py} | 0 .../FreeBSD/{lit.local.cfg => lit.local.cfg.py} | 0 .../Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../NetBSD/{lit.local.cfg => lit.local.cfg.py} | 0 .../Posix/{lit.local.cfg => lit.local.cfg.py} | 0 .../Unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 .../{lit.common.cfg => lit.common.cfg.py} | 0 .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/scudo/CMakeLists.txt | 8 +- compiler-rt/test/scudo/{lit.cfg => lit.cfg.py} | 0 .../scudo/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/scudo/standalone/CMakeLists.txt | 4 +- .../unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 0 compiler-rt/test/shadowcallstack/CMakeLists.txt | 4 +- .../test/shadowcallstack/{lit.cfg => lit.cfg.py} | 0 .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/tsan/CMakeLists.txt | 16 +- .../Darwin/{lit.local.cfg => lit.local.cfg.py} | 0 .../tsan/Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Unit/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- .../libcxx/{lit.local.cfg => lit.local.cfg.py} | 0 .../{lit.local.cfg => lit.local.cfg.py} | 0 compiler-rt/test/tsan/{lit.cfg => lit.cfg.py} | 4 +- .../tsan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/ubsan/CMakeLists.txt | 8 +- .../Misc/Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../Function/{lit.local.cfg => lit.local.cfg.py} | 0 .../Linux/{lit.local.cfg => lit.local.cfg.py} | 0 .../ubsan/{lit.common.cfg => lit.common.cfg.py} | 2 +- .../ubsan/{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/ubsan_minimal/CMakeLists.txt | 4 +- .../{lit.common.cfg => lit.common.cfg.py} | 2 +- .../{lit.site.cfg.in => lit.site.cfg.py.in} | 2 +- compiler-rt/test/xray/CMakeLists.txt | 8 +- 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+ llvm/lib/AsmParser/LLLexer.cpp | 2 +- llvm/lib/AsmParser/LLParser.cpp | 14 +- llvm/lib/AsmParser/LLToken.h | 2 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 429 ++- llvm/lib/Bitcode/Reader/ValueList.cpp | 12 +- llvm/lib/Bitcode/Reader/ValueList.h | 28 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 7 +- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 4 + llvm/lib/CodeGen/AsmPrinter/DebugLocEntry.h | 1 + llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 21 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 5 + llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp | 17 + llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h | 15 + llvm/lib/CodeGen/ExecutionDomainFix.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 61 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 138 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 14 +- llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 9 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 100 +- llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 20 +- llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 44 +- llvm/lib/CodeGen/HardwareLoops.cpp | 121 +- llvm/lib/CodeGen/InlineSpiller.cpp | 2 + llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 + llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 47 + llvm/lib/CodeGen/MIRPrinter.cpp | 37 + llvm/lib/CodeGen/MachineFunction.cpp | 23 + llvm/lib/CodeGen/MachineOutliner.cpp | 12 +- llvm/lib/CodeGen/MachineVerifier.cpp | 4 + llvm/lib/CodeGen/PeepholeOptimizer.cpp | 2 + llvm/lib/CodeGen/RegisterCoalescer.cpp | 87 +- .../CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 159 +- llvm/lib/CodeGen/TargetInstrInfo.cpp | 10 +- llvm/lib/CodeGen/XRayInstrumentation.cpp | 2 + llvm/lib/DebugInfo/DWARF/DWARFDebugAranges.cpp | 2 +- llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp | 4 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp | 8 +- llvm/lib/DebugInfo/DWARF/DWARFExpression.cpp | 20 +- llvm/lib/DebugInfo/DWARF/DWARFUnitIndex.cpp | 4 +- llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp | 3 +- llvm/lib/DebugInfo/GSYM/InlineInfo.cpp | 2 +- llvm/lib/DebugInfo/GSYM/LLVMBuild.txt | 2 +- llvm/lib/DebugInfo/GSYM/Range.cpp | 52 +- llvm/lib/IR/AsmWriter.cpp | 5 +- llvm/lib/IR/Attributes.cpp | 2 + llvm/lib/IR/DataLayout.cpp | 4 +- llvm/lib/IR/DebugInfoMetadata.cpp | 21 +- llvm/lib/IR/Function.cpp | 5 +- llvm/lib/IR/LLVMContextImpl.h | 2 +- llvm/lib/IR/Type.cpp | 13 +- llvm/lib/IR/Verifier.cpp | 43 +- llvm/lib/MC/MCParser/WasmAsmParser.cpp | 97 +- llvm/lib/ObjectYAML/ELFYAML.cpp | 5 + llvm/lib/ProfileData/InstrProf.cpp | 11 +- llvm/lib/Support/APInt.cpp | 7 +- llvm/lib/Support/Unix/Path.inc | 14 +- llvm/lib/Support/Windows/Path.inc | 7 +- llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 75 +- llvm/lib/Target/AArch64/AArch64CallLowering.h | 7 +- llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp | 12 +- llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 29 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 28 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 167 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 4 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 262 +- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 +- llvm/lib/Target/AMDGPU/SIDefines.h | 13 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 97 +- llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 21 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 108 + llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 42 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 8 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 22 + llvm/lib/Target/ARM/ARMCallLowering.cpp | 89 +- llvm/lib/Target/ARM/ARMCallLowering.h | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 353 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 8 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 31 + llvm/lib/Target/ARM/ARMInstrMVE.td | 223 +- llvm/lib/Target/ARM/ARMInstrNEON.td | 224 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 25 +- llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 19 +- llvm/lib/Target/ARM/ARMRegisterInfo.td | 12 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 4 +- .../Target/ARM/Disassembler/ARMDisassembler.cpp | 43 +- .../Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 11 +- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 2 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 19 +- llvm/lib/Target/Mips/MipsCallLowering.h | 2 +- llvm/lib/Target/Mips/MipsCondMov.td | 22 +- llvm/lib/Target/Mips/MipsInstrInfo.td | 10 +- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 78 +- llvm/lib/Target/Mips/MipsScheduleP5600.td | 6 +- .../PowerPC/Disassembler/PPCDisassembler.cpp | 6 - llvm/lib/Target/PowerPC/PPC.td | 5 +- llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp | 8 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 +- llvm/lib/Target/PowerPC/PPCInstrHTM.td | 38 +- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 - llvm/lib/Target/PowerPC/PPCInstrVSX.td | 66 +- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 2 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 2 - llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 4 +- llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 - llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 29 + .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 112 +- .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 10 +- llvm/lib/Target/X86/X86CallLowering.cpp | 27 +- llvm/lib/Target/X86/X86CallLowering.h | 2 +- llvm/lib/Target/X86/X86ExpandPseudo.cpp | 1 + llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 29 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 163 +- llvm/lib/Target/X86/X86ISelLowering.h | 3 +- llvm/lib/Target/X86/X86InstrAVX512.td | 6 +- llvm/lib/Target/X86/X86InstrFMA3Info.cpp | 4 +- llvm/lib/Target/X86/X86InstrSSE.td | 5 - llvm/lib/TextAPI/MachO/InterfaceFile.cpp | 16 +- llvm/lib/Transforms/IPO/Attributor.cpp | 95 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 13 + .../Transforms/InstCombine/InstCombineShifts.cpp | 48 + .../Instrumentation/HWAddressSanitizer.cpp | 106 +- llvm/lib/Transforms/Scalar/GVN.cpp | 1 + llvm/lib/Transforms/Scalar/GVNSink.cpp | 1 + llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 143 +- llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp | 4 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 1 + llvm/lib/Transforms/Utils/CodeExtractor.cpp | 1 + llvm/lib/Transforms/Utils/FunctionComparator.cpp | 13 + llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 38 +- .../Analysis/CostModel/PowerPC/insert_extract.ll | 48 +- llvm/test/Analysis/ScalarEvolution/trip-count14.ll | 4 + llvm/test/Bitcode/attributes.ll | 11 +- llvm/test/Bitcode/compatibility.ll | 4 - llvm/test/Bitcode/invalid.test | 2 +- .../GlobalISel/arm64-irtranslator-switch.ll | 1141 ++++++++ .../AArch64/GlobalISel/arm64-irtranslator.ll | 13 +- .../AArch64/GlobalISel/call-translator-cse.ll | 10 +- .../AArch64/GlobalISel/call-translator-ios.ll | 9 +- .../CodeGen/AArch64/GlobalISel/call-translator.ll | 44 +- llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll | 12 +- .../CodeGen/AArch64/urem-seteq-vec-nonsplat.ll | 670 ++++- llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll | 181 +- llvm/test/CodeGen/AArch64/urem-seteq.ll | 186 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir | 112 +- .../GlobalISel/irtranslator-amdgpu_kernel.ll | 8 +- .../GlobalISel/regbankselect-amdgcn.atomic.dec.mir | 80 + .../GlobalISel/regbankselect-amdgcn.atomic.inc.mir | 80 + .../GlobalISel/regbankselect-amdgcn.div.fmas.mir | 106 + .../GlobalISel/regbankselect-amdgcn.ds.append.mir | 36 + .../regbankselect-amdgcn.ds.bpermute.mir | 24 + .../GlobalISel/regbankselect-amdgcn.ds.consume.mir | 36 + .../GlobalISel/regbankselect-amdgcn.ds.fmax.mir | 83 + .../GlobalISel/regbankselect-amdgcn.ds.fmin.mir | 83 + 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llvm/test/CodeGen/Thumb2/mve-loadstore.ll | 175 ++ llvm/test/CodeGen/Thumb2/mve-shuffle.ll | 624 +++++ llvm/test/CodeGen/Thumb2/mve-simple-arith.ll | 385 +++ llvm/test/CodeGen/Thumb2/mve-vdup.ll | 138 + llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll | 127 + llvm/test/CodeGen/X86/avx512-select.ll | 58 + llvm/test/CodeGen/X86/call-site-info-output.ll | 44 + llvm/test/CodeGen/X86/combine-sdiv.ll | 480 ++-- llvm/test/CodeGen/X86/combine-udiv.ll | 46 +- llvm/test/CodeGen/X86/fold-load-unops.ll | 34 + llvm/test/CodeGen/X86/jump_sign.ll | 10 +- llvm/test/CodeGen/X86/known-signbits-vector.ll | 53 +- .../CodeGen/X86/machinesink-merge-debuginfo.ll | 14 +- .../test/CodeGen/X86/machinesink-null-debuginfo.ll | 3 +- ...ower-of-two-or-zero-when-comparing-with-zero.ll | 30 +- .../test/CodeGen/X86/shuffle-vs-trunc-512-widen.ll | 31 +- llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll | 31 +- llvm/test/CodeGen/X86/urem-seteq-optsize.ll | 21 +- llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll | 2884 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llvm/test/MC/AMDGPU/sopp-err.s | 103 +- llvm/test/MC/AMDGPU/sopp.s | 126 +- llvm/test/MC/ARM/coprocessors.s | 74 + llvm/test/MC/ARM/diagnostics.s | 24 +- llvm/test/MC/ARM/mve-misc.s | 4 + llvm/test/MC/ARM/thumb2-diagnostics.s | 4 +- llvm/test/MC/ARM/thumbv8.1m.s | 20 + llvm/test/MC/ARM/v8_IT_manual.s | 928 +++---- .../test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt | 4 +- llvm/test/MC/Disassembler/AMDGPU/sopp_vi.txt | 23 +- llvm/test/MC/Disassembler/ARM/coprocessors-arm.txt | 68 + .../MC/Disassembler/ARM/coprocessors-thumb.txt | 70 + llvm/test/MC/Disassembler/ARM/mve-misc.txt | 46 +- llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt | 8 +- llvm/test/MC/Disassembler/ARM/mve-scalar-shift.txt | 2 +- llvm/test/MC/Disassembler/ARM/thumb2-v8.1m.txt | 18 + llvm/test/MC/Disassembler/ARM/thumbv8.1m.s | 16 +- .../Disassembler/PowerPC/ppc64-encoding-p8htm.txt | 43 + llvm/test/MC/WebAssembly/atomics-encodings.s | 99 +- llvm/test/MC/WebAssembly/basic-assembly.s | 92 +- llvm/test/MC/WebAssembly/reloc-pic.s | 4 +- llvm/test/MC/WebAssembly/simd-encodings.s | 4 +- llvm/test/Object/Inputs/invalid-bad-rel-type.elf | Bin 845 -> 0 bytes llvm/test/Object/Inputs/invalid-buffer.elf | 1 - llvm/test/Object/Inputs/invalid-rel-sym.elf | Bin 496 -> 0 bytes llvm/test/Object/Inputs/invalid-section-index.elf | Bin 536 -> 0 bytes llvm/test/Object/Inputs/invalid-section-size.elf | Bin 584 -> 0 bytes llvm/test/Object/Inputs/invalid-sections-num.elf | Bin 528 -> 0 bytes llvm/test/Object/Inputs/invalid-sh_entsize.elf | Bin 1736 -> 0 bytes .../test/Object/Inputs/invalid-strtab-non-null.elf | Bin 536 -> 0 bytes llvm/test/Object/Inputs/invalid-strtab-type.elf | Bin 536 -> 0 bytes .../Object/Inputs/invalid-strtab-zero-size.elf | Bin 494 -> 0 bytes .../Object/Inputs/invalid-symbol-table-size.elf | Bin 536 -> 0 bytes llvm/test/Object/Inputs/invalid-xindex-size.elf | Bin 624 -> 0 bytes llvm/test/Object/invalid.test | 392 ++- llvm/test/Transforms/Float2Int/basic.ll | 16 + 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llvm/unittests/ADT/APIntTest.cpp | 34 +- llvm/unittests/ADT/STLExtrasTest.cpp | 21 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 3 + llvm/unittests/DebugInfo/GSYM/CMakeLists.txt | 5 - llvm/unittests/DebugInfo/GSYM/GSYMTest.cpp | 125 +- llvm/unittests/IR/CMakeLists.txt | 1 - llvm/unittests/IR/PatternMatch.cpp | 21 + llvm/unittests/IR/VectorTypesTest.cpp | 164 -- llvm/unittests/Support/Path.cpp | 58 +- llvm/utils/LLVMVisualizers/llvm.natvis | 19 +- llvm/utils/UpdateTestChecks/asm.py | 9 + .../utils/gn/build/sync_source_lists_from_cmake.py | 14 +- .../clang/lib/Tooling/DependencyScanning/BUILD.gn | 1 + .../gn/secondary/compiler-rt/test/hwasan/BUILD.gn | 4 +- .../gn/secondary/llvm/lib/DebugInfo/GSYM/BUILD.gn | 3 - llvm/utils/gn/secondary/llvm/test/BUILD.gn | 1 - llvm/utils/gn/secondary/llvm/unittests/BUILD.gn | 1 + .../llvm/unittests/DebugInfo/GSYM/BUILD.gn | 17 + llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn | 1 - openmp/libomptarget/deviceRTLs/nvptx/src/sync.cu | 2 +- .../deviceRTLs/nvptx/test/parallel/flush.c | 35 + 669 files changed, 28014 insertions(+), 6170 deletions(-) delete mode 100644 .github/lockdown.yml create mode 100644 clang/test/Analysis/egraph-asm-goto-no-crash.cpp create mode 100644 clang/test/CodeGen/debug-info-extern-call.c create mode 100644 compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cc create mode 100644 compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cc create mode 100644 compiler-rt/lib/scudo/standalone/wrappers_c.cc create mode 100644 compiler-rt/lib/scudo/standalone/wrappers_c.h create mode 100644 compiler-rt/lib/scudo/standalone/wrappers_c.inc create mode 100644 compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cc create mode 100644 compiler-rt/lib/scudo/standalone/wrappers_c_checks.h create mode 100644 compiler-rt/lib/scudo/standalone/wrappers_cpp.cc rename compiler-rt/test/asan/TestCases/Android/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/asan/TestCases/Darwin/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/asan/TestCases/Helpers/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/asan/TestCases/Linux/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/asan/TestCases/Posix/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/asan/TestCases/Windows/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/asan/Unit/{lit.site.cfg.in => lit.site.cfg.py.in} (100%) rename compiler-rt/test/asan/{lit.cfg => lit.cfg.py} (99%) rename compiler-rt/test/asan/{lit.site.cfg.in => lit.site.cfg.py.in} (89%) rename compiler-rt/test/builtins/TestCases/Darwin/{lit.local.cfg => lit.local.cfg. [...] rename compiler-rt/test/builtins/Unit/{lit.cfg => lit.cfg.py} (98%) rename compiler-rt/test/builtins/Unit/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/builtins/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/builtins/{lit.site.cfg.in => lit.site.cfg.py.in} (97%) rename compiler-rt/test/cfi/cross-dso/icall/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/cfi/cross-dso/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/cfi/icall/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/cfi/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/cfi/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/crt/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/crt/{lit.site.cfg.in => lit.site.cfg.py.in} (88%) rename compiler-rt/test/dfsan/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/dfsan/{lit.site.cfg.in => lit.site.cfg.py.in} (85%) rename compiler-rt/test/fuzzer/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/fuzzer/{lit.site.cfg.in => lit.site.cfg.py.in} (99%) rename compiler-rt/test/fuzzer/unit/{lit.site.cfg.in => lit.site.cfg.py.in} (100%) rename compiler-rt/test/gwp_asan/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/gwp_asan/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/gwp_asan/unit/{lit.site.cfg.in => lit.site.cfg.py.in} (100%) rename compiler-rt/test/hwasan/TestCases/Linux/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/hwasan/TestCases/Posix/{lit.local.cfg => lit.local.cfg.py} (100%) create mode 100644 compiler-rt/test/hwasan/TestCases/stack-uar-dynamic.c create mode 100644 compiler-rt/test/hwasan/TestCases/stack-uar-realign.c rename compiler-rt/test/hwasan/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/hwasan/{lit.site.cfg.in => lit.site.cfg.py.in} (87%) rename compiler-rt/test/interception/Unit/{lit.site.cfg.in => lit.site.cfg.py.in} (100%) rename compiler-rt/test/{lit.common.cfg => lit.common.cfg.py} (99%) rename compiler-rt/test/lsan/TestCases/Darwin/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/lsan/TestCases/Linux/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/lsan/TestCases/Posix/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/lsan/{lit.common.cfg => lit.common.cfg.py} (98%) rename compiler-rt/test/lsan/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/msan/Linux/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/msan/Unit/{lit.site.cfg.in => lit.site.cfg.py.in} (100%) rename compiler-rt/test/msan/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/msan/{lit.site.cfg.in => lit.site.cfg.py.in} (87%) rename compiler-rt/test/profile/Linux/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/profile/Posix/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/profile/{lit.cfg => lit.cfg.py} (98%) rename compiler-rt/test/profile/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/safestack/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/safestack/{lit.site.cfg.in => lit.site.cfg.py.in} (97%) rename compiler-rt/test/sanitizer_common/TestCases/Darwin/{lit.local.cfg => lit.lo [...] rename compiler-rt/test/sanitizer_common/TestCases/FreeBSD/{lit.local.cfg => lit.l [...] rename compiler-rt/test/sanitizer_common/TestCases/Linux/{lit.local.cfg => lit.loc [...] rename compiler-rt/test/sanitizer_common/TestCases/NetBSD/{lit.local.cfg => lit.lo [...] rename compiler-rt/test/sanitizer_common/TestCases/Posix/{lit.local.cfg => lit.loc [...] rename compiler-rt/test/sanitizer_common/Unit/{lit.site.cfg.in => lit.site.cfg.py. [...] rename compiler-rt/test/sanitizer_common/{lit.common.cfg => lit.common.cfg.py} (100%) rename compiler-rt/test/sanitizer_common/{lit.site.cfg.in => lit.site.cfg.py.in} (96%) rename compiler-rt/test/scudo/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/scudo/{lit.site.cfg.in => lit.site.cfg.py.in} (84%) rename compiler-rt/test/scudo/standalone/unit/{lit.site.cfg.in => lit.site.cfg.py. [...] rename compiler-rt/test/shadowcallstack/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/shadowcallstack/{lit.site.cfg.in => lit.site.cfg.py.in} (97%) rename compiler-rt/test/tsan/Darwin/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/tsan/Linux/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/tsan/Unit/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/tsan/libcxx/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/tsan/libdispatch/{lit.local.cfg => lit.local.cfg.py} (100%) rename compiler-rt/test/tsan/{lit.cfg => lit.cfg.py} (98%) rename compiler-rt/test/tsan/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/ubsan/TestCases/Misc/Linux/{lit.local.cfg => lit.local.cfg [...] rename compiler-rt/test/ubsan/TestCases/TypeCheck/Function/{lit.local.cfg => lit.l [...] rename compiler-rt/test/ubsan/TestCases/TypeCheck/Linux/{lit.local.cfg => lit.loca [...] rename compiler-rt/test/ubsan/{lit.common.cfg => lit.common.cfg.py} (98%) rename compiler-rt/test/ubsan/{lit.site.cfg.in => lit.site.cfg.py.in} (98%) rename compiler-rt/test/ubsan_minimal/{lit.common.cfg => lit.common.cfg.py} (97%) rename compiler-rt/test/ubsan_minimal/{lit.site.cfg.in => lit.site.cfg.py.in} (97%) rename compiler-rt/test/xray/Unit/{lit.site.cfg.in => lit.site.cfg.py.in} (100%) rename compiler-rt/test/xray/{lit.cfg => lit.cfg.py} (100%) rename compiler-rt/test/xray/{lit.site.cfg.in => lit.site.cfg.py.in} (99%) rename compiler-rt/unittests/{lit.common.unit.cfg => lit.common.unit.cfg.py} (100%) copy libcxx/test/std/strings/{basic.string.hash/char_type_hash.fail.cpp => string. [...] create mode 100644 libcxxabi/lib/itanium-base.exp create mode 100644 libcxxabi/lib/new-delete.exp create mode 100644 libcxxabi/lib/personality-sjlj.exp create mode 100644 libcxxabi/lib/personality-v0.exp create mode 100644 lld/test/COFF/Inputs/id.res.o create mode 100644 lld/test/COFF/resource-objs.test delete mode 100644 lld/test/ELF/invalid/Inputs/invalid-e_shnum.elf delete mode 100644 lld/test/ELF/invalid/invalid-e_shnum.s create mode 100644 lld/test/ELF/invalid/invalid-e_shnum.test create mode 100644 lld/test/ELF/linkerscript/empty-relaplt-dyntags.test create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_ [...] delete mode 100644 llvm/include/llvm/Support/ScalableSize.h create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpe [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.con [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.per [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groups [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get. 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6 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-Oz updated (2f2e762 -> c2736f6)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-Oz in repository toolchain/ci/base-artifacts. discards 2f2e762 0: update: glibc-3db85a9814784a74536a1f0e7b7ddbfef7dc84bb: 0 new c2736f6 0: update: llvm-fb133b0aabec9b669bf7db60586b900c3422f38f: 0 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2f2e762) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk/llvm-master-aarch64- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 22 +- 02-prepare_abe/console.log | 236 +- 03-build_abe-binutils/console.log | 10735 ++- 04-build_abe-stage1/console.log | 14803 ++--- 05-build_abe-linux/console.log | 280 +- 06-build_abe-glibc/console.log | 35995 +++++----- 07-build_abe-stage2/console.log | 39912 ++++++------ 08-build_llvm-true/console.log | 11814 ++-- 09-benchmark/benchmark-start.log | 2 +- 09-benchmark/benchmark.log | 5 +- 09-benchmark/console.log | 99 +- 10-check_regression/console.log | 3209 +- 11-update_baseline/console.log | 861 +- console.log | 122742 +++++++++++++++++------------------ jenkins/manifest.sh | 8 +- results.csv | 176 +- results_id | 2 +- 17 files changed, 120188 insertions(+), 120713 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap updated (2052a2bc9ff -> 0240c270776)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap in repository toolchain/ci/gcc. from 2052a2bc9ff Daily bump. adds 83cfdc89abe Daily bump. adds a1425c004e8 Daily bump. adds 0240c270776 2019-07-07 Paul Thomas <pault(a)gcc.gnu.org> No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 7 ++ gcc/fortran/trans-array.c | 6 +- gcc/testsuite/ChangeLog | 6 ++ gcc/testsuite/gfortran.dg/pointer_array_11.f90 | 90 ++++++++++++++++++++++++++ 5 files changed, 106 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/pointer_array_11.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap updated (903e7f6 -> a9a356f)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap in repository toolchain/ci/base-artifacts. discards 903e7f6 0: update: gcc-2052a2bc9ffb71d78e38d4095bdaec8fdb87249d: -5 new a9a356f 0: update: gcc-0240c270776948b7b8a50380af246b4aae4857c5: -5 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (903e7f6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-aarch64- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-prepare_abe/console.log | 396 +- 03-build_abe-bootstrap/console.log | 65073 +++++++++++++++++----------------- console.log | 65631 +++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 5 files changed, 65632 insertions(+), 65638 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (87856e739c8 -> 8cedf04a6c8)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project. from 87856e739c8 [Rewrite] Try to fix buildbot link fail left by r365263 adds 8c036bf784e [X86] Copy some test cases from vector-shuffle-sse1.ll to v [...] adds 913105ca42b [X86] Add patterns to select MOVLPDrm from MOVSD+load and M [...] adds 317d6093df7 [X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions. adds e753247b061 [X86] Add PS<->PD domain changing support for MOVH/MOVL loa [...] adds 9c68aa33e3b [DAGCombine] convertBuildVecZextToZext - remove duplicate g [...] adds 01f1bad6182 [X86] LowerBuildVectorv16i8 - pull out repeated getOperand( [...] adds a7145c45a7e [X86] SimplifyDemandedVectorEltsForTargetNode - fix shadow [...] adds 9e52c43090f Treat the range of representable values of floating-point t [...] adds 8baf83839e9 Fix PR27658 - Make ~mutex trivial when possible. adds 617df204b5b [CodeGen] Add larger vector types for i32 and f32 adds ac744d5a864 [X86] Make sure load isn't volatile before shrinking it in [...] adds 3e9ef48440a gn build: Merge r365258 and follow-ups r365263, r365264 adds d22fd0e4ecc gn build: Sort cxx_sources in libcxx build file adds 7e063620611 gn build: Sort sync script output adds 18d138e6acc gn build: Merge r365273 adds 87210015581 gn build: Merge r355546 new 8cedf04a6c8 Make ~mutex and ~condition_variable trivial on Windows. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/docs/UndefinedBehaviorSanitizer.rst | 18 +- clang/include/clang/Basic/Sanitizers.def | 2 +- clang/lib/AST/ExprConstant.cpp | 22 +- clang/lib/CodeGen/CGExprScalar.cpp | 178 ++++------- clang/test/CXX/expr/expr.const/p2-0x.cpp | 28 +- clang/test/CodeGen/catch-undef-behavior.c | 42 +-- clang/test/Driver/fsanitize.c | 18 +- clang/test/SemaCXX/constant-expression-cxx1y.cpp | 5 +- libcxx/include/__config | 17 ++ libcxx/include/__mutex_base | 42 +-- libcxx/src/CMakeLists.txt | 2 + libcxx/src/condition_variable.cpp | 5 +- libcxx/src/condition_variable_destructor.cpp | 46 +++ libcxx/src/mutex.cpp | 5 +- libcxx/src/mutex_destructor.cpp | 51 ++++ .../thread.mutex.class/default.pass.cpp | 6 +- llvm/include/llvm/CodeGen/ValueTypes.td | 186 ++++++------ llvm/include/llvm/Support/MachineValueType.h | 274 ++++++++++------- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- llvm/lib/CodeGen/ValueTypes.cpp | 26 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 12 +- llvm/lib/Target/X86/X86InstrAVX512.td | 18 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 30 +- llvm/lib/Target/X86/X86InstrSSE.td | 38 ++- llvm/test/CodeGen/X86/avx2-masked-gather.ll | 18 +- llvm/test/CodeGen/X86/avx512-insert-extract.ll | 4 +- llvm/test/CodeGen/X86/avx512-masked-memop-64-32.ll | 2 +- llvm/test/CodeGen/X86/dag-merge-fast-accesses.ll | 4 +- llvm/test/CodeGen/X86/extract-store.ll | 8 +- llvm/test/CodeGen/X86/extractelement-load.ll | 4 +- llvm/test/CodeGen/X86/fma.ll | 62 ++-- llvm/test/CodeGen/X86/gather-addresses.ll | 20 +- llvm/test/CodeGen/X86/half.ll | 12 +- .../CodeGen/X86/insert-into-constant-vector.ll | 30 +- llvm/test/CodeGen/X86/insertelement-ones.ll | 12 +- llvm/test/CodeGen/X86/masked_compressstore.ll | 144 ++++----- llvm/test/CodeGen/X86/masked_expandload.ll | 324 ++++++++++----------- .../CodeGen/X86/masked_gather_scatter_widen.ll | 8 +- llvm/test/CodeGen/X86/masked_load.ll | 282 +++++++++--------- llvm/test/CodeGen/X86/masked_store.ll | 44 +-- .../CodeGen/X86/merge-consecutive-loads-128.ll | 2 +- .../CodeGen/X86/merge-consecutive-loads-256.ll | 38 +-- .../CodeGen/X86/merge-consecutive-loads-512.ll | 4 +- llvm/test/CodeGen/X86/nontemporal-2.ll | 8 +- llvm/test/CodeGen/X86/oddshuffles.ll | 18 +- llvm/test/CodeGen/X86/pr11334.ll | 10 +- llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 36 +-- llvm/test/CodeGen/X86/sse-only.ll | 6 +- llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 48 +-- llvm/test/CodeGen/X86/sse2.ll | 24 +- llvm/test/CodeGen/X86/sse3.ll | 12 +- llvm/test/CodeGen/X86/var-permute-128.ll | 4 +- llvm/test/CodeGen/X86/vec_insert-2.ll | 2 +- llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll | 60 +++- llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll | 64 +++- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 6 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 4 +- .../CodeGen/X86/vector-shuffle-variable-128.ll | 4 +- .../CodeGen/X86/vector-shuffle-variable-256.ll | 8 +- llvm/test/TableGen/intrinsic-varargs.td | 2 +- llvm/utils/TableGen/CodeGenTarget.cpp | 12 + .../utils/gn/build/sync_source_lists_from_cmake.py | 4 +- .../gn/secondary/clang/unittests/Rewrite/BUILD.gn | 4 + llvm/utils/gn/secondary/libcxx/src/BUILD.gn | 69 ++--- 64 files changed, 1378 insertions(+), 1122 deletions(-) create mode 100644 libcxx/src/condition_variable_destructor.cpp create mode 100644 libcxx/src/mutex_destructor.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (a9f4a38 -> 42f5f29)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards a9f4a38 0: update: llvm-linux: boot new 42f5f29 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a9f4a38) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-build_llvm/console.log | 11816 +++++++++++++++---------------- 03-build_linux/console.log | 1654 ++--- 04-boot_linux/console.log | 460 +- 05-check_regression/console.log | 6 +- console.log | 14118 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 14122 insertions(+), 14122 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 1 month

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