Tcwg-commits June 2019

tcwg-commits@lists.linaro.org

6 participants
15913 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk/gnu-release-aarch64-spec2k6-Os_LTO updated (b0b55e95 -> 3573be47)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/gnu-release-aarch64-spec2k6-Os_LTO in repository toolchain/ci/base-artifacts. discards b0b55e95 0: init: binutils-gcc-glibc: 0 new 3573be47 0: init: binutils-gcc-glibc: 0 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b0b55e95) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk/gnu-release-aarch64- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 152 +- 02-prepare_abe/console.log | 432 +- 03-build_abe-binutils/console.log | 11132 ++-- 04-build_abe-stage1/console.log | 13723 +++-- 05-build_abe-linux/console.log | 304 +- 06-build_abe-glibc/console.log | 39169 ++++++------- 07-build_abe-stage2/console.log | 40292 +++++++------- 08-benchmark/benchmark-start.log | 2 +- 08-benchmark/benchmark.log | 24 +- 08-benchmark/console.log | 140 +- 10-update_baseline/console.log | 6 +- console.log | 105378 ++++++++++++++++++----------------- jenkins/manifest.sh | 14 +- results_id | 2 +- 14 files changed, 105387 insertions(+), 105383 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (29f785ff76b6 -> bed3c0d84e7e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/linux. from 29f785ff76b6 Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux [...] adds 8c30d32b1a32 lib/test_stackinit: Handle Clang auto-initialization pattern adds 915ed9320cba Merge tag 'meminit-v5.2-rc6' of git://git.kernel.org/pub/s [...] adds 490cad5a3ad6 soc: brcmstb: Fix error path for unsupported CPUs adds 6b23af0783a5 soc: bcm: brcmstb: biuctrl: Register writes require a barrier adds c1d6f4adf465 Merge tag 'arm-soc/for-5.2/drivers-fixes' of https://githu [...] adds b2279bcffa72 MAINTAINERS: Update Stefan Wahren email address adds 9925a6d9b794 Merge tag 'arm-soc/for-5.2/maintainers' of https://github. [...] adds fafaa0a27675 arm64: imx: Fix build error without CONFIG_SOC_BUS adds a0b14e6585b9 firmware: imx: SCU irq should ONLY be enabled after SCU IP [...] adds b25af2ff7c07 ARM: imx: cpuidle-imx6sx: Restrict the SW2ISO increase to i.MX6SX adds 4bded299838f Merge tag 'imx-fixes-5.2' of git://git.kernel.org/pub/scm/ [...] adds 88a748419b84 ARM: dts: am57xx-idk: Remove support for voltage switching [...] adds c3c0b70cd3f8 ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values adds 1ba12322e2f0 Merge branch 'am5-sdio-fixes' into fixes adds f7b9cb944a5d ARM: dts: dra76x: Disable rtc target module adds b07bd27e02b9 ARM: dts: dra76x: Disable usb4_tm target module adds fe9edfe648ac ARM: dts: dra71x: Disable rtc target module adds 34b1b8061de3 ARM: dts: dra71x: Disable usb4_tm target module adds f29f24b5568f Merge branch 'fixes-dra7' into fixes adds 516f1117d0fb ARM: dts: Configure osc clock for d_can on am335x adds e4f50c8d1047 bus: ti-sysc: Handle devices with no control registers adds 4ee23cd76c0c Merge branch 'omap-for-v5.2/ti-sysc' into fixes adds 6515a2ceac76 Merge tag 'omap-for-v5.2/fixes-rc2' of git://git.kernel.or [...] adds e8bd76dccd79 ARM: dts: bcm: Add missing device_type = "memory" property adds 9f22081ea221 Merge tag 'arm-soc/for-5.2/devicetree-fixes' of https://gi [...] adds a6b112b04355 arm64: arch_k3: Fix kconfig dependency warning adds 5a55a1612373 Merge tag 'am654-fixes-for-v5.2' of git://git.kernel.org/p [...] adds cc538ca43083 ARM: mvebu_v7_defconfig: fix Ethernet on Clearfog adds 75d91ba4750e Merge tag 'mvebu-fixes-5.2-1' of git://git.infradead.org/l [...] adds 0c0c9b5753cd ARM: davinci: da850-evm: call regulator_has_full_constraints() adds 68f2515bb31a ARM: davinci: da8xx: specify dma_coherent_mask for lcdc adds d5d3652af157 Merge tag 'davinci-fixes-for-v5.2' of git://git.kernel.org [...] adds 34f61de87017 ARM: dts: Drop bogus CLKSEL for timer12 on dra7 adds cbdce1418894 ARM: dts: dra72x: Disable usb4_tm target module adds 8a0098c05a27 ARM: dts: am335x phytec boards: Fix cd-gpios active level adds 80d1d4652545 Merge tag 'omap-for-v5.2/fixes-rc4' of git://git.kernel.or [...] adds 4b576d15df5c MAINTAINERS: Change QCOM repo location adds cad47b322da0 firmware: trusted_foundations: add ARMv7 dependency adds 6d8df6021841 ARM: ixp4xx: don't select SERIAL_OF_PLATFORM adds 4ea10150ea00 ARM: ixp4xx: mark ixp4xx_irq_setup as __init adds 140d90098fed ARM: ixp4xx: include irqs.h where needed adds cd3967bee004 soc: ixp4xx: npe: Fix an IS_ERR() vs NULL check in probe adds 7b306892cc57 Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/l [...] adds 8eaf40c0e24e Btrfs: fix race between block group removal and block grou [...] adds c4e0540d0ad4 btrfs: start readahead also in seed devices adds 3763771cf602 Btrfs: fix failure to persist compression property xattr d [...] adds bed3c0d84e7e Merge tag 'for-5.2-rc5-tag' of git://git.kernel.org/pub/sc [...] No new revisions were added by this update. Summary of changes: MAINTAINERS | 4 +-- arch/arm/boot/dts/am335x-pcm-953.dtsi | 2 +- arch/arm/boot/dts/am335x-wega.dtsi | 2 +- arch/arm/boot/dts/am33xx-l4.dtsi | 14 ++++---- arch/arm/boot/dts/am437x-l4.dtsi | 4 --- arch/arm/boot/dts/am57xx-idk-common.dtsi | 1 + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 1 + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 1 + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 1 + arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts | 1 + arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts | 1 + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 1 + arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 1 + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 1 + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 1 + arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 1 + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 1 + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 1 + arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 1 + arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 1 + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 1 + arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 1 + arch/arm/boot/dts/bcm47094-phicomm-k3.dts | 1 + arch/arm/boot/dts/bcm94708.dts | 1 + arch/arm/boot/dts/bcm94709.dts | 1 + arch/arm/boot/dts/bcm963138dvt.dts | 1 + arch/arm/boot/dts/dra7-l4.dtsi | 4 +-- arch/arm/boot/dts/dra71-evm.dts | 2 +- .../i2c/mt9v022.h => arch/arm/boot/dts/dra71x.dtsi | 13 +++---- arch/arm/boot/dts/dra72x.dtsi | 4 +++ arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 40 +++++++++++----------- arch/arm/boot/dts/dra76x.dtsi | 8 +++++ arch/arm/configs/mvebu_v7_defconfig | 1 + arch/arm/mach-davinci/board-da850-evm.c | 2 ++ arch/arm/mach-davinci/devices-da8xx.c | 3 ++ arch/arm/mach-imx/cpuidle-imx6sx.c | 3 +- arch/arm/mach-ixp4xx/Kconfig | 1 - arch/arm/mach-ixp4xx/goramo_mlr.c | 2 ++ arch/arm/mach-ixp4xx/miccpt-pci.c | 2 ++ arch/arm/mach-ixp4xx/omixp-setup.c | 2 ++ arch/arm/mach-ixp4xx/vulcan-pci.c | 2 ++ arch/arm/mach-ixp4xx/vulcan-setup.c | 2 ++ arch/arm64/Kconfig.platforms | 2 ++ drivers/bus/ti-sysc.c | 23 ++++++------- drivers/firmware/Kconfig | 2 +- drivers/firmware/imx/imx-scu-irq.c | 3 ++ drivers/irqchip/irq-ixp4xx.c | 8 ++--- drivers/soc/bcm/brcmstb/biuctrl.c | 6 ++-- drivers/soc/ixp4xx/ixp4xx-npe.c | 4 +-- fs/btrfs/extent-tree.c | 24 +++++++------ fs/btrfs/ioctl.c | 2 -- fs/btrfs/reada.c | 5 +++ fs/btrfs/xattr.c | 6 ++-- lib/test_stackinit.c | 21 ++++++++---- 54 files changed, 153 insertions(+), 91 deletions(-) copy include/media/i2c/mt9v022.h => arch/arm/boot/dts/dra71x.dtsi (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (afb17daedf9 -> 4ef7c2868a5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/llvm-project. from afb17daedf9 Fix windows build for r363357 adds a1a4f5f12cc [DebugInfo][Docs] Document that prologue/epilogue variable [...] adds 7dd529e54da [X86] Replace any_extend* vector extensions with zero_exten [...] adds 0265716b272 [NFC] Improve triple match of scripts that update tests adds 6658bfb171a [X86] Regenerate promote.ll. NFC. adds 43854e3ccc7 [SVE][IR] Scalable Vector IR Type with pr42210 fix adds 7e854e1cdd2 [AMDGPU] Speed up live-in virtual register set computaion i [...] adds 40fdd7a643b [clangd] Detect C++ language based on well-known file path [...] adds 8ddf31bc33e [clangd] Parse files without extensions if we don't have a [...] adds 8d41294c189 [clangd] Add a capability to enable completions with fixes. adds 5c64a8c4c69 [SystemZ] Fix AHIMuxK pseudo expansion. adds 7a7009f7c82 [ARM] Some Thumb2ITBlock clean ups. NFC adds d5ce8ec778c AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.scale adds 23f03f5059c AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca adds e75e197ad87 AMDGPU: Remove unnecessary check for virtual register adds bcb5ea00428 AMDGPU: Fold readlane from copy of SGPR or imm adds 83bacd8d72b [SelectionDAG] Legalize vaargs that require vector splitting adds 7001fe8d143 gn build: Merge r363649 adds 3c8e2cdda5a gn build: Merge r363658 adds c99d9aee007 MCContext: Delete unused functions adds f39f3bd056f AMDGPU: Change API for checking for exec modification adds 7a89909c842 Require commas to separate multiple GNU-style attributes in [...] adds 3b2f5df12c8 [MCA] Slightly refactor the bottleneck analysis view. NFCI adds 8d35dcd7039 AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics adds 45b10d2da5c [compiler-rt][SystemZ] Work around ASAN failures via -fno-p [...] adds 395fde753c9 [clangd] Add hidden tweaks to dump AST/selection. adds 9483bcf7815 [clangd] Remove the extra ";", NFC adds d204987ada4 AMDGPU: Disable errno by default adds 677423997d6 [llvm-readobj] Allow --hex-dump/--string-dump to dump multi [...] adds 2acc7176271 AMDGPU: Add GWS instruction builtins adds 2fef12ccb19 Fix -Wunused-but-set-variable warning. NFCI. adds 74c83649547 [RISCV] Lower calls through PLT adds a45292cbfd2 [CodeGen][ARM] Fix FP16 vector coercion adds 1fab01f92bd [libc++] Revert the addition of map/multimap CTAD adds 91185b69d12 [libc++] Re-apply XFAIL to is_base_of test that was inadver [...] adds ed4a6025152 [ARM] Rename MVE instructions in Tablegen for consistency. adds df9ee08b649 [clangd] Return vector<TextEdit> from applyTweak. NFC adds c74fc6d5f96 [libc++] Implement P0608R3 - A sane variant converting constructor adds 9c8593934af [X86][AVX] extract_subvector(any_extend(x)) -> any_extend_v [...] adds 9aa25be1491 [TargetLowering] SimplifyDemandedVectorElts - support MUL a [...] adds faaf1a53663 [ARM] Add MVE integer vector min/max instructions. adds cfc70782d7e [ARM] Add MVE vector shift instructions. adds c470ac50a8a [Reproducers] Make reproducer relocatable adds 5aed309a4f6 [Syntax] Add a helper to find expansion by its first spelled token adds 3559d2224ee Add test cases for dumping AST decl nodes to JSON; NFC. adds 46e6e132987 Fix some lit test ResourceWarnings on Windows adds 9086ba8763a [mips] Set the hasNoSchedulingInfo flag for the `MipsAsmPse [...] adds 60a9d0c248b [mips] Add PTR_64 and GPR_64 predicates to some MIPS 64-bit [...] adds 796e7f87241 [mips] Add more strict predicates to the RSQRT_S_MM and TAI [...] adds 223176f5d74 [x86] add test for load splitting with extracted store (PR4 [...] adds 5cf216c9a72 [scudo][standalone] Fuchsia related changes adds fda83c9b0b1 Implement xfer:libraries-svr4:read packet adds d4a1c3bb5a1 Add test cases for dumping AST function decl nodes to JSON; NFC. adds b6e7108dcd6 [TargetLowering] SimplifyDemandedBits - Merge SIGN_EXTEND+S [...] adds 76a149ef818 [SROA] Enhance SROA to handle `addrspacecast`ed allocas adds d9b3d08a9a6 [clang-tidy] Split fuchsia-default-arguments adds 032b54f8e87 [TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+Z [...] adds 8dc6840f1c9 Fix the floating point version of midpoint. It wasn't const [...] adds 5bef886cd8e [TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND [...] adds 8557d1ac988 [OPENMP]Use host's long double when compiling the code for device. adds 33e85ad9567 Revert [SROA] Enhance SROA to handle `addrspacecast`ed allocas adds 10e6128c62e [X86] Remove unnecessary line that makes v4f32 FP_ROUND Legal. NFC adds 7ae267dc0f3 [OPENMP][NVPTX]Correct codegen for 128 bit long double. adds ab4f2ea7931 [AMDGPU] gfx1010 disassembler changes for wave32 adds a8aa58fb3d3 Reconfigure docker builders to be more modular. adds 9d54063c823 [pstl] Remove stray usage of pstl::execution instead of std [...] adds a702f07301f [PDB] Ignore .debug$S subsections with high bit set adds 8ff822d61da Add debug location verification for !llvm.loop attachments. adds 050b804b139 [pstl] Disable workarounds for broken ICC versions when usi [...] adds 3fcad775c0f [coroutines] Add missing pass dependency. adds acc93d62e04 Revert Add debug location verification for !llvm.loop attachments. adds bb1c8b6f5ca [AMDGPU] gfx10 wave32 patterns adds 1db8d4a8660 Fix broken debug info in in an !llvm.loop attachment in thi [...] adds fc5107cde64 Add debug location verification for !llvm.loop attachments. adds 413ed69b4b7 [x86] add another test for load splitting with extracted st [...] adds ba43840bfe2 [MachinePipeliner][NFC] Do resource tracking log only when [...] adds 9f3a805ee96 [OPENMP]Use host's mangling for 128 bit float types on the device. adds a0eb49c26e5 [libFuzzer] Improve FuzzedDataProvider helper. adds 9f155bc6e59 [RISCV] Prevent re-ordering some adds after shifts adds 64fbefde6eb [libcxxabi] Remove the unused buildit script adds 5c739665a87 Remove GCC C++03 fallbacks for decltype and static_assert. adds d16779a732d [ARM] Comply with rules on ARMv8-A thumb mode partial depre [...] adds 2184374d948 Disable the 'nextafter' portions of these tests on PPC when [...] adds e8d8bb51707 InstCombine: Pre-commit test for reassociating nuw adds 7bfb43985f2 [test] NFC, udpate clang-scan-deps tests to not use -c to a [...] adds 4f7f70e2624 Recommit [SROA] Enhance SROA to handle `addrspacecast`ed allocas adds 9b2252123d1 [tblgen][disasm] Allow multiple encodings to disassemble to [...] adds d11ea2c8c54 [GlobalISel][Localizer] Remove redundant set lookup. adds c2885ded2b1 Print dylib load kind (weak, reexport, etc) in llvm-objdump [...] adds 4053d95cd85 Revert [tblgen][disasm] Allow multiple encodings to disasse [...] adds f9c6e565de2 Show note for -Wmissing-prototypes for functions with parameters adds df195d8aedf Suggestions to fix -Wmissing-{prototypes,variable-declarations} adds a7335393f50 Add ReadCStringFromMemory for faster string reads adds 1933cbe8662 [test] Change comment wording (NFC) adds cf8c6cfcdc8 [demangle] Special case clang's creative mangling of __uuid [...] adds 4c2522220fe Re-commit r363744: [tblgen][disasm] Allow multiple encoding [...] adds 2b285c664d7 Fix tests after r363749 adds c6b5be6cf07 Don't crash if PR_SET_VMA_ANON_NAME fails. adds 1885747498c [WebAssembly] Optimize ISel for SIMD Boolean reductions adds 9cac4e6d140 Rename ExpandISelPseudo->FinalizeISel, delay register reservation adds c5b918de58c [NFC] move some hardware loop checking code to a common pla [...] adds 8c24a576956 git-clang-format: Remove trailing whitespace in docstring. NFC. adds 44940048dde Fix more tests after r363749 adds c4d5c372853 [TEST] Fix test on Windows by looking for substrings rather [...] adds ec4e0809df1 [RISCV] Fix test after r363757 adds 58dbe47b9c6 Test commit access new 3f0ae625ebf [libc++] Revert r363692 which implements P0608R3 new 38047dbca4e [clangd] Add ClangdServer accessor for buffer contents new 08372eb73bf Revert "[clangd] Return vector<TextEdit> from applyTweak. NFC" new 67b45acefef DWARF: Make DIERefs always valid new e9435190d6b Revert r359557 "vs integration: vs2019 support" new 9ed156701b7 vs integration: bump version nbr new 73a28f06432 Fix a dangling StringRef in FileCollector new 39263ac5d13 [RISCV] Add lowering of global TLS addresses new 80b6b705f87 Stabilize TestGdbRemoteLibrariesSvr4Support new 4ef7c2868a5 [X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsr The 10 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/fuchsia/CMakeLists.txt | 3 +- .../fuchsia/DefaultArgumentsCallsCheck.cpp | 35 + ...gumentsCheck.h => DefaultArgumentsCallsCheck.h} | 16 +- .../clang-tidy/fuchsia/DefaultArgumentsCheck.cpp | 61 - .../fuchsia/DefaultArgumentsDeclarationsCheck.cpp | 54 + ...Check.h => DefaultArgumentsDeclarationsCheck.h} | 16 +- .../clang-tidy/fuchsia/FuchsiaTidyModule.cpp | 11 +- clang-tools-extra/clangd/ClangdLSPServer.cpp | 36 +- clang-tools-extra/clangd/ClangdServer.cpp | 42 +- clang-tools-extra/clangd/ClangdServer.h | 11 +- .../clangd/GlobalCompilationDatabase.cpp | 6 +- clang-tools-extra/clangd/Protocol.cpp | 11 + clang-tools-extra/clangd/Protocol.h | 28 + clang-tools-extra/clangd/Selection.cpp | 3 + clang-tools-extra/clangd/TUScheduler.cpp | 9 + clang-tools-extra/clangd/TUScheduler.h | 4 + .../clangd/clients/clangd-vscode/package.json | 4 + clang-tools-extra/clangd/refactor/Tweak.h | 44 +- .../clangd/refactor/tweaks/CMakeLists.txt | 1 + .../clangd/refactor/tweaks/DumpAST.cpp | 139 ++ .../clangd/refactor/tweaks/RawStringLiteral.cpp | 14 +- .../clangd/refactor/tweaks/SwapIfBranches.cpp | 11 +- clang-tools-extra/clangd/tool/ClangdMain.cpp | 6 + .../unittests/GlobalCompilationDatabaseTests.cpp | 4 + .../clangd/unittests/SelectionTests.cpp | 10 + .../clangd/unittests/TUSchedulerTests.cpp | 8 +- clang-tools-extra/clangd/unittests/TweakTests.cpp | 74 +- clang-tools-extra/docs/ReleaseNotes.rst | 22 + ...nts.rst => fuchsia-default-arguments-calls.rst} | 12 +- .../fuchsia-default-arguments-declarations.rst | 16 + clang-tools-extra/docs/clang-tidy/checks/list.rst | 3 +- .../test/clang-tidy/export-diagnostics.cpp | 14 + .../clang-tidy/fuchsia-default-arguments-calls.cpp | 36 + ... => fuchsia-default-arguments-declarations.cpp} | 39 +- clang/include/clang/Basic/BuiltinsAMDGPU.def | 2 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 6 +- clang/include/clang/Tooling/Syntax/Tokens.h | 19 + clang/lib/AST/ASTContext.cpp | 11 +- clang/lib/AST/ItaniumMangle.cpp | 28 +- clang/lib/CodeGen/TargetInfo.cpp | 40 +- clang/lib/Driver/ToolChains/AMDGPU.h | 2 + clang/lib/Parse/ParseDecl.cpp | 10 +- clang/lib/Sema/SemaDecl.cpp | 43 +- clang/lib/Sema/SemaOpenMP.cpp | 4 +- clang/lib/Tooling/Syntax/Tokens.cpp | 26 + clang/test/AST/ast-dump-decl-json.c | 1671 ++++++++++++++++++++ clang/test/AST/ast-dump-funcs-json.cpp | 1126 +++++++++++++ clang/test/ClangScanDeps/Inputs/regular_cdb.json | 4 +- clang/test/CodeGen/arm-vfp16-arguments2.cpp | 63 + clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 12 + clang/test/Driver/fast-math.c | 6 + .../test/OpenMP/nvptx_unsupported_type_codegen.cpp | 21 +- .../OpenMP/nvptx_unsupported_type_messages.cpp | 15 +- clang/test/Parser/attributes.c | 12 +- clang/test/Preprocessor/Weverything_pragma.c | 1 + clang/test/Preprocessor/pragma_diagnostic.c | 3 + clang/test/Preprocessor/pushable-diagnostics.c | 4 + clang/test/Sema/warn-missing-prototypes.c | 16 +- .../test/Sema/warn-missing-variable-declarations.c | 5 +- clang/test/SemaCXX/warn-everthing.cpp | 1 + clang/test/SemaCXX/warn-missing-prototypes.cpp | 8 + .../SemaCXX/warn-missing-variable-declarations.cpp | 10 +- clang/test/SemaOpenCL/warn-missing-prototypes.cl | 1 + clang/tools/clang-format/git-clang-format | 26 +- clang/unittests/Tooling/Syntax/TokensTest.cpp | 78 + compiler-rt/CMakeLists.txt | 9 + compiler-rt/cmake/config-ix.cmake | 1 + .../fuzzer/tests/FuzzedDataProviderUnittest.cpp | 51 +- compiler-rt/lib/fuzzer/utils/FuzzedDataProvider.h | 154 +- .../lib/sanitizer_common/sanitizer_posix.cc | 3 +- compiler-rt/lib/scudo/standalone/fuchsia.cc | 32 +- compiler-rt/lib/scudo/standalone/linux.cc | 20 +- compiler-rt/lib/scudo/standalone/mutex.h | 23 +- libcxx/include/__config | 28 +- libcxx/include/iterator | 16 - libcxx/include/map | 57 +- libcxx/include/numeric | 29 +- .../associative/map/map.cons/deduct.fail.cpp | 107 -- .../associative/map/map.cons/deduct.pass.cpp | 137 -- .../associative/map/map.cons/deduct_const.pass.cpp | 107 -- .../multimap/multimap.cons/deduct.fail.cpp | 107 -- .../multimap/multimap.cons/deduct.pass.cpp | 137 -- .../multimap/multimap.cons/deduct_const.pass.cpp | 107 -- .../numeric.ops.midpoint/midpoint.float.pass.cpp | 67 +- .../meta/meta.rel/is_base_of_union.pass.cpp | 6 +- libcxx/utils/docker/debian9/Dockerfile | 205 --- libcxx/utils/docker/debian9/Dockerfile.base | 46 + libcxx/utils/docker/debian9/Dockerfile.buildbot | 26 + libcxx/utils/docker/debian9/Dockerfile.clang | 19 + .../utils/docker/debian9/Dockerfile.compiler_zoo | 35 + libcxx/utils/docker/debian9/Dockerfile.gcc | 18 + libcxx/utils/docker/docker-compose.yml | 46 +- libcxx/utils/docker/scripts/checkout_git.sh | 129 -- .../utils/docker/scripts/docker_start_buildbots.sh | 6 +- libcxx/utils/docker/scripts/docker_update_bot.sh | 32 + libcxx/utils/docker/scripts/run_buildbot.sh | 141 +- libcxx/utils/docker/scripts/run_buildbot_new.sh | 110 -- libcxxabi/lib/buildit | 99 -- libcxxabi/src/demangle/ItaniumDemangle.h | 31 + libcxxabi/test/test_demangle.pass.cpp | 3 + lld/COFF/PDB.cpp | 5 + lld/test/COFF/pdb-unknown-subsection.s | 14 + .../lldb/Host/common/NativeProcessProtocol.h | 39 + lldb/include/lldb/Utility/FileCollector.h | 5 +- lldb/include/lldb/Utility/Reproducer.h | 7 +- lldb/lit/Reproducer/TestReuseDirectory.test | 7 + .../test/tools/lldb-server/gdbremote_testcase.py | 29 +- .../test/tools/lldb-server/libraries-svr4/Makefile | 17 + .../TestGdbRemoteLibrariesSvr4Support.py | 130 ++ .../test/tools/lldb-server/libraries-svr4/main.cpp | 15 + .../tools/lldb-server/libraries-svr4/svr4lib_a.cpp | 9 + .../tools/lldb-server/libraries-svr4/svr4lib_a.mk | 9 + .../lldb-server/libraries-svr4/svr4lib_b_quote.cpp | 9 + .../lldb-server/libraries-svr4/svr4lib_b_quote.mk | 9 + lldb/source/API/SBDebugger.cpp | 6 + lldb/source/Host/common/FileSystem.cpp | 5 +- lldb/source/Host/common/NativeProcessProtocol.cpp | 54 + .../Plugins/Process/NetBSD/NativeProcessNetBSD.h | 4 +- .../Plugins/Process/POSIX/NativeProcessELF.cpp | 68 + .../Plugins/Process/POSIX/NativeProcessELF.h | 7 + .../GDBRemoteCommunicationServerCommon.cpp | 1 + .../GDBRemoteCommunicationServerLLGS.cpp | 43 + .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 2 + lldb/source/Plugins/SymbolFile/DWARF/DIERef.cpp | 19 - lldb/source/Plugins/SymbolFile/DWARF/DIERef.h | 19 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 51 +- .../Plugins/SymbolFile/DWARF/DWARFBaseDIE.cpp | 4 +- .../source/Plugins/SymbolFile/DWARF/DWARFBaseDIE.h | 2 +- lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.cpp | 10 +- lldb/source/Plugins/SymbolFile/DWARF/DWARFDIE.h | 2 +- .../SymbolFile/DWARF/DWARFDebugInfoEntry.cpp | 18 +- .../SymbolFile/DWARF/DebugNamesDWARFIndex.cpp | 31 +- .../SymbolFile/DWARF/DebugNamesDWARFIndex.h | 2 +- .../Plugins/SymbolFile/DWARF/HashedNameToDIE.cpp | 20 +- .../Plugins/SymbolFile/DWARF/HashedNameToDIE.h | 20 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp | 19 +- .../Plugins/SymbolFile/DWARF/SymbolFileDWARF.h | 8 +- lldb/source/Utility/FileCollector.cpp | 7 +- lldb/unittests/Host/NativeProcessProtocolTest.cpp | 51 + lldb/unittests/Utility/FileCollectorTest.cpp | 6 +- llvm/docs/LangRef.rst | 54 +- llvm/docs/SourceLevelDebugging.rst | 17 +- llvm/include/llvm/ADT/DenseMapInfo.h | 16 + llvm/include/llvm/Analysis/TargetTransformInfo.h | 40 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 2 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 2 +- llvm/include/llvm/CodeGen/Passes.h | 5 +- llvm/include/llvm/DebugInfo/CodeView/CodeView.h | 3 + llvm/include/llvm/Demangle/ItaniumDemangle.h | 31 + llvm/include/llvm/IR/DerivedTypes.h | 68 +- llvm/include/llvm/IR/Instructions.h | 1 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 22 + llvm/include/llvm/IR/IntrinsicsX86.td | 12 +- llvm/include/llvm/IR/Type.h | 1 + llvm/include/llvm/InitializePasses.h | 2 +- llvm/include/llvm/MC/MCContext.h | 15 - llvm/include/llvm/MCA/HardwareUnits/LSUnit.h | 2 +- llvm/include/llvm/Support/ScalableSize.h | 43 + llvm/include/llvm/Target/Target.td | 76 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 85 + llvm/lib/AsmParser/LLLexer.cpp | 1 + llvm/lib/AsmParser/LLParser.cpp | 13 +- llvm/lib/AsmParser/LLToken.h | 1 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 6 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 5 +- llvm/lib/CodeGen/CMakeLists.txt | 2 +- llvm/lib/CodeGen/CodeGen.cpp | 2 +- .../{ExpandISelPseudos.cpp => FinalizeISel.cpp} | 29 +- llvm/lib/CodeGen/GlobalISel/Localizer.cpp | 2 +- llvm/lib/CodeGen/HardwareLoops.cpp | 92 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 65 +- llvm/lib/CodeGen/MachineVerifier.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 + .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 23 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 29 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 101 +- llvm/lib/CodeGen/TargetPassConfig.cpp | 13 +- llvm/lib/IR/AsmWriter.cpp | 5 +- llvm/lib/IR/LLVMContextImpl.h | 2 +- llvm/lib/IR/Type.cpp | 13 +- llvm/lib/IR/Verifier.cpp | 95 +- llvm/lib/MC/MCContext.cpp | 8 - llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 85 + llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 14 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 14 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 3 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 6 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 14 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.h | 2 + llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 2 +- llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 7 +- llvm/lib/Target/AMDGPU/GCNRegPressure.h | 47 + llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 28 +- llvm/lib/Target/AMDGPU/GCNSchedStrategy.h | 3 + llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 60 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 18 + llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 28 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 58 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 13 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 80 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 37 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 10 +- llvm/lib/Target/AMDGPU/SOPInstructions.td | 18 +- llvm/lib/Target/ARM/ARM.h | 1 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 35 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 26 + llvm/lib/Target/ARM/ARMInstrMVE.td | 988 +++++++++--- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 92 +- .../Target/ARM/Disassembler/ARMDisassembler.cpp | 12 +- .../Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 41 + llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 90 +- llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 2 +- llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 3 +- llvm/lib/Target/Mips/Mips64InstrInfo.td | 29 +- llvm/lib/Target/Mips/MipsInstrFormats.td | 1 + llvm/lib/Target/Mips/MipsScheduleP5600.td | 3 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 2 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 28 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 177 ++- llvm/lib/Target/RISCV/RISCVISelLowering.h | 7 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 18 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 6 + llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp | 23 +- llvm/lib/Target/RISCV/Utils/RISCVMatInt.h | 9 + llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 10 +- .../lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 22 + llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 20 + llvm/lib/Target/X86/X86ISelLowering.cpp | 17 +- llvm/lib/Target/X86/X86InstrAVX512.td | 36 - llvm/lib/Target/X86/X86InstrSSE.td | 85 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 7 +- llvm/lib/Transforms/Scalar/SROA.cpp | 8 +- llvm/test/Bitcode/compatibility.ll | 4 + .../gisel-commandline-option-fastisel.ll | 2 +- .../AArch64/GlobalISel/gisel-commandline-option.ll | 2 +- llvm/test/CodeGen/AArch64/O0-pipeline.ll | 2 +- llvm/test/CodeGen/AArch64/O3-pipeline.ll | 2 +- llvm/test/CodeGen/AArch64/apple-latest-cpu.ll | 2 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-rem.ll | 2 +- llvm/test/CodeGen/AArch64/fast-isel-dbg.ll | 2 +- llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll | 2 +- .../GlobalISel/regbankselect-amdgcn.div.scale.mir | 67 + llvm/test/CodeGen/AMDGPU/fold-readlane.mir | 250 +++ llvm/test/CodeGen/AMDGPU/gws-hazards.mir | 103 ++ llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir | 59 + .../CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll | 179 +++ .../test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll | 119 ++ .../CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll | 50 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll | 46 +- .../test/CodeGen/AMDGPU/promote-alloca-lifetime.ll | 28 +- .../si-instr-info-correct-implicit-operands.ll | 2 +- .../CodeGen/AMDGPU/tail-duplication-convergent.ll | 48 + llvm/test/CodeGen/ARM/2014-08-04-muls-it.ll | 3 +- llvm/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll | 2 +- llvm/test/CodeGen/ARM/CGP/arm-cgp-signed-icmps.ll | 2 +- llvm/test/CodeGen/ARM/GlobalISel/pr35375.ll | 4 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 2 +- llvm/test/CodeGen/ARM/Windows/dbzchk.ll | 6 +- llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll | 2 +- llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll | 7 +- llvm/test/CodeGen/ARM/copy-by-struct-i32.ll | 2 +- .../hoist-and-by-const-from-lshr-in-eqcmp-zero.ll | 38 +- .../hoist-and-by-const-from-shl-in-eqcmp-zero.ll | 38 +- llvm/test/CodeGen/ARM/mve-vpt-block.mir | 6 +- llvm/test/CodeGen/Generic/MachineBranchProb.ll | 4 +- llvm/test/CodeGen/Hexagon/call-v4.ll | 2 +- .../print-parse-verify-failedISel-property.mir | 2 +- .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 2 +- llvm/test/CodeGen/MIR/Generic/multiRunPass.mir | 12 +- .../buildpairf64-extractelementf64-implicit-sp.ll | 6 +- .../indirect-jump-hazard/guards-verify-call.mir | 2 +- .../guards-verify-tailcall.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dext-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dext-size.mir | 2 +- .../CodeGen/Mips/instverify/dextm-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextm-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextm-size.mir | 2 +- .../CodeGen/Mips/instverify/dextu-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextu-pos.mir | 2 +- .../CodeGen/Mips/instverify/dextu-size-valid.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextu-size.mir | 2 +- .../test/CodeGen/Mips/instverify/dins-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dins-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dins-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsm-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsm-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsu-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsu-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-size.mir | 2 +- llvm/test/CodeGen/Mips/micromips-eva.mir | 2 +- .../Mips/micromips-target-external-symbol-reloc.ll | 2 +- .../Mips/mirparser/target-flags-pic-mxgot-tls.mir | 4 +- .../Mips/mirparser/target-flags-pic-o32.mir | 4 +- .../CodeGen/Mips/mirparser/target-flags-pic.mir | 4 +- .../Mips/mirparser/target-flags-static-tls.mir | 4 +- .../test/CodeGen/Mips/unaligned-memops-mapping.mir | 2 +- llvm/test/CodeGen/Mips/unaligned-memops.ll | 4 +- llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll | 2 +- llvm/test/CodeGen/PowerPC/legalize-vaarg.ll | 52 + llvm/test/CodeGen/RISCV/add-before-shl.ll | 74 + llvm/test/CodeGen/RISCV/calls.ll | 124 ++ .../CodeGen/RISCV/select-optimize-multiple.mir | 4 +- llvm/test/CodeGen/RISCV/tls-models.ll | 155 ++ llvm/test/CodeGen/SystemZ/cc-liveness.ll | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-02.mir | 2 +- llvm/test/CodeGen/SystemZ/int-add-18.mir | 20 + llvm/test/CodeGen/Thumb2/v8_deprecate_IT.ll | 32 + llvm/test/CodeGen/WebAssembly/simd-reductions.ll | 295 ++++ llvm/test/CodeGen/X86/MachineBranchProb.ll | 2 +- llvm/test/CodeGen/X86/O0-pipeline.ll | 2 +- llvm/test/CodeGen/X86/O3-pipeline.ll | 2 +- llvm/test/CodeGen/X86/catchpad-weight.ll | 2 +- llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll | 2 +- llvm/test/CodeGen/X86/fixed-stack-di-mir.ll | 2 +- llvm/test/CodeGen/X86/i16lshr8pat.ll | 2 +- .../CodeGen/X86/inline-asm-avx512f-x-constraint.ll | 2 +- .../CodeGen/X86/inline-asm-default-clobbers.ll | 2 +- llvm/test/CodeGen/X86/legalize-vaarg.ll | 79 + llvm/test/CodeGen/X86/pr39896.ll | 2 +- llvm/test/CodeGen/X86/promote.ll | 10 +- .../CodeGen/X86/sjlj-shadow-stack-liveness.mir | 2 +- llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll | 2 +- llvm/test/CodeGen/X86/stack-protector-weight.ll | 8 +- llvm/test/CodeGen/X86/switch-edge-weight.ll | 8 +- llvm/test/CodeGen/X86/switch-jump-table.ll | 2 +- .../test/CodeGen/X86/switch-lower-peel-top-case.ll | 2 +- llvm/test/CodeGen/X86/switch.ll | 16 +- llvm/test/CodeGen/X86/vecloadextract.ll | 2 +- llvm/test/CodeGen/X86/vmaskmov-offset.ll | 2 +- llvm/test/CodeGen/X86/widen_load-3.ll | 116 ++ llvm/test/CodeGen/X86/xor-combine-debugloc.ll | 2 +- llvm/test/DebugInfo/ARM/float-stack-arg.ll | 2 +- llvm/test/DebugInfo/Generic/linear-dbg-value.ll | 2 +- llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll | 2 +- llvm/test/DebugInfo/X86/dbg-value-frame-index-2.ll | 2 +- llvm/test/DebugInfo/X86/dbg-value-funcarg.ll | 2 +- llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll | 2 +- llvm/test/DebugInfo/X86/pr40427.ll | 2 +- llvm/test/DebugInfo/X86/safestack-byval.ll | 2 +- llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll | 2 +- llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll | 2 +- llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll | 2 +- llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll | 2 +- llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll | 2 +- llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll | 2 +- llvm/test/DebugInfo/X86/sdag-ir-salvage.ll | 2 +- llvm/test/MC/ARM/mve-minmax.s | 58 + llvm/test/MC/ARM/mve-shifts.s | 576 +++++++ llvm/test/MC/Disassembler/ARM/mve-minmax.txt | 48 + llvm/test/MC/Disassembler/ARM/mve-shifts.txt | 585 +++++++ .../test/Transforms/InstCombine/reassociate-nuw.ll | 131 ++ .../LoopUnroll/runtime-epilog-debuginfo.ll | 4 +- llvm/test/Transforms/SROA/addrspacecast.ll | 15 + llvm/test/Verifier/llvm.loop.ll | 28 + llvm/test/Verifier/scalable-aggregates.ll | 27 + llvm/test/Verifier/scalable-global-vars.ll | 26 + llvm/test/tools/llvm-mca/X86/Atom/resources-sse1.s | 4 +- llvm/test/tools/llvm-mca/X86/BdVer2/pr37790.s | 6 +- .../tools/llvm-mca/X86/BdVer2/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/BdVer2/resources-sse1.s | 4 +- .../tools/llvm-mca/X86/Broadwell/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/Broadwell/resources-sse1.s | 4 +- llvm/test/tools/llvm-mca/X86/BtVer2/pr37790.s | 6 +- .../tools/llvm-mca/X86/BtVer2/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/BtVer2/resources-sse1.s | 4 +- .../tools/llvm-mca/X86/Generic/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/Generic/resources-sse1.s | 4 +- .../tools/llvm-mca/X86/Haswell/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/Haswell/resources-sse1.s | 4 +- llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s | 4 +- .../llvm-mca/X86/SandyBridge/resources-avx1.s | 4 +- .../llvm-mca/X86/SandyBridge/resources-sse1.s | 4 +- .../llvm-mca/X86/SkylakeClient/resources-avx1.s | 4 +- .../llvm-mca/X86/SkylakeClient/resources-sse1.s | 4 +- .../llvm-mca/X86/SkylakeServer/resources-avx1.s | 4 +- .../llvm-mca/X86/SkylakeServer/resources-sse1.s | 4 +- .../tools/llvm-mca/X86/Znver1/resources-avx1.s | 4 +- .../tools/llvm-mca/X86/Znver1/resources-sse1.s | 4 +- .../ELF/overlapping-sections-in-segments.test | 1 + .../llvm-objcopy/ELF/overlapping-sections.test | 1 + llvm/test/tools/llvm-objdump/X86/macho-dylib.test | 11 +- llvm/test/tools/llvm-readobj/hex-dump-multi.s | 21 + llvm/test/tools/llvm-readobj/hex-dump.test | 59 + llvm/test/tools/llvm-readobj/hexdump.test | 32 - llvm/test/tools/llvm-readobj/print-hex.test | 26 - llvm/test/tools/llvm-readobj/string-dump-multi.s | 21 + llvm/test/tools/llvm-readobj/string-dump.test | 17 +- llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp | 104 +- llvm/tools/llvm-mca/Views/BottleneckAnalysis.h | 53 +- llvm/tools/llvm-mca/llvm-mca.cpp | 6 +- llvm/tools/llvm-objdump/MachODump.cpp | 11 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 1 + llvm/tools/llvm-readobj/COFFDumper.cpp | 5 + llvm/tools/llvm-readobj/ObjDumper.cpp | 209 +-- llvm/tools/llvm-readobj/ObjDumper.h | 6 +- llvm/tools/llvm-readobj/llvm-readobj.cpp | 8 +- llvm/tools/msbuild/source.extension.vsixmanifest | 14 +- llvm/unittests/IR/CMakeLists.txt | 1 + llvm/unittests/IR/VectorTypesTest.cpp | 164 ++ llvm/utils/TableGen/FixedLenDecoderEmitter.cpp | 140 +- llvm/utils/UpdateTestChecks/asm.py | 69 +- .../utils/gn/secondary/clang/lib/Frontend/BUILD.gn | 1 - llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn | 1 + llvm/utils/lit/lit/TestRunner.py | 1 + .../alg.modifying.operations/rotate.pass.cpp | 4 +- .../algorithms/alg.nonmodifying/for_each.pass.cpp | 2 +- .../algorithms/alg.nonmodifying/mismatch.pass.cpp | 2 +- .../numerics/numeric.ops/transform_scan.pass.cpp | 6 +- pstl/test/support/pstl_test_config.h | 2 + 422 files changed, 11856 insertions(+), 3361 deletions(-) create mode 100644 clang-tools-extra/clang-tidy/fuchsia/DefaultArgumentsCallsCheck.cpp copy clang-tools-extra/clang-tidy/fuchsia/{DefaultArgumentsCheck.h => DefaultArgum [...] delete mode 100644 clang-tools-extra/clang-tidy/fuchsia/DefaultArgumentsCheck.cpp create mode 100644 clang-tools-extra/clang-tidy/fuchsia/DefaultArgumentsDeclaratio [...] rename clang-tools-extra/clang-tidy/fuchsia/{DefaultArgumentsCheck.h => DefaultArg [...] create mode 100644 clang-tools-extra/clangd/refactor/tweaks/DumpAST.cpp rename clang-tools-extra/docs/clang-tidy/checks/{fuchsia-default-arguments.rst => [...] create mode 100644 clang-tools-extra/docs/clang-tidy/checks/fuchsia-default-argume [...] create mode 100644 clang-tools-extra/test/clang-tidy/fuchsia-default-arguments-calls.cpp rename clang-tools-extra/test/clang-tidy/{fuchsia-default-arguments.cpp => fuchsia [...] create mode 100644 clang/test/AST/ast-dump-decl-json.c create mode 100644 clang/test/AST/ast-dump-funcs-json.cpp create mode 100644 clang/test/CodeGen/arm-vfp16-arguments2.cpp delete mode 100644 libcxx/test/std/containers/associative/map/map.cons/deduct.fail.cpp delete mode 100644 libcxx/test/std/containers/associative/map/map.cons/deduct.pass.cpp delete mode 100644 libcxx/test/std/containers/associative/map/map.cons/deduct_cons [...] delete mode 100644 libcxx/test/std/containers/associative/multimap/multimap.cons/d [...] delete mode 100644 libcxx/test/std/containers/associative/multimap/multimap.cons/d [...] delete mode 100644 libcxx/test/std/containers/associative/multimap/multimap.cons/d [...] delete mode 100644 libcxx/utils/docker/debian9/Dockerfile create mode 100644 libcxx/utils/docker/debian9/Dockerfile.base create mode 100644 libcxx/utils/docker/debian9/Dockerfile.buildbot create mode 100644 libcxx/utils/docker/debian9/Dockerfile.clang create mode 100644 libcxx/utils/docker/debian9/Dockerfile.compiler_zoo create mode 100644 libcxx/utils/docker/debian9/Dockerfile.gcc delete mode 100755 libcxx/utils/docker/scripts/checkout_git.sh create mode 100755 libcxx/utils/docker/scripts/docker_update_bot.sh delete mode 100755 libcxx/utils/docker/scripts/run_buildbot_new.sh delete mode 100755 libcxxabi/lib/buildit create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 llvm/include/llvm/Support/ScalableSize.h rename llvm/lib/CodeGen/{ExpandISelPseudos.cpp => FinalizeISel.cpp} (68%) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir create mode 100644 llvm/test/CodeGen/AMDGPU/fold-readlane.mir create mode 100644 llvm/test/CodeGen/AMDGPU/gws-hazards.mir create mode 100644 llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll create mode 100644 llvm/test/CodeGen/PowerPC/legalize-vaarg.ll create mode 100644 llvm/test/CodeGen/RISCV/add-before-shl.ll create mode 100644 llvm/test/CodeGen/RISCV/tls-models.ll create mode 100644 llvm/test/CodeGen/SystemZ/int-add-18.mir create mode 100644 llvm/test/CodeGen/Thumb2/v8_deprecate_IT.ll create mode 100644 llvm/test/CodeGen/WebAssembly/simd-reductions.ll create mode 100644 llvm/test/CodeGen/X86/legalize-vaarg.ll create mode 100644 llvm/test/MC/ARM/mve-shifts.s create mode 100644 llvm/test/MC/Disassembler/ARM/mve-shifts.txt create mode 100644 llvm/test/Transforms/InstCombine/reassociate-nuw.ll create mode 100644 llvm/test/Verifier/llvm.loop.ll create mode 100644 llvm/test/Verifier/scalable-aggregates.ll create mode 100644 llvm/test/Verifier/scalable-global-vars.ll create mode 100644 llvm/test/tools/llvm-readobj/hex-dump-multi.s create mode 100644 llvm/test/tools/llvm-readobj/hex-dump.test delete mode 100644 llvm/test/tools/llvm-readobj/hexdump.test delete mode 100644 llvm/test/tools/llvm-readobj/print-hex.test create mode 100644 llvm/test/tools/llvm-readobj/string-dump-multi.s create mode 100644 llvm/unittests/IR/VectorTypesTest.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (b215f524 -> 66be2ecf)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig in repository toolchain/ci/base-artifacts. discards b215f524 0: update: llvm-linux: boot new 66be2ecf 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b215f524) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 175 +- 02-build_llvm/console.log | 11937 ++++++++++++++++----------------- 03-build_linux/console.log | 1616 ++--- 04-boot_linux/console.log | 438 +- console.log | 14166 ++++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 6 files changed, 14182 insertions(+), 14162 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[compiler-rt] branch master updated (4503b7125 -> 8be6b7799)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository compiler-rt. from 4503b7125 [Sanitizers] Fix sanitizer_posix_libcdep.cc compilation on So [...] new 8be6b7799 Revert r363633 "[CMake] Fix the value of `config.target_cflag [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: cmake/config-ix.cmake | 26 ----------------- test/asan/CMakeLists.txt | 19 +++---------- test/fuzzer/CMakeLists.txt | 11 ++------ test/tsan/CMakeLists.txt | 70 +++++++++++++++++++--------------------------- test/ubsan/CMakeLists.txt | 6 +--- 5 files changed, 35 insertions(+), 97 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig updated (961f9b6c746 -> f85aeb54a6a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig in repository toolchain/ci/gcc. from 961f9b6c746 PR ada/80590 adds 412e0a7b7e8 * config/mips/mips.c (mips_expand_builtin_insn): Swap the [...] adds 981b66dd433 Daily bump. adds f85aeb54a6a Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 8 +++ gcc/DATESTAMP | 2 +- gcc/config/mips/mips.c | 13 ++++ gcc/testsuite/ChangeLog | 6 ++ gcc/testsuite/gcc.target/mips/msa-fmadd.c | 101 ++++++++++++++++++++++++++++++ 5 files changed, 129 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/mips/msa-fmadd.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig updated (9137726eb6 -> a9f626606e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from 9137726eb6 Automatic date update in version.in adds 8bd3c5f928 Automatic date update in version.in adds a9f626606e Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig updated (95be4c9d -> 02ddf20e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 95be4c9d 0: update: binutils-gcc-linux: all new 02ddf20e 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (95be4c9d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 158 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 10522 ++++++------- 04-build_abe-stage1/console.log | 16975 ++++++++++----------- 05-build_linux/console.log | 821 +- 06-boot_linux/console.log | 2 +- console.log | 28977 ++++++++++++++++++------------------ jenkins/manifest.sh | 14 +- 8 files changed, 28951 insertions(+), 28952 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (1edcb734227 -> 301f3b0628a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 1edcb734227 [NFC][X86][MCA] Barcelona: add load/store/load-store-throug [...] new 301f3b0628a [yaml2obj/obj2yaml] - Make RawContentSection::Info Optional<> The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/ObjectYAML/ELFYAML.h | 2 +- lib/ObjectYAML/ELFYAML.cpp | 2 +- test/tools/obj2yaml/sections-info.yaml | 25 +++++ .../dynsymtab-implicit-sections-size-content.yaml | 8 +- test/tools/yaml2obj/implicit-sections-info.yaml | 113 +++++++++++++++++++++ .../symtab-implicit-sections-size-content.yaml | 8 +- tools/obj2yaml/elf2yaml.cpp | 3 +- tools/yaml2obj/yaml2elf.cpp | 12 ++- 8 files changed, 159 insertions(+), 14 deletions(-) create mode 100644 test/tools/obj2yaml/sections-info.yaml create mode 100644 test/tools/yaml2obj/implicit-sections-info.yaml -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[clang] branch master updated (a03a7fe0df -> cc8f460143)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from a03a7fe0df git-clang-format: Remove trailing whitespace in docstring. NFC. new cc8f460143 [RISCV] Mark TLS as supported The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Basic/Targets/RISCV.h | 1 - test/CodeGen/thread-specifier.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

Jump to page:

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits June 2019