Tcwg-commits April 2019

tcwg-commits@lists.linaro.org

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16351 discussions

[glibc] branch tuliom/libmvec updated (1dd33db8c3 -> 5722187ba5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch tuliom/libmvec in repository glibc. from 1dd33db8c3 PPC64: Add libmvec SIMD single-precision sine function. new 5722187ba5 PPC64: Add libmvec SIMD double-precision sincos function. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: NEWS | 1 + sysdeps/powerpc/bits/math-vector.h | 2 + sysdeps/powerpc/fpu/libm-test-ulps | 3 + sysdeps/powerpc/powerpc64/fpu/Versions | 1 + sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile | 6 +- .../fpu/multiarch/test-double-vlen2-wrappers.c | 2 + .../powerpc64/fpu/multiarch/vec_d_sincos2_vsx.c | 19 +++-- .../{vec_d_sin2_vsx.c => vec_d_sincos2_vsx.h} | 82 ++++++++++++++++++++-- .../sysv/linux/powerpc/powerpc64/libmvec.abilist | 1 + 9 files changed, 102 insertions(+), 15 deletions(-) copy support/xpthread_attr_setstack.c => sysdeps/powerpc/powerpc64/fpu/multiarch/v [...] copy sysdeps/powerpc/powerpc64/fpu/multiarch/{vec_d_sin2_vsx.c => vec_d_sincos2_vs [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[llvm] branch master updated (995a17c619c -> 878c0a9d38c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 995a17c619c [Tests] Add a few more tests for LoopPredication w/invariant loads new 878c0a9d38c Revert r358418: "[llvm-objdump] Simplify PrintHelpMessage() logic" The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../llvm-objdump/X86/macho-private-header.test | 2 +- tools/llvm-objdump/llvm-objdump.cpp | 37 ++++++++++++++++------ 2 files changed, 29 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[openmp] branch master updated (c1629ee -> 6c19876)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository openmp. from c1629ee [OpenMP] Exchange code in asm file for inline assembly new 6c19876 [OPENMP][NVPTX]Fix dynamic scheduling in L2+ SPMD parallel regions. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libomptarget/deviceRTLs/nvptx/src/libcall.cu | 3 ++- libomptarget/deviceRTLs/nvptx/src/loop.cu | 19 +++++++++++--- libomptarget/deviceRTLs/nvptx/src/parallel.cu | 2 +- .../nvptx/test/parallel/spmd_parallel_regions.cpp | 30 ++++++++++++++++++++++ 4 files changed, 48 insertions(+), 6 deletions(-) create mode 100644 libomptarget/deviceRTLs/nvptx/test/parallel/spmd_parallel_regions.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[clang] branch master updated (471eb8155d -> 5bb4348faf)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 471eb8155d Revert "[clang] Aligned allocation is actually supported in [...] new 5bb4348faf [clang-format] Fix -Wconversion-null warning in GCC The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: unittests/Format/FormatTest.cpp | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[glibc] branch tuliom/libmvec updated (3dce324f20 -> 1dd33db8c3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch tuliom/libmvec in repository glibc. from 3dce324f20 PPC64: Add libmvec SIMD single-precision cosine function. new 627066b299 PPC64: Add libmvec SIMD double-precision sine function. new 1dd33db8c3 PPC64: Add libmvec SIMD single-precision sine function. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: NEWS | 2 + sysdeps/powerpc/fpu/libm-test-ulps | 6 ++ sysdeps/powerpc/powerpc64/fpu/Versions | 2 +- sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile | 9 +- .../fpu/multiarch/test-double-vlen2-wrappers.c | 1 + .../fpu/multiarch/test-float-vlen4-wrappers.c | 1 + .../powerpc64/fpu/multiarch/vec_d_sin2_vsx.c | 101 +++++++++++++++++++++ .../powerpc64/fpu/multiarch/vec_d_trig_data.h | 44 +++++---- .../{vec_s_cosf4_vsx.c => vec_s_sinf4_vsx.c} | 94 ++++++++++--------- .../powerpc64/fpu/multiarch/vec_s_trig_data.h | 28 +++--- .../sysv/linux/powerpc/powerpc64/libmvec.abilist | 2 + 11 files changed, 213 insertions(+), 77 deletions(-) create mode 100644 sysdeps/powerpc/powerpc64/fpu/multiarch/vec_d_sin2_vsx.c copy sysdeps/powerpc/powerpc64/fpu/multiarch/{vec_s_cosf4_vsx.c => vec_s_sinf4_vsx [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[glibc] branch tuliom/libmvec updated (f29bf4633f -> 3dce324f20)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch tuliom/libmvec in repository glibc. from f29bf4633f PPC64: Add libmvec SIMD double-precision cosine function. new 3dce324f20 PPC64: Add libmvec SIMD single-precision cosine function. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: NEWS | 10 +- sysdeps/powerpc/fpu/libm-test-ulps | 3 + sysdeps/powerpc/powerpc64/fpu/Versions | 2 +- sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile | 10 +- ...len2-wrappers.c => test-float-vlen4-wrappers.c} | 6 +- .../powerpc64/fpu/multiarch/vec_s_cosf4_vsx.c | 109 +++++++++++++++++++++ .../powerpc64/fpu/multiarch/vec_s_trig_data.h | 72 ++++++++++++++ .../sysv/linux/powerpc/powerpc64/libmvec.abilist | 1 + 8 files changed, 205 insertions(+), 8 deletions(-) copy sysdeps/powerpc/powerpc64/fpu/multiarch/{test-double-vlen2-wrappers.c => test [...] create mode 100644 sysdeps/powerpc/powerpc64/fpu/multiarch/vec_s_cosf4_vsx.c create mode 100644 sysdeps/powerpc/powerpc64/fpu/multiarch/vec_s_trig_data.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO updated (96950f1fa98 -> 0fa94ee318d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO in repository toolchain/ci/llvm-project. from 96950f1fa98 [X86] Put the locked mi8 instrutions above the locked mi/mi [...] adds 5b92eb007b8 [X86] Redefine KUNPCK instructions to take a narrower sourc [...] adds 63fe2593ae5 llvm-undname: Fix another crash-on-invalid found by oss-fuzz adds ce1452ad27e gn build: Merge r358272 adds 6de31be67e7 gn build: Merge r358243 adds 274f305a418 gn build: Merge r358297 adds ae050d214b9 llvm-undname: Fix oss-fuzz-foudn crash-on-invalid with inco [...] adds d189680baa0 [GlobalISel] Introduce a CSEConfigBase class to allow targe [...] adds 946b1246d6c [GlobalISel] Enable CSE in the IRTranslator & legalizer for [...] adds 489f8255fcb [Sparc] Fix typo. NFC. adds abd87ff48b9 [X86] Regenerate checks for domain-reassignment.mir adds 60569363a58 [SelectionDAG] Use KnownBits::computeForAddSub/computeForAddCarry adds 43e92880acf [clangd] Reorder source files in CMakeLists adds 50a09670f0d [DWARF] Make DWARFDebugLine::ParsingState::RowNumber a loca [...] adds bd8a1ce7bbb [clang-format] [PR41170] Break after return type ignored wi [...] adds b93de4cd263 [DWARF] Fix DWARFVerifier::DieRangeInfo::intersects adds 42605f83d3e [DWARF] Delete redundant check in DWARFAddressRange::intersects adds dc8d8fb20b8 [Lookup] Invisible decls should not be ambiguous when renaming. adds f54328372b1 [NewPM] Add Option handling for SimplifyCFG adds 6a63e5aa7be [Transforms][ASan] Move findAllocaForValue() to Utils/Local [...] adds 0e17ab0fd2a Revert "[DWARF] Delete redundant check in DWARFAddressRange [...] adds a9ce09be033 [clangd] Bump clangd-index version for TemplateArgument changes adds 3992e9d229e Codegen: Fixed perf branch_weights in couple of tests. NFC. adds 38803920c49 [DebugInfo][Docs] Document variable location metadata trans [...] adds f56a436891e [DWARF] Fix DWARFVerifier::DieRangeInfo::contains adds 38c1bda9f64 [Docs] Correct some indentation muppetry that trips buildbots adds 301ed1cb49a [TableGen] Include schedule model name in diagnostic. adds e038fa7292c FileCheck [1/12]: Move variable table in new object adds 7a112c44ff4 [Docs] Switch a code block from LLVM to text adds 842be38162e [AMDGPU] Fixed incorrect test in vcnd/vcmp optimization adds 7844031d460 [MinGW] Remove some supefluous calls to MakeArgString. NFC. adds cdf126ebec1 [COFF] Link crtend.o as the last object file adds 19bb1d5739b [llvm-readobj] Reapply: Improve error message for --string-dump adds 4918738c070 [llvm-readelf] Correctly dump symbols whose section id is S [...] adds abcade08b5d gn build: Merge r358390 adds 9db00f7e5b3 DAG: propagate whether an arg is a pointer for CallingConv [...] adds 2be3f868f9c DAG: propagate ConsecutiveRegs flags to returns too. adds 9ef03dd20a5 [clangd] Wait for compile command in ASTWorker instead of C [...] adds 5db281cd4ed clang-format vs plugin: Visual Studio 2019 support adds 5e13cd2e61c [InstCombine] canonicalize fdiv after fmul if reassociation [...] adds b688a200e4c [llvm-objdump] Align instructions to a tab stop in disassem [...] adds c71433335ad [EarlyCSE] regenerate test checks; NFC adds f3e4f24ed74 [libc++] Make sure that the symbol differ takes into accoun [...] adds f2073321c93 [clang] Aligned allocation is actually supported in macosx 10.13 adds 5e165fba3ac [NFC] Add missing revision number in libc++ ABI changelog adds bb6cd8254c2 [clangd] Fallback to OrigD when SLoc is invalid adds 70921d4a86e Revert r358337: "[CommandLineParser] Add DefaultOption flag" adds 9d812f44994 [llvm-objdump] Reorganize cl::opt variables and move Mach-O [...] adds 8c1353dd14e [llvm-objdump] Delete unused forward declarations adds 523758ef5b5 [llvm-objdump] Wrap things in namespace llvm adds 204339a2348 [llvm-objdump] Simplify PrintHelpMessage() logic adds fbe64a2cfb4 [LoopPred] Hoist and of predicated checks where legal adds 0e0bb0e24a0 [EarlyCSE] add tests for selects with commuted operands (PR [...] adds 64041d7b907 llvm-undname: Fix nullptr deref on invalid conversion opera [...] adds 09e539fcaeb [PGO] Profile guided code size optimization. adds 3c3ccc00495 [libc++] Fix build failure with _LIBCPP_DEBUG=0 when iterat [...] adds 8d856488a89 Add slbfee instruction. adds 8e364c680fa [X86] Restore the pavg intrinsics. adds b85f74a283a [CommandLineParser] Add DefaultOption flag adds 5221532a4eb Fix header guard typo and build error. adds 3929c432e65 Add explicit dependency to MCDwarf.h in ARC backend. adds 4fe42214e24 [DEBUGINFO] Prevent Instcombine from dropping debuginfo whe [...] adds 8ae68f26489 [x86] update test checks; NFC adds e1e1bd7f9c4 [libc++] Fix debug_less test in C++03 adds e46d77d1d91 [LoopPred] Stop passing around builders [NFC] adds a54a11e22a3 [X86] Improve avx512-kconstraints-att_inline_asm.c to not b [...] adds 3d9b47c770d [X86] Block i32/i64 for 'k' and 'Yk' in getRegForInlineAsmC [...] new 0fa94ee318d Revert "[clang] Aligned allocation is actually supported in [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clangd/ClangdServer.cpp | 18 +- clang-tools-extra/clangd/ClangdServer.h | 3 - clang-tools-extra/clangd/Compiler.h | 2 +- .../clangd/GlobalCompilationDatabase.cpp | 9 +- clang-tools-extra/clangd/TUScheduler.cpp | 125 +++-- clang-tools-extra/clangd/TUScheduler.h | 14 +- clang-tools-extra/clangd/index/Serialization.cpp | 2 +- clang-tools-extra/clangd/index/SymbolCollector.cpp | 6 + clang-tools-extra/unittests/clangd/CMakeLists.txt | 2 +- clang-tools-extra/unittests/clangd/ClangdTests.cpp | 58 +++ .../unittests/clangd/CodeCompleteTests.cpp | 2 +- .../unittests/clangd/SymbolCollectorTests.cpp | 8 + .../unittests/clangd/TUSchedulerTests.cpp | 65 ++- clang/include/clang/Basic/BuiltinsX86.def | 6 + clang/include/clang/Tooling/Core/Lookup.h | 3 + clang/lib/Driver/ToolChains/MinGW.cpp | 16 +- clang/lib/Format/TokenAnnotator.h | 14 +- clang/lib/Headers/avx2intrin.h | 12 +- clang/lib/Headers/avx512bwintrin.h | 12 +- clang/lib/Headers/emmintrin.h | 12 +- clang/lib/Tooling/Core/Lookup.cpp | 21 +- .../Tooling/Refactoring/Rename/USRLocFinder.cpp | 4 +- clang/test/CodeGen/avx2-builtins.c | 16 +- .../CodeGen/avx512-kconstraints-att_inline_asm.c | 82 ++-- clang/test/CodeGen/avx512bw-builtins.c | 50 +- clang/test/CodeGen/avx512vlbw-builtins.c | 68 +-- clang/test/CodeGen/sse2-builtins.c | 16 +- .../source.extension.vsixmanifest.in | 2 +- clang/unittests/Format/FormatTest.cpp | 20 + clang/unittests/Tooling/LookupTest.cpp | 46 +- libcxx/include/algorithm | 9 + libcxx/lib/abi/CHANGELOG.TXT | 2 +- libcxx/test/libcxx/algorithms/debug_less.pass.cpp | 35 ++ libcxx/utils/libcxx/sym_check/diff.py | 6 +- lld/COFF/Driver.cpp | 33 +- lld/docs/ReleaseNotes.rst | 4 +- lld/test/COFF/Inputs/eh_frame_terminator-crtend.s | 3 + .../COFF/Inputs/eh_frame_terminator-otherfunc.s | 7 + lld/test/COFF/eh_frame_terminator.s | 26 ++ llvm/docs/SourceLevelDebugging.rst | 310 ++++++++++++ llvm/include/llvm/CodeGen/CSEConfigBase.h | 28 ++ llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h | 34 +- llvm/include/llvm/CodeGen/TargetCallingConv.h | 16 +- llvm/include/llvm/CodeGen/TargetPassConfig.h | 4 + .../llvm/DebugInfo/DWARF/DWARFAddressRange.h | 6 - llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLine.h | 3 - llvm/include/llvm/IR/IntrinsicsX86.td | 18 + llvm/include/llvm/Support/FileCheck.h | 63 ++- llvm/include/llvm/Target/TargetCallingConv.td | 9 + .../llvm/Transforms/Scalar/ConstantHoisting.h | 5 +- llvm/include/llvm/Transforms/Utils/Local.h | 4 + .../llvm/Transforms/Utils/SimplifyLibCalls.h | 5 + llvm/include/llvm/Transforms/Utils/SizeOpts.h | 34 ++ llvm/include/llvm/Transforms/Utils/UnrollLoop.h | 5 +- .../llvm/Transforms/Vectorize/LoopVectorize.h | 4 +- llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp | 20 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 21 +- llvm/lib/CodeGen/GlobalISel/Legalizer.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 92 ++-- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 40 ++ llvm/lib/CodeGen/TargetPassConfig.cpp | 7 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 4 +- llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp | 62 ++- llvm/lib/Demangle/MicrosoftDemangle.cpp | 20 +- llvm/lib/IR/AutoUpgrade.cpp | 36 +- llvm/lib/Passes/PassBuilder.cpp | 46 +- llvm/lib/Passes/PassRegistry.def | 6 +- llvm/lib/Support/CommandLine.cpp | 2 + llvm/lib/Support/FileCheck.cpp | 171 +++---- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 5 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 7 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 28 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 + .../Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp | 2 +- .../Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp | 1 + llvm/lib/Target/ARM/ARMTargetMachine.cpp | 6 + llvm/lib/Target/Mips/MipsTargetMachine.cpp | 6 + llvm/lib/Target/PowerPC/P9InstrResources.td | 1 + llvm/lib/Target/PowerPC/PPCInstrFormats.td | 1 + llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 + llvm/lib/Target/PowerPC/PPCSchedule.td | 1 + llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 4 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 45 +- llvm/lib/Target/X86/X86InstrAVX512.td | 20 +- llvm/lib/Target/X86/X86IntrinsicsInfo.h | 6 + llvm/lib/Target/X86/X86TargetMachine.cpp | 6 + .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/InstCombine/InstCombineInternal.h | 10 +- .../InstCombine/InstCombineMulDivRem.cpp | 8 + .../InstCombine/InstructionCombining.cpp | 29 +- .../Instrumentation/AddressSanitizer.cpp | 42 +- llvm/lib/Transforms/Scalar/ConstantHoisting.cpp | 18 +- llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp | 36 +- llvm/lib/Transforms/Scalar/LoopPredication.cpp | 94 ++-- .../lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp | 3 +- llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 24 +- llvm/lib/Transforms/Utils/CMakeLists.txt | 1 + llvm/lib/Transforms/Utils/Local.cpp | 47 +- llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 10 +- llvm/lib/Transforms/Utils/SizeOpts.cpp | 37 ++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 37 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 29 +- .../AArch64/GlobalISel/call-translator-ios.ll | 2 +- .../CodeGen/AArch64/GlobalISel/call-translator.ll | 2 +- .../CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-div.mir | 8 +- .../CodeGen/AArch64/GlobalISel/legalize-ext.mir | 5 +- .../legalize-load-store-s128-unaligned.mir | 3 +- .../AArch64/GlobalISel/legalize-merge-values.mir | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-phi.mir | 3 +- .../CodeGen/AArch64/GlobalISel/legalize-rem.mir | 5 +- .../CodeGen/AArch64/GlobalISel/legalize-shift.mir | 15 +- .../CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 10 +- .../CodeGen/AArch64/GlobalISel/translate-gep.ll | 21 +- llvm/test/CodeGen/AArch64/ragreedy-csr.ll | 4 +- .../AMDGPU/GlobalISel/legalize-addrspacecast.mir | 34 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 240 ++++------ .../CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir | 6 +- .../AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir | 6 +- .../AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir | 9 +- .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 240 ++++------ .../AMDGPU/GlobalISel/legalize-merge-values.mir | 37 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 300 +++++------- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir | 18 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 133 +++--- .../CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir | 18 +- .../ARM/GlobalISel/arm-legalize-bitcounts.mir | 2 - .../CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 8 - .../CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 16 +- .../ARM/GlobalISel/arm-legalize-load-store.mir | 12 +- .../test/CodeGen/Mips/GlobalISel/legalizer/add.mir | 12 +- .../test/CodeGen/Mips/GlobalISel/legalizer/mul.mir | 30 +- .../Mips/GlobalISel/legalizer/rem_and_div.mir | 92 ++-- .../test/CodeGen/Mips/GlobalISel/legalizer/sub.mir | 12 +- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll | 16 +- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll | 40 +- .../CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll | 36 +- llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll | 20 +- llvm/test/CodeGen/X86/GlobalISel/add-ext.ll | 79 ++-- llvm/test/CodeGen/X86/GlobalISel/gep.ll | 16 +- .../X86/GlobalISel/irtranslator-callingconv.ll | 38 +- .../X86/GlobalISel/legalize-memop-scalar-32.mir | 3 +- .../x86_64-irtranslator-struct-return.ll | 39 +- llvm/test/CodeGen/X86/asm-reject-vk32-vk64.ll | 31 ++ llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll | 16 +- .../CodeGen/X86/avx2-intrinsics-x86-upgrade.ll | 20 - llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll | 32 ++ llvm/test/CodeGen/X86/avx512bw-intrinsics.ll | 52 +++ llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll | 105 +++++ llvm/test/CodeGen/X86/domain-reassignment.mir | 7 +- llvm/test/CodeGen/X86/lea-2.ll | 37 +- llvm/test/CodeGen/X86/lea-3.ll | 104 ++--- llvm/test/CodeGen/X86/lea-4.ll | 42 +- llvm/test/CodeGen/X86/pr32282.ll | 19 +- llvm/test/CodeGen/X86/ragreedy-bug.ll | 4 +- llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 38 +- .../CodeGen/X86/sse2-intrinsics-x86-upgrade.ll | 40 -- llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll | 42 ++ llvm/test/Demangle/invalid-manglings.test | 20 + llvm/test/MC/PowerPC/ppc64-encoding-bookIII.s | 4 + llvm/test/Object/corrupt.test | 6 +- llvm/test/Other/new-pm-defaults.ll | 2 +- llvm/test/Other/new-pm-lto-defaults.ll | 1 + llvm/test/Other/new-pm-thinlto-defaults.ll | 2 +- llvm/test/Other/opt-O2-pipeline.ll | 2 + llvm/test/Other/opt-O3-pipeline.ll | 2 + llvm/test/Other/opt-Os-pipeline.ll | 2 + llvm/test/TableGen/SchedModelError.td | 18 + .../ARM/const-addr-no-neg-offset.ll | 59 +++ llvm/test/Transforms/EarlyCSE/commute.ll | 277 ++++++++--- .../test/Transforms/InstCombine/cast-mul-select.ll | 9 + llvm/test/Transforms/InstCombine/fast-math.ll | 4 +- llvm/test/Transforms/InstCombine/fmul-pow.ll | 5 +- llvm/test/Transforms/InstCombine/fmul.ll | 36 +- llvm/test/Transforms/InstCombine/fputs-opt-size.ll | 33 ++ llvm/test/Transforms/LoopLoadElim/opt-size.ll | 53 +++ llvm/test/Transforms/LoopPredication/basic.ll | 6 +- llvm/test/Transforms/LoopPredication/widened.ll | 6 +- .../Transforms/LoopUnroll/unroll-opt-attribute.ll | 46 ++ llvm/test/Transforms/LoopVectorize/optsize.ll | 43 ++ .../SimplifyCFG/ARM/switch-to-lookup-table.ll | 6 + .../Transforms/SimplifyCFG/CoveredLookupTable.ll | 1 + .../SimplifyCFG/ForwardSwitchConditionToPHI.ll | 3 + .../SimplifyCFG/X86/disable-lookup-table.ll | 1 + .../SimplifyCFG/X86/switch-covered-bug.ll | 2 + .../Transforms/SimplifyCFG/X86/switch-table-bug.ll | 2 + .../SimplifyCFG/X86/switch_to_lookup_table.ll | 2 +- .../SimplifyCFG/branch-fold-threshold.ll | 3 + llvm/test/Transforms/SimplifyCFG/multiple-phis.ll | 1 + llvm/test/Transforms/SimplifyCFG/no-md-sink.ll | 1 + .../SimplifyCFG/preserve-llvm-loop-metadata.ll | 1 + llvm/test/Transforms/SimplifyCFG/rangereduce.ll | 1 + .../Transforms/SimplifyCFG/sink-common-code.ll | 1 + llvm/test/Transforms/SimplifyCFG/switch_undef.ll | 1 + .../tools/llvm-objdump/X86/disassemble-align.s | 29 ++ .../llvm-objdump/X86/macho-private-header.test | 2 +- llvm/test/tools/llvm-readobj/basic.test | 4 +- .../tools/llvm-readobj/codeview-merging-cycle.test | 2 +- .../tools/llvm-readobj/elf-dynamic-malformed.test | 4 +- .../llvm-readobj/elf-malformed-pt-dynamic.test | 2 +- .../tools/llvm-readobj/elf-packed-relocs-error1.s | 2 +- .../tools/llvm-readobj/elf-packed-relocs-error2.s | 2 +- .../tools/llvm-readobj/elf-packed-relocs-error3.s | 2 +- .../tools/llvm-readobj/elf-packed-relocs-error4.s | 2 +- .../tools/llvm-readobj/elf-packed-relocs-error5.s | 2 +- llvm/test/tools/llvm-readobj/many-sections2.s | 24 + llvm/test/tools/llvm-readobj/mips-got.test | 4 +- llvm/test/tools/llvm-readobj/string-dump.test | 11 +- .../tools/llvm-readobj/thin-archive-paths.test | 4 +- llvm/test/tools/llvm-readobj/thin-archive.test | 2 +- llvm/test/tools/llvm-readobj/wasm-invalid.test | 2 +- llvm/tools/llvm-objdump/COFFDump.cpp | 17 +- llvm/tools/llvm-objdump/ELFDump.cpp | 19 +- llvm/tools/llvm-objdump/MachODump.cpp | 247 ++++++---- llvm/tools/llvm-objdump/WasmDump.cpp | 9 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 518 +++++++++------------ llvm/tools/llvm-objdump/llvm-objdump.h | 40 -- llvm/tools/llvm-readobj/ELFDumper.cpp | 7 +- llvm/tools/llvm-readobj/ObjDumper.cpp | 6 +- llvm/tools/llvm-readobj/llvm-readobj.cpp | 21 +- llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp | 42 ++ llvm/unittests/CodeGen/GlobalISel/CSETest.cpp | 2 +- .../DebugInfo/DWARF/DWARFDebugInfoTest.cpp | 84 ++-- llvm/unittests/Support/CMakeLists.txt | 1 + llvm/unittests/Support/CommandLineTest.cpp | 1 + llvm/unittests/Support/FileCheckTest.cpp | 52 +++ llvm/utils/TableGen/CodeGenSchedule.cpp | 3 +- .../clang-tools-extra/unittests/clangd/BUILD.gn | 1 + llvm/utils/gn/secondary/clang/lib/CodeGen/BUILD.gn | 1 + .../gn/secondary/llvm/unittests/Support/BUILD.gn | 2 + 235 files changed, 3940 insertions(+), 2610 deletions(-) create mode 100644 lld/test/COFF/Inputs/eh_frame_terminator-crtend.s create mode 100644 lld/test/COFF/Inputs/eh_frame_terminator-otherfunc.s create mode 100644 lld/test/COFF/eh_frame_terminator.s create mode 100644 llvm/include/llvm/CodeGen/CSEConfigBase.h create mode 100644 llvm/include/llvm/Transforms/Utils/SizeOpts.h create mode 100644 llvm/lib/Transforms/Utils/SizeOpts.cpp create mode 100644 llvm/test/CodeGen/X86/asm-reject-vk32-vk64.ll create mode 100644 llvm/test/TableGen/SchedModelError.td create mode 100644 llvm/test/tools/llvm-objdump/X86/disassemble-align.s create mode 100644 llvm/test/tools/llvm-readobj/many-sections2.s create mode 100644 llvm/unittests/Support/FileCheckTest.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO updated (37684a4cd6a -> 969b7ab65f2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO in repository toolchain/ci/gcc. from 37684a4cd6a 2019-04-14 Paul Thomas <pault(a)gcc.gnu.org> adds 4aab72939c3 2019-04-14 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds 008ae11cbb5 PR lto/89358 * g++.dg/lto/pr89358_0.C: New testcase. * g [...] adds 3b275f5d475 Daily bump. adds d71996db7a9 [NDS32] Provide one valid nds32 assembly instruction to che [...] adds 39ebb01497b 2019-04-15 Dominique d'Humieres <dominiq(a)gcc.gnu.org> adds 08dfb42801b [NDS32] Rewrite PIC/TLS patterns. adds 0be984ed89d [NDS32] nds32*-*-linux* target using init_array/finit_array [...] adds 48f42cbf10f [NDS32] Refine force unwind. Linux kernel only uses RT_SIGRETURN. adds fc01d804ff1 Reorganize cgraph_node::clone_of_p adds d8c947941f4 2019-04-15 Richard Biener <rguenther(a)suse.de> adds f9fd14f18d5 combine: Count auto_inc properly (PR89794) adds a5189c16a7e 2019-04-15 Richard Biener <rguenther(a)suse.de> adds 969b7ab65f2 2019-04-15 Richard Biener <rguenther(a)suse.de> No new revisions were added by this update. Summary of changes: ChangeLog | 9 ++++ gcc/ChangeLog | 68 +++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/cgraph.c | 30 ++++++----- gcc/combine.c | 60 +++++++++++++++------- gcc/config.gcc | 1 + gcc/config/nds32/nds32-md-auxiliary.c | 43 ++++++++++------ gcc/config/nds32/nds32-protos.h | 3 ++ gcc/config/nds32/nds32-relax-opt.c | 19 +++---- gcc/config/nds32/nds32.md | 27 ++++++++++ gcc/configure | 2 +- gcc/configure.ac | 2 +- gcc/ipa-devirt.c | 22 +++++++- gcc/testsuite/ChangeLog | 44 ++++++++++++++++ gcc/testsuite/g++.dg/ipa/pr89693.C | 52 +++++++++++++++++++ gcc/testsuite/g++.dg/lto/pr89358_0.C | 11 ++++ gcc/testsuite/g++.dg/lto/pr89358_1.C | 7 +++ gcc/testsuite/gcc.dg/guality/pr90074.c | 31 ++++++++++++ gcc/testsuite/gcc.dg/torture/pr88936-1.c | 27 ++++++++++ gcc/testsuite/gcc.dg/torture/pr88936-2.c | 22 ++++++++ gcc/testsuite/gcc.dg/torture/pr88936-3.c | 21 ++++++++ gcc/testsuite/gcc.dg/torture/pr89794.c | 24 +++++++++ gcc/testsuite/gcc.dg/torture/pr90020.c | 2 + gcc/testsuite/gcc.dg/torture/pr90071.c | 24 +++++++++ gcc/testsuite/gfortran.dg/bind_c_usage_33.f90 | 21 ++++++++ gcc/testsuite/gfortran.dg/bind_c_usage_33_c.c | 15 ++++++ gcc/tree-loop-distribution.c | 43 +++++++++++++--- gcc/tree-ssa-ccp.c | 25 ++++++---- gcc/tree-ssa-reassoc.c | 3 +- gcc/tree-ssa-structalias.c | 72 +++++++++++++++++++++++++++ gcc/tree.c | 18 +++++-- gcc/tree.h | 1 + libgcc/ChangeLog | 6 +++ libgcc/config/nds32/linux-unwind.h | 9 ++-- 34 files changed, 677 insertions(+), 89 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ipa/pr89693.C create mode 100644 gcc/testsuite/g++.dg/lto/pr89358_0.C create mode 100644 gcc/testsuite/g++.dg/lto/pr89358_1.C create mode 100644 gcc/testsuite/gcc.dg/guality/pr90074.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr88936-1.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr88936-2.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr88936-3.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr89794.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr90071.c create mode 100644 gcc/testsuite/gfortran.dg/bind_c_usage_33.f90 create mode 100644 gcc/testsuite/gfortran.dg/bind_c_usage_33_c.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO updated (d94c001b35 -> 4aa866af6b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO in repository toolchain/ci/binutils-gdb. from d94c001b35 Automatic date update in version.in adds 8669f96f0d Automatic date update in version.in adds 031254f211 [binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI adds e0991585ad [GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline adds e12437dc86 [binutils, ARM, 3/16] BF insns infrastructure with new bfd_r [...] adds e2b0ab5978 [binutils, ARM, 4/16] BF insns infrastructure with array of [...] adds e5d6e09ee6 [binutils, ARM, 5/16] BF insns infrastructure with new globa [...] adds 4389b29a5a [binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline adds f1c7f42126 [binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8 [...] adds 1caf72a584 [binutils, ARM, 8/16] BFL infrastructure with new global rel [...] adds 65d1bc05e8 [binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline adds 1889da7048 [binutils, ARM, 10/16] BFCSEL infrastructure with new global [...] adds f6b2b12db8 [binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M [...] adds 60f993ce17 [binutils, ARM, 12/16] Scalar Low Overhead loop instructions [...] adds 4b5a202f10 [binutils, ARM, 13/16] Add support for CLRM adds 6b0dd09474 [opcodes, ARM, 14/16] Add mode availability to coprocessor t [...] adds efd6b3591b [binutils, ARM, 15/16] Add support for VSCCLRM adds 32c36c3ce9 [binutils, ARM, 16/16] Add support to VLDR and VSTR of syste [...] adds ccb8d7e819 AArch64: Tidy up aarch64_gdbarch_init adds 4da037ef9d AArch64 SVE: Check for vector length change when getting gdbarch adds 48574d91bf AArch64 SVE: Support changing vector lengths for ptrace adds 86333705ae Skip print-map-discarded test for non-ELF targets adds 4aa866af6b Fix AMD64 return value ABI in expression evaluation No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 69 + bfd/archures.c | 1 + bfd/bfd-in2.h | 20 + bfd/cpu-arm.c | 1 + bfd/elf32-arm.c | 282 +++- bfd/libbfd.h | 7 + bfd/reloc.c | 32 + bfd/version.h | 2 +- binutils/ChangeLog | 4 + binutils/readelf.c | 2 +- elfcpp/ChangeLog | 12 + elfcpp/arm.h | 7 +- gas/ChangeLog | 201 +++ gas/config/tc-arm.c | 1484 ++++++++++++++++----- gas/doc/c-arm.texi | 11 + gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.d | 4 + gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l | 16 + gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s | 23 + gas/testsuite/gas/arm/archv8m_1m-cmse-main.d | 57 + gas/testsuite/gas/arm/archv8m_1m-cmse-main.s | 54 + gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d | 203 +++ gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 270 ++++ gas/testsuite/gas/arm/armv8.1-m.main-hp.d | 75 ++ gas/testsuite/gas/arm/armv8_1-m-bf-bad.d | 4 + gas/testsuite/gas/arm/armv8_1-m-bf-bad.l | 9 + gas/testsuite/gas/arm/armv8_1-m-bf-bad.s | 14 + gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d | 4 + gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l | 7 + gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s | 12 + gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d | 14 + gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s | 12 + gas/testsuite/gas/arm/armv8_1-m-bf-rel.d | 10 + gas/testsuite/gas/arm/armv8_1-m-bf-rel.s | 5 + gas/testsuite/gas/arm/armv8_1-m-bf.d | 13 + gas/testsuite/gas/arm/armv8_1-m-bf.s | 12 + gas/testsuite/gas/arm/armv8_1-m-bfcsel.d | 12 + gas/testsuite/gas/arm/armv8_1-m-bfcsel.s | 12 + gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d | 4 + gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l | 9 + gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s | 14 + gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d | 10 + gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s | 5 + gas/testsuite/gas/arm/armv8_1-m-bfl.d | 13 + gas/testsuite/gas/arm/armv8_1-m-bfl.s | 12 + gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d | 4 + gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l | 7 + gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s | 12 + gas/testsuite/gas/arm/armv8_1-m-loloop.d | 17 + gas/testsuite/gas/arm/armv8_1-m-loloop.s | 14 + gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d | 13 + gdb/ChangeLog | 27 + gdb/aarch64-linux-nat.c | 36 + gdb/aarch64-tdep.c | 92 +- gdb/amd64-tdep.c | 44 +- gdb/nat/aarch64-sve-linux-ptrace.c | 92 +- gdb/nat/aarch64-sve-linux-ptrace.h | 12 +- gdb/testsuite/ChangeLog | 5 + gdb/testsuite/gdb.arch/amd64-eval.cc | 120 ++ gdb/testsuite/gdb.arch/amd64-eval.exp | 43 + include/ChangeLog | 21 + include/elf/arm.h | 6 +- include/opcode/arm.h | 6 + ld/ChangeLog | 29 + ld/testsuite/ld-arm/arm-elf.exp | 10 + ld/testsuite/ld-arm/attr-merge-13.attr | 6 + ld/testsuite/ld-arm/attr-merge-13a.s | 5 + ld/testsuite/ld-arm/attr-merge-13b.s | 5 + ld/testsuite/ld-arm/bf.d | 14 + ld/testsuite/ld-arm/bf.s | 19 + ld/testsuite/ld-arm/bfcsel.d | 18 + ld/testsuite/ld-arm/bfcsel.s | 25 + ld/testsuite/ld-arm/bfl.d | 14 + ld/testsuite/ld-arm/bfl.s | 19 + ld/testsuite/ld-gc/gc.exp | 4 +- opcodes/ChangeLog | 73 + opcodes/arm-dis.c | 1070 +++++++++------ 76 files changed, 4031 insertions(+), 895 deletions(-) create mode 100644 gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.d create mode 100644 gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.l create mode 100644 gas/testsuite/gas/arm/archv8m_1m-cmse-main-bad.s create mode 100644 gas/testsuite/gas/arm/archv8m_1m-cmse-main.d create mode 100644 gas/testsuite/gas/arm/archv8m_1m-cmse-main.s create mode 100644 gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d create mode 100644 gas/testsuite/gas/arm/armv8.1-m.main-fp.d create mode 100644 gas/testsuite/gas/arm/armv8.1-m.main-hp.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-bad.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-bad.l create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-bad.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-rel.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf-rel.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bf.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfcsel.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfcsel.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl-bad.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl-bad.l create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl-bad.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl-rel.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-bfl.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop-bad.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop-bad.l create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop-bad.s create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop.d create mode 100644 gas/testsuite/gas/arm/armv8_1-m-loloop.s create mode 100644 gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d create mode 100644 gdb/testsuite/gdb.arch/amd64-eval.cc create mode 100644 gdb/testsuite/gdb.arch/amd64-eval.exp create mode 100644 ld/testsuite/ld-arm/attr-merge-13.attr create mode 100644 ld/testsuite/ld-arm/attr-merge-13a.s create mode 100644 ld/testsuite/ld-arm/attr-merge-13b.s create mode 100644 ld/testsuite/ld-arm/bf.d create mode 100644 ld/testsuite/ld-arm/bf.s create mode 100644 ld/testsuite/ld-arm/bfcsel.d create mode 100644 ld/testsuite/ld-arm/bfcsel.s create mode 100644 ld/testsuite/ld-arm/bfl.d create mode 100644 ld/testsuite/ld-arm/bfl.s -- To stop receiving notification emails like this one, please contact the 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6 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO updated (4db3e4be -> ce82cb0d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-arm-spec2k6-Oz_LTO in repository toolchain/ci/base-artifacts. discards 4db3e4be 0: good: binutils-gcc-glibc-llvm: -1 new ce82cb0d 0: good: binutils-gcc-glibc-llvm: -1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4db3e4be) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk/llvm-master-arm-spec [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 120 +- 02-prepare_abe/console.log | 212 +- 03-build_abe-binutils/console.log | 10635 +-- 04-build_abe-stage1/console.log | 19921 +++--- 05-build_abe-linux/console.log | 236 +- 06-build_abe-glibc/console.log | 38944 +++++------ 07-build_abe-stage2/console.log | 46722 +++++++------ 08-build_llvm-true/console.log | 11387 ++-- 09-benchmark/benchmark.log | 14 +- 09-benchmark/console.log | 74 +- 11-update_baseline/console.log | 2 +- console.log | 128253 +++++++++++++++++------------------ jenkins/manifest.sh | 16 +- 13 files changed, 128175 insertions(+), 128361 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

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