Tcwg-commits April 2019

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16351 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig updated (f7043f6281 -> 4c7c79dd98)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig in repository toolchain/ci/binutils-gdb. from f7043f6281 PR24402, global buffer overflow in symtab_finalize adds 8828efdb24 Add myself to gdb/MAINTAINERS adds 52093e1b93 Add gdb.Value.format_string () adds 34ef62f465 [GAS, Arm] CLI with architecture sensitive extensions adds 9d1447e09d Destroy allocated values when exiting GDB adds 05caa1d236 Handle DW_AT_ranges when reading partial symtabs adds c29705b71a Fix internal error and improve 'set debug infrun 1'/target w [...] adds 8bdc16587e gdb: Add $_cimag and $_creal internal functions adds d7df654955 gdb/fortran: Handle internal function calls adds 4c7c79dd98 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gas/ChangeLog | 61 ++ gas/config/tc-arm.c | 316 ++++++- gas/doc/c-arm.texi | 167 +++- .../gas/arm/armv8-2-fp16-scalar-bad-ext.d | 4 + gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d | 75 ++ .../gas/arm/armv8-2-fp16-scalar-thumb-ext.d | 75 ++ gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d | 159 ++++ .../gas/arm/armv8-2-fp16-simd-thumb-ext.d | 159 ++++ .../gas/arm/armv8-2-fp16-simd-warning-ext.d | 4 + .../gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d | 4 + gas/testsuite/gas/arm/armv8_2+rdma-ext.d | 79 ++ gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d | 249 ++++++ gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d | 249 ++++++ gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d | 3 + gas/testsuite/gas/arm/armv8_3-a-fp-ext.d | 16 + gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d | 249 ++++++ gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d | 3 + gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d | 249 ++++++ gas/testsuite/gas/arm/armv8m.main+fp.d | 32 + gas/testsuite/gas/arm/armv8m.main+fp.dp.d | 63 ++ gas/testsuite/gas/arm/attr-ext-fpv5-d16.d | 14 + gas/testsuite/gas/arm/attr-ext-fpv5.d | 15 + gas/testsuite/gas/arm/attr-ext-idiv.d | 15 + gas/testsuite/gas/arm/attr-ext-mp.d | 15 + gas/testsuite/gas/arm/attr-ext-neon-fp16.d | 20 + ...attr-mfpu-neon-fp16.d => attr-ext-neon-vfpv3.d} | 10 +- gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d | 19 + gas/testsuite/gas/arm/attr-ext-sec.d | 15 + gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d | 21 + gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d | 14 + gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d | 20 + .../{attr-mfpu-neon-fp16.d => attr-ext-vfpv3.d} | 11 +- gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d | 17 + gas/testsuite/gas/arm/attr-ext-vfpv3xd.d | 16 + gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d | 18 + gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d | 15 + gas/testsuite/gas/arm/attr-ext-vfpv4.d | 18 + gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d | 8 +- gas/testsuite/gas/arm/dotprod-mandatory-ext.d | 297 +++++++ gas/testsuite/gas/arm/fpv5-d16.s | 58 ++ gas/testsuite/gas/arm/fpv5-sp-d16.s | 27 + gdb/ChangeLog | 38 + gdb/MAINTAINERS | 1 + gdb/NEWS | 11 + gdb/doc/ChangeLog | 5 + gdb/doc/gdb.texinfo | 11 + gdb/doc/python.texi | 80 ++ gdb/dwarf2read.c | 55 +- gdb/eval.c | 12 +- gdb/gnu-nat.c | 10 +- gdb/infrun.c | 78 +- gdb/python/py-value.c | 164 ++++ gdb/target/waitstatus.c | 3 +- gdb/testsuite/ChangeLog | 18 + gdb/testsuite/gdb.base/complex-parts.c | 50 ++ gdb/testsuite/gdb.base/complex-parts.exp | 62 ++ gdb/testsuite/gdb.base/default.exp | 2 + gdb/testsuite/gdb.dwarf2/dw2-ranges-main.c | 19 + gdb/testsuite/gdb.dwarf2/dw2-ranges-psym.c | 46 + gdb/testsuite/gdb.dwarf2/dw2-ranges-psym.exp | 138 +++ gdb/testsuite/gdb.python/py-format-string.c | 118 +++ gdb/testsuite/gdb.python/py-format-string.exp | 957 +++++++++++++++++++++ gdb/testsuite/gdb.python/py-format-string.py | 49 ++ gdb/testsuite/gdb.python/py-function.exp | 8 +- gdb/testsuite/lib/gdb.exp | 8 + gdb/top.c | 6 + gdb/value.c | 60 ++ gdb/value.h | 4 + include/ChangeLog | 11 + include/opcode/arm.h | 31 +- 71 files changed, 4795 insertions(+), 141 deletions(-) create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-scalar-ext.d create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-simd-ext.d create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d create mode 100644 gas/testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_2+rdma-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_2-a-fp16_ext.d create mode 100644 gas/testsuite/gas/arm/armv8_3-a-fp-bad-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_3-a-fp-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_3-a-fp16-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_3-a-simd-bad-ext.d create mode 100644 gas/testsuite/gas/arm/armv8_4-a-fp16-ext.d create mode 100644 gas/testsuite/gas/arm/armv8m.main+fp.d create mode 100644 gas/testsuite/gas/arm/armv8m.main+fp.dp.d create mode 100644 gas/testsuite/gas/arm/attr-ext-fpv5-d16.d create mode 100644 gas/testsuite/gas/arm/attr-ext-fpv5.d create mode 100644 gas/testsuite/gas/arm/attr-ext-idiv.d create mode 100644 gas/testsuite/gas/arm/attr-ext-mp.d create mode 100644 gas/testsuite/gas/arm/attr-ext-neon-fp16.d copy gas/testsuite/gas/arm/{attr-mfpu-neon-fp16.d => attr-ext-neon-vfpv3.d} (53%) create mode 100644 gas/testsuite/gas/arm/attr-ext-neon-vfpv4.d create mode 100644 gas/testsuite/gas/arm/attr-ext-sec.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv3-d16.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv3-fp16.d copy gas/testsuite/gas/arm/{attr-mfpu-neon-fp16.d => attr-ext-vfpv3.d} (51%) create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv3xd-fp.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv3xd.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv4-d16.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d create mode 100644 gas/testsuite/gas/arm/attr-ext-vfpv4.d create mode 100644 gas/testsuite/gas/arm/dotprod-mandatory-ext.d create mode 100644 gas/testsuite/gas/arm/fpv5-d16.s create mode 100644 gas/testsuite/gas/arm/fpv5-sp-d16.s create mode 100644 gdb/testsuite/gdb.base/complex-parts.c create mode 100644 gdb/testsuite/gdb.base/complex-parts.exp create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-ranges-main.c create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-ranges-psym.c create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-ranges-psym.exp create mode 100644 gdb/testsuite/gdb.python/py-format-string.c create mode 100644 gdb/testsuite/gdb.python/py-format-string.exp create mode 100644 gdb/testsuite/gdb.python/py-format-string.py -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig updated (30b6356 -> aef94de)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards 30b6356 0: good: binutils-gcc-linux: boot new aef94de 0: good: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (30b6356) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 182 +- 03-build_abe-binutils/console.log | 10416 ++++++------ 04-build_abe-stage1/console.log | 18870 ++++++++++----------- 05-build_linux/console.log | 1909 +-- 06-boot_linux/console.log | 384 +- console.log | 31910 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 8 files changed, 32525 insertions(+), 31286 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (2e1bf89e3a8 -> 9d1449246dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project. from 2e1bf89e3a8 [X86] Use ISD::INTRINSIC_VOID in getTgtMemIntrinsic for tru [...] adds 38a82413210 [Linux/x86] Fix writing of non-gpr registers on newer processors adds d83fb24533e [ELF] Rename SyntheticSection::empty to more appropriate is [...] adds 3091884e25d [RISCV] Add seto pattern expansion adds e8c3136994b [X86][SSE] Add fcmp constant folding tests adds 7af32444b9b [X86] Fix a test from r357317 adds d9f6ee1c3cc [X86MacroFusion][NFC] Add more tests. adds 97d1bc44544 [InstCombine] eliminate commuted select-shuffles + binop (PR41304) adds bf55c4e3e39 [LLD][COFF] Early dependency detection adds 7e062c9b1f9 [X86] Make post-ra scheduling macrofusion-aware. adds d66a47f90a7 [InstCombine] Handle vector gep with scalar argument in eva [...] adds 0276b943566 InstSimplify: Add baseline test for upcoming change adds 3e527cd823a Revert "[InstCombine] Handle vector gep with scalar argumen [...] adds ebf90db0848 X86: Fix override warning adds 150a7ec2dc0 [InstCombine] Handle vector gep with scalar argument in eva [...] adds e106f25f056 [OPENMP] Check that allocated variables are used in private [...] adds 30c2f20e558 Fix builder. adds efe376add6a [AArch64] Add v8.5-a Memory Tagging GMID_EL1 register adds da20f5ca745 [RISCV] Generate address sequences suitable for mcmodel=medium adds 60768cd8967 [ASTImporter] Make ODR error handling configurable adds 9142b8ef1b9 [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions adds 44668ae7c7d [RISCV] Attach VK_RISCV_CALL to symbols upon creation adds 3d233d5d4d8 [AArch64] Add v8.5-a Memory Tagging STZGM instruction adds 22990ba11c2 gn build: Merge r357383 adds d8519f4a7db [lldb] [Process/elf-core] Support aarch64 NetBSD core dumps adds 0a30f33ce21 [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. adds 95c585e258f [pstl] Indent preprocessor directives as part of the clang- [...] adds 410f32ce7c6 [ASTImporter] Convert ODR diagnostics inside ASTImporter im [...] adds 9ef7708bbbf [Tests] Add tests for a possible loop predication transform [...] adds 7eee62b5d4e [Tests] Autogen all the LoopPredication tests adds dae5ff2b7b8 Attempt to fix failing buildbot (ppc64le) adds d109e2a7c3b [LoopPred] Delete the old condition expressions if unused adds 6c21ccd245b [NVPTX] Fix the codegen for llvm.round. adds 05e3e554b47 [LoopPred] Be uniform about proving generated conditions adds 2a67c910764 Commit accidentally omitted test case. adds efa6d803c62 Fix PR41130 - 'operator/ of std::chrono::duration and custo [...] adds 2b0c7abba35 [libc++] Declare std::tuple_element as struct instead of class adds 84c8baeef71 [OPENMP]Allocate clause allocator in target region. adds ecad92b0680 Fix PR#41323 'Race condition in steady_clock::now for _LIBC [...] adds f6c04ad4860 [SLP] getGatherCost and isFullyVectorizableTinyTree are con [...] adds 58e7642669b [CodeGen] Generate follow-up metadata for loops with more t [...] adds b06935fa8c1 [SLP] getVectorElementSize and isTreeTinyAndNotFullyVectori [...] adds a9e847238e1 ELF: Perform per-section .ARM.exidx processing during combi [...] adds f2baddb0fc4 [llvm-objcopy] Add --keep-symbols option adds 4307172b841 [X86] Classify the AVX512 rounding control operand as X86:: [...] adds 62bcf736834 [Process] Fix WriteMemory return value adds 3c023420d1d [NFC][LLD] Specify namespaces explicity to fix build failur [...] adds a735985abe8 [pstl] Mangle the parallel_strict_scan backend function adds beb6efb42ec [libcxx] Make sure reference_wrapper works with incomplete types adds c791a20b429 [API] Add SBReproducer to LLDB.h adds 66d7eb97045 Not all blocks are reachable from entry. Don't assume they are. adds 4665aca8ca7 [lldb-vscode] Add logic to handle EOF when reading from lld [...] adds 1e1e212d274 [NFC] Remove dead parameter "FreeInLoop", fix some typos an [...] adds 533fe617ac6 [Process] Use early returns in Process::WriteMemory (NFC) adds 1cd4216c75a Fix clangd unittest _WIN32 ifdef adds dd245c4f8fe [CMake] Only the Python scirpt interpreter should link agai [...] adds e44c20a68d2 [AArch64][GlobalISe] Select STRQui for stores into v264s in [...] adds f608678f1f3 [LoopPred] Rename a variable to simply a future patch [NFC] adds 73af6ef2e75 [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz. adds 3813fe0bda8 [ARM] Optimize expressions like "return x != 0;" for Thumb1. adds 294e07cf034 AMDGPU: Fix test filename adds 9bef688bc29 [AMDGPU] Add more test cases of D59608. adds fa0a2c529bc InstSimplify: Add missing case from r357386 adds c5903c935c2 [X86] Use unsigned type for opcodes throughout X86FixupLEAs. adds c1330159754 [X86] Autogenerate complete checks. NFC adds 536383a3548 [X86] Add test cases to fixup-lea.ll for optsize and no siz [...] adds c0ebfbe3f32 Add an optional list of blocks to avoid when looking for a [...] adds adb3ece2164 [LoopPredication] Simplify widenable condition handling [NFC] adds 60a8816c2fc [compiler-rt][test] Make instrprof-set-dir-mode test tolera [...] adds 9d1449246dd ar_to_bc.sh: replace readlink -f with custom relative path [...] No new revisions were added by this update. Summary of changes: .../unittests/clangd/JSONTransportTests.cpp | 4 +- clang/include/clang/AST/ASTStructuralEquivalence.h | 4 + clang/include/clang/Basic/DiagnosticASTKinds.td | 72 +- clang/include/clang/Basic/DiagnosticGroups.td | 1 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 5 + clang/lib/AST/ASTImporter.cpp | 28 +- clang/lib/AST/ASTStructuralEquivalence.cpp | 161 ++- clang/lib/CodeGen/CGLoopInfo.cpp | 540 ++++++++-- clang/lib/CodeGen/CGLoopInfo.h | 84 +- clang/lib/Sema/SemaOpenMP.cpp | 366 ++++--- clang/test/CodeGenCXX/pragma-followup_inner.cpp | 42 + clang/test/CodeGenCXX/pragma-followup_outer.cpp | 41 + .../pragma-loop-safety-imperfectly_nested.cpp | 4 +- .../test/CodeGenCXX/pragma-loop-safety-nested.cpp | 4 +- clang/test/CodeGenCXX/pragma-loop-safety-outer.cpp | 2 +- clang/test/CodeGenCXX/pragma-loop-safety.cpp | 10 +- clang/test/CodeGenCXX/pragma-loop.cpp | 59 +- clang/test/CodeGenCXX/pragma-unroll-and-jam.cpp | 2 +- clang/test/OpenMP/allocate_messages.cpp | 2 + clang/test/OpenMP/nvptx_allocate_messages.cpp | 6 + clang/test/OpenMP/simd_metadata.c | 6 +- .../symbolizer/scripts/ar_to_bc.sh | 4 +- compiler-rt/test/profile/instrprof-set-dir-mode.c | 6 +- libcxx/include/__tuple | 17 +- libcxx/include/array | 5 +- libcxx/include/chrono | 38 +- libcxx/include/span | 3 +- libcxx/include/tuple | 4 +- libcxx/include/utility | 10 +- libcxx/src/chrono.cpp | 21 +- .../refwrap/refwrap.const/ctor.incomplete.pass.cpp | 41 + .../refwrap.helpers/cref.incomplete.pass.cpp | 42 + .../refwrap.helpers/ref.incomplete.pass.cpp | 42 + .../refwrap.invoke/invoke.incomplete.fail.cpp | 37 + libcxx/test/std/utilities/time/rep.h | 36 + .../time.duration.arithmetic/op_divide=.pass.cpp | 10 + .../op_mod=duration.pass.cpp | 10 + .../time.duration.arithmetic/op_mod=rep.pass.cpp | 15 + .../time.duration.arithmetic/op_times=.pass.cpp | 10 + .../time.duration.nonmember/op_divide_rep.pass.cpp | 16 +- .../time.duration.nonmember/op_mod_rep.pass.cpp | 16 +- .../time.duration.nonmember/op_times_rep.pass.cpp | 16 + .../tuple.helper/tuple.include.array.pass.cpp | 3 +- .../tuple.helper/tuple_element.fail.cpp | 3 +- .../tuple.helper/tuple_element.pass.cpp | 3 +- .../tuple_size_structured_bindings.pass.cpp | 3 +- libcxx/www/cxx2a_status.html | 2 +- lld/COFF/CMakeLists.txt | 1 + lld/COFF/DebugTypes.cpp | 88 ++ lld/COFF/DebugTypes.h | 51 + lld/COFF/InputFiles.cpp | 56 ++ lld/COFF/InputFiles.h | 8 + lld/COFF/PDB.cpp | 97 +- lld/ELF/SyntheticSections.cpp | 119 ++- lld/ELF/SyntheticSections.h | 42 +- lld/ELF/Writer.cpp | 31 +- lldb/include/lldb/API/LLDB.h | 1 + .../gdb_remote_client/TestWriteMemory.py | 29 + .../postmortem/netbsd-core/1lwp_SIGSEGV.aarch64 | Bin 0 -> 9088 bytes .../netbsd-core/1lwp_SIGSEGV.aarch64.core | Bin 0 -> 225728 bytes .../netbsd-core/2lwp_process_SIGSEGV.aarch64 | Bin 0 -> 13192 bytes .../netbsd-core/2lwp_process_SIGSEGV.aarch64.core | Bin 0 -> 246936 bytes .../postmortem/netbsd-core/2lwp_t2_SIGSEGV.aarch64 | Bin 0 -> 11848 bytes .../netbsd-core/2lwp_t2_SIGSEGV.aarch64.core | Bin 0 -> 251904 bytes .../postmortem/netbsd-core/TestNetBSDCore.py | 15 + .../lldbsuite/test/tools/lldb-vscode/vscode.py | 76 +- .../Linux/NativeRegisterContextLinux_x86_64.cpp | 119 ++- .../Linux/NativeRegisterContextLinux_x86_64.h | 3 +- .../Plugins/Process/elf-core/ProcessElfCore.cpp | 26 + .../Plugins/Process/elf-core/RegisterUtilities.h | 5 + .../Plugins/Process/elf-core/ThreadElfCore.cpp | 3 + lldb/source/Target/Process.cpp | 105 +- lldb/unittests/Interpreter/CMakeLists.txt | 5 - .../ScriptInterpreter/Python/CMakeLists.txt | 4 +- llvm/include/llvm/Analysis/CFG.h | 25 +- llvm/include/llvm/CodeGen/MachineBasicBlock.h | 11 + llvm/lib/Analysis/BasicAliasAnalysis.cpp | 2 +- llvm/lib/Analysis/CFG.cpp | 76 +- llvm/lib/Analysis/CaptureTracking.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 5 +- llvm/lib/CodeGen/DwarfEHPrepare.cpp | 2 +- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 13 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 3 +- llvm/lib/Target/AArch64/AArch64SystemOperands.td | 1 + .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 9 - .../AArch64/Disassembler/AArch64Disassembler.cpp | 27 - llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 12 +- llvm/lib/Target/AMDGPU/CMakeLists.txt | 2 +- llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp | 417 -------- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 17 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 + llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 5 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 221 +++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 21 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 24 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 104 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 4 + llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 9 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 34 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 6 +- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 45 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 100 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 16 +- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 4 + llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 4 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 9 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 2 + llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 5 + .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 +- llvm/lib/Target/X86/X86FixupLEAs.cpp | 25 +- llvm/lib/Target/X86/X86InstrInfo.td | 3 +- llvm/lib/Target/X86/X86Subtarget.cpp | 6 + llvm/lib/Target/X86/X86Subtarget.h | 3 + .../InstCombine/InstCombineVectorOps.cpp | 9 +- .../InstCombine/InstructionCombining.cpp | 24 + llvm/lib/Transforms/Scalar/LICM.cpp | 27 +- llvm/lib/Transforms/Scalar/LoopPredication.cpp | 43 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 22 +- .../GlobalISel/legalize-load-store-fewerElts.mir | 6 +- .../CodeGen/AArch64/GlobalISel/select-store.mir | 22 + .../CodeGen/AMDGPU/atomic_optimizations_buffer.ll | 5 +- .../AMDGPU/atomic_optimizations_global_pointer.ll | 8 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 4 +- .../AMDGPU/atomic_optimizations_raw_buffer.ll | 4 +- .../AMDGPU/atomic_optimizations_struct_buffer.ll | 4 +- llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll | 32 + llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir | 185 ---- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 3 - llvm/test/CodeGen/AMDGPU/uaddo.ll | 27 + llvm/test/CodeGen/AMDGPU/usubo.ll | 51 + llvm/test/CodeGen/AMDGPU/wqm.mir | 2 +- llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 188 ++++ llvm/test/CodeGen/ARM/fold-stack-adjust.ll | 48 +- llvm/test/CodeGen/ARM/select-imm.ll | 48 +- llvm/test/CodeGen/NVPTX/f16-instructions.ll | 8 +- llvm/test/CodeGen/NVPTX/f16x2-instructions.ll | 13 +- llvm/test/CodeGen/NVPTX/math-intrins.ll | 12 +- llvm/test/CodeGen/RISCV/codemodel-lowering.ll | 80 ++ llvm/test/CodeGen/RISCV/double-br-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/double-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/double-select-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/float-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/float-select-fcmp.ll | 8 - .../Thumb/umulo-128-legalisation-lowering.ll | 235 ++--- .../Thumb/umulo-32-legalisation-lowering.ll | 15 +- llvm/test/CodeGen/X86/fcmp-constant.ll | 278 ++++++ llvm/test/CodeGen/X86/fixup-lea.ll | 190 +++- llvm/test/CodeGen/X86/testb-je-fusion.ll | 303 ++++-- llvm/test/CodeGen/X86/win64-nosse-error.ll | 2 +- llvm/test/MC/AArch64/armv8.5a-mte-error.s | 106 +- llvm/test/MC/AArch64/armv8.5a-mte.s | 42 +- .../AArch64/armv8.5a-mte-unpredictable.txt | 7 - llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt | 31 +- llvm/test/ThinLTO/X86/builtin-nostrip.ll | 59 ++ ...-amdgpu-dx10.ll => inline-amdgpu-dx10-clamp.ll} | 0 .../Transforms/InstCombine/vec-binop-select.ll | 71 +- .../Transforms/InstCombine/vec_gep_scalar_arg.ll | 16 + .../Transforms/InstSimplify/round-intrinsics.ll | 143 +++ llvm/test/Transforms/LoopPredication/basic.ll | 1035 +++++++++++++++----- .../basic_widenable_branch_guards.ll | 490 ++++++++- .../Transforms/LoopPredication/invariant_load.ll | 246 +++++ llvm/test/Transforms/LoopPredication/nested.ll | 223 ++++- .../Transforms/LoopPredication/profitability.ll | 89 +- llvm/test/Transforms/LoopPredication/reverse.ll | 229 ++++- llvm/test/Transforms/LoopPredication/visited.ll | 42 +- llvm/test/Transforms/LoopPredication/widened.ll | 142 ++- llvm/test/tools/llvm-objcopy/ELF/keep-symbol.test | 7 + llvm/tools/llvm-objcopy/CopyConfig.cpp | 4 + llvm/tools/llvm-objcopy/ObjcopyOpts.td | 9 + llvm/unittests/Analysis/CFGTest.cpp | 140 ++- llvm/utils/gn/secondary/lld/COFF/BUILD.gn | 1 + pstl/.clang-format | 3 + pstl/include/pstl/algorithm | 6 +- pstl/include/pstl/execution | 8 +- pstl/include/pstl/internal/algorithm_impl.h | 20 +- pstl/include/pstl/internal/glue_execution_defs.h | 6 +- pstl/include/pstl/internal/numeric_impl.h | 4 +- pstl/include/pstl/internal/parallel_backend.h | 2 +- pstl/include/pstl/internal/parallel_backend_tbb.h | 7 +- pstl/include/pstl/internal/pstl_config.h | 98 +- pstl/include/pstl/memory | 6 +- pstl/include/pstl/numeric | 6 +- 189 files changed, 6782 insertions(+), 2507 deletions(-) create mode 100644 clang/test/CodeGenCXX/pragma-followup_inner.cpp create mode 100644 clang/test/CodeGenCXX/pragma-followup_outer.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.cons [...] create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.help [...] create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.help [...] create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.invo [...] create mode 100644 lld/COFF/DebugTypes.cpp create mode 100644 lld/COFF/DebugTypes.h create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_ [...] create mode 100755 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100755 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100755 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] delete mode 100644 llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp delete mode 100644 llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir create mode 100644 llvm/test/CodeGen/AMDGPU/wwm-reserved.ll create mode 100644 llvm/test/CodeGen/RISCV/codemodel-lowering.ll create mode 100644 llvm/test/CodeGen/X86/fcmp-constant.ll delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt create mode 100644 llvm/test/ThinLTO/X86/builtin-nostrip.ll rename llvm/test/Transforms/Inline/AMDGPU/{inline-amdgpu-dx10.ll => inline-amdgpu- [...] create mode 100644 llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll create mode 100644 llvm/test/Transforms/InstSimplify/round-intrinsics.ll create mode 100644 llvm/test/Transforms/LoopPredication/invariant_load.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (40f0f9f -> b9c17ff)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 40f0f9f 2: good: llvm-linux: 4887 new b9c17ff 2: good: llvm-linux: 4887 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (40f0f9f) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-build_llvm/console.log | 11290 +++++++++++++++++---------------- 03-build_linux/console.log | 1821 +++--- console.log | 13239 +++++++++++++++++++-------------------- jenkins/manifest.sh | 8 +- 5 files changed, 13210 insertions(+), 13276 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig updated (79a3aaa7b82e -> 5e7a8ca31926)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from 79a3aaa7b82e Linux 5.1-rc3 adds 4fdcfab5b553 jffs2: fix use-after-free on symlink traversal adds 0cdc17ebd207 ubifs: fix use-after-free on symlink traversal adds 93b919da64c1 debugfs: fix use-after-free on symlink traversal adds db5481e705e2 Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux [...] adds b53119f13a04 pin iocb through aio. adds 833f4154ed56 aio: fold lookup_kiocb() into its sole caller adds a9339b785509 aio: keep io_event in aio_kiocb adds 2bb874c0d873 aio: store event at final iocb_put() adds af5c72b1fc7a Fix aio_poll() races adds 958c13ce141c make aio_read()/aio_write() return int adds 7425970347a2 aio: move dropping ->ki_eventfd into iocb_destroy() adds fa0ca2aee3be deal with get_reqs_available() in aio_get_req() itself adds 7316b49c2a11 aio: move sanity checks and request allocation to io_submit_one() adds 5e7a8ca31926 Merge branch 'work.aio' of git://git.kernel.org/pub/scm/li [...] No new revisions were added by this update. Summary of changes: fs/aio.c | 338 +++++++++++++++++++++++---------------------------- fs/debugfs/inode.c | 13 +- fs/jffs2/readinode.c | 5 - fs/jffs2/super.c | 5 +- fs/ubifs/super.c | 4 +- 5 files changed, 164 insertions(+), 201 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig updated (3771b76a540 -> ae3bd4cd077)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig in repository toolchain/ci/gcc. from 3771b76a540 Daily bump. adds ae3bd4cd077 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig updated (b26a7d3276 -> bd6e382a51)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig in repository toolchain/ci/binutils-gdb. from b26a7d3276 Automatic date update in version.in adds 263825a224 AArch64: Fix disassembler bug with out-of-order sections adds bd6e382a51 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- binutils/ChangeLog | 57 +++++ binutils/objdump.c | 1 + .../testsuite/binutils-all/aarch64/in-order-all.d | 38 ++++ binutils/testsuite/binutils-all/aarch64/in-order.d | 28 +++ .../binutils-all/aarch64/out-of-order-all.d | 38 ++++ .../testsuite/binutils-all/aarch64/out-of-order.T | 14 ++ .../testsuite/binutils-all/aarch64/out-of-order.d | 27 +++ .../testsuite/binutils-all/aarch64/out-of-order.s | 28 +++ binutils/testsuite/binutils-all/arm/in-order-all.d | 48 ++++ binutils/testsuite/binutils-all/arm/in-order.d | 28 +++ binutils/testsuite/binutils-all/arm/objdump.exp | 14 ++ .../testsuite/binutils-all/arm/out-of-order-all.d | 48 ++++ binutils/testsuite/binutils-all/arm/out-of-order.T | 14 ++ binutils/testsuite/binutils-all/arm/out-of-order.d | 27 +++ binutils/testsuite/binutils-all/arm/out-of-order.s | 29 +++ include/ChangeLog | 7 + include/dis-asm.h | 6 + ld/ChangeLog | 5 + ld/testsuite/ld-arm/jump-reloc-veneers-cond-long.d | 2 +- ld/testsuite/ld-arm/jump-reloc-veneers-long.d | 5 +- opcodes/ChangeLog | 33 +++ opcodes/aarch64-dis.c | 52 ++++- opcodes/arm-dis.c | 249 +++++++++------------ 24 files changed, 641 insertions(+), 159 deletions(-) create mode 100644 binutils/testsuite/binutils-all/aarch64/in-order-all.d create mode 100644 binutils/testsuite/binutils-all/aarch64/in-order.d create mode 100644 binutils/testsuite/binutils-all/aarch64/out-of-order-all.d create mode 100644 binutils/testsuite/binutils-all/aarch64/out-of-order.T create mode 100644 binutils/testsuite/binutils-all/aarch64/out-of-order.d create mode 100644 binutils/testsuite/binutils-all/aarch64/out-of-order.s create mode 100644 binutils/testsuite/binutils-all/arm/in-order-all.d create mode 100644 binutils/testsuite/binutils-all/arm/in-order.d create mode 100644 binutils/testsuite/binutils-all/arm/out-of-order-all.d create mode 100644 binutils/testsuite/binutils-all/arm/out-of-order.T create mode 100644 binutils/testsuite/binutils-all/arm/out-of-order.d create mode 100644 binutils/testsuite/binutils-all/arm/out-of-order.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig updated (9b39521 -> ac74dbc)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards 9b39521 0: good: binutils-gcc-linux: all new ac74dbc 0: good: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9b39521) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-prepare_abe/console.log | 128 +- 03-build_abe-binutils/console.log | 10334 +++++++-------- 04-build_abe-stage1/console.log | 12746 +++++++++--------- 05-build_linux/console.log | 1337 +- 06-boot_linux/console.log | 6 +- console.log | 24836 +++++++++++++++++++----------------- jenkins/manifest.sh | 16 +- 8 files changed, 25701 insertions(+), 23770 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (79a3aaa7b82e -> 5e7a8ca31926)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/linux. from 79a3aaa7b82e Linux 5.1-rc3 adds 4fdcfab5b553 jffs2: fix use-after-free on symlink traversal adds 0cdc17ebd207 ubifs: fix use-after-free on symlink traversal adds 93b919da64c1 debugfs: fix use-after-free on symlink traversal adds db5481e705e2 Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux [...] adds b53119f13a04 pin iocb through aio. adds 833f4154ed56 aio: fold lookup_kiocb() into its sole caller adds a9339b785509 aio: keep io_event in aio_kiocb adds 2bb874c0d873 aio: store event at final iocb_put() adds af5c72b1fc7a Fix aio_poll() races adds 958c13ce141c make aio_read()/aio_write() return int adds 7425970347a2 aio: move dropping ->ki_eventfd into iocb_destroy() adds fa0ca2aee3be deal with get_reqs_available() in aio_get_req() itself adds 7316b49c2a11 aio: move sanity checks and request allocation to io_submit_one() adds 5e7a8ca31926 Merge branch 'work.aio' of git://git.kernel.org/pub/scm/li [...] No new revisions were added by this update. Summary of changes: fs/aio.c | 338 +++++++++++++++++++++++---------------------------- fs/debugfs/inode.c | 13 +- fs/jffs2/readinode.c | 5 - fs/jffs2/super.c | 5 +- fs/ubifs/super.c | 4 +- 5 files changed, 164 insertions(+), 201 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig updated (2e1bf89e3a8 -> 9d1449246dd)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-defconfig in repository toolchain/ci/llvm-project. from 2e1bf89e3a8 [X86] Use ISD::INTRINSIC_VOID in getTgtMemIntrinsic for tru [...] adds 38a82413210 [Linux/x86] Fix writing of non-gpr registers on newer processors adds d83fb24533e [ELF] Rename SyntheticSection::empty to more appropriate is [...] adds 3091884e25d [RISCV] Add seto pattern expansion adds e8c3136994b [X86][SSE] Add fcmp constant folding tests adds 7af32444b9b [X86] Fix a test from r357317 adds d9f6ee1c3cc [X86MacroFusion][NFC] Add more tests. adds 97d1bc44544 [InstCombine] eliminate commuted select-shuffles + binop (PR41304) adds bf55c4e3e39 [LLD][COFF] Early dependency detection adds 7e062c9b1f9 [X86] Make post-ra scheduling macrofusion-aware. adds d66a47f90a7 [InstCombine] Handle vector gep with scalar argument in eva [...] adds 0276b943566 InstSimplify: Add baseline test for upcoming change adds 3e527cd823a Revert "[InstCombine] Handle vector gep with scalar argumen [...] adds ebf90db0848 X86: Fix override warning adds 150a7ec2dc0 [InstCombine] Handle vector gep with scalar argument in eva [...] adds e106f25f056 [OPENMP] Check that allocated variables are used in private [...] adds 30c2f20e558 Fix builder. adds efe376add6a [AArch64] Add v8.5-a Memory Tagging GMID_EL1 register adds da20f5ca745 [RISCV] Generate address sequences suitable for mcmodel=medium adds 60768cd8967 [ASTImporter] Make ODR error handling configurable adds 9142b8ef1b9 [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions adds 44668ae7c7d [RISCV] Attach VK_RISCV_CALL to symbols upon creation adds 3d233d5d4d8 [AArch64] Add v8.5-a Memory Tagging STZGM instruction adds 22990ba11c2 gn build: Merge r357383 adds d8519f4a7db [lldb] [Process/elf-core] Support aarch64 NetBSD core dumps adds 0a30f33ce21 [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. adds 95c585e258f [pstl] Indent preprocessor directives as part of the clang- [...] adds 410f32ce7c6 [ASTImporter] Convert ODR diagnostics inside ASTImporter im [...] adds 9ef7708bbbf [Tests] Add tests for a possible loop predication transform [...] adds 7eee62b5d4e [Tests] Autogen all the LoopPredication tests adds dae5ff2b7b8 Attempt to fix failing buildbot (ppc64le) adds d109e2a7c3b [LoopPred] Delete the old condition expressions if unused adds 6c21ccd245b [NVPTX] Fix the codegen for llvm.round. adds 05e3e554b47 [LoopPred] Be uniform about proving generated conditions adds 2a67c910764 Commit accidentally omitted test case. adds efa6d803c62 Fix PR41130 - 'operator/ of std::chrono::duration and custo [...] adds 2b0c7abba35 [libc++] Declare std::tuple_element as struct instead of class adds 84c8baeef71 [OPENMP]Allocate clause allocator in target region. adds ecad92b0680 Fix PR#41323 'Race condition in steady_clock::now for _LIBC [...] adds f6c04ad4860 [SLP] getGatherCost and isFullyVectorizableTinyTree are con [...] adds 58e7642669b [CodeGen] Generate follow-up metadata for loops with more t [...] adds b06935fa8c1 [SLP] getVectorElementSize and isTreeTinyAndNotFullyVectori [...] adds a9e847238e1 ELF: Perform per-section .ARM.exidx processing during combi [...] adds f2baddb0fc4 [llvm-objcopy] Add --keep-symbols option adds 4307172b841 [X86] Classify the AVX512 rounding control operand as X86:: [...] adds 62bcf736834 [Process] Fix WriteMemory return value adds 3c023420d1d [NFC][LLD] Specify namespaces explicity to fix build failur [...] adds a735985abe8 [pstl] Mangle the parallel_strict_scan backend function adds beb6efb42ec [libcxx] Make sure reference_wrapper works with incomplete types adds c791a20b429 [API] Add SBReproducer to LLDB.h adds 66d7eb97045 Not all blocks are reachable from entry. Don't assume they are. adds 4665aca8ca7 [lldb-vscode] Add logic to handle EOF when reading from lld [...] adds 1e1e212d274 [NFC] Remove dead parameter "FreeInLoop", fix some typos an [...] adds 533fe617ac6 [Process] Use early returns in Process::WriteMemory (NFC) adds 1cd4216c75a Fix clangd unittest _WIN32 ifdef adds dd245c4f8fe [CMake] Only the Python scirpt interpreter should link agai [...] adds e44c20a68d2 [AArch64][GlobalISe] Select STRQui for stores into v264s in [...] adds f608678f1f3 [LoopPred] Rename a variable to simply a future patch [NFC] adds 73af6ef2e75 [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz. adds 3813fe0bda8 [ARM] Optimize expressions like "return x != 0;" for Thumb1. adds 294e07cf034 AMDGPU: Fix test filename adds 9bef688bc29 [AMDGPU] Add more test cases of D59608. adds fa0a2c529bc InstSimplify: Add missing case from r357386 adds c5903c935c2 [X86] Use unsigned type for opcodes throughout X86FixupLEAs. adds c1330159754 [X86] Autogenerate complete checks. NFC adds 536383a3548 [X86] Add test cases to fixup-lea.ll for optsize and no siz [...] adds c0ebfbe3f32 Add an optional list of blocks to avoid when looking for a [...] adds adb3ece2164 [LoopPredication] Simplify widenable condition handling [NFC] adds 60a8816c2fc [compiler-rt][test] Make instrprof-set-dir-mode test tolera [...] new 9d1449246dd ar_to_bc.sh: replace readlink -f with custom relative path [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../unittests/clangd/JSONTransportTests.cpp | 4 +- clang/include/clang/AST/ASTStructuralEquivalence.h | 4 + clang/include/clang/Basic/DiagnosticASTKinds.td | 72 +- clang/include/clang/Basic/DiagnosticGroups.td | 1 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 5 + clang/lib/AST/ASTImporter.cpp | 28 +- clang/lib/AST/ASTStructuralEquivalence.cpp | 161 ++- clang/lib/CodeGen/CGLoopInfo.cpp | 540 ++++++++-- clang/lib/CodeGen/CGLoopInfo.h | 84 +- clang/lib/Sema/SemaOpenMP.cpp | 366 ++++--- clang/test/CodeGenCXX/pragma-followup_inner.cpp | 42 + clang/test/CodeGenCXX/pragma-followup_outer.cpp | 41 + .../pragma-loop-safety-imperfectly_nested.cpp | 4 +- .../test/CodeGenCXX/pragma-loop-safety-nested.cpp | 4 +- clang/test/CodeGenCXX/pragma-loop-safety-outer.cpp | 2 +- clang/test/CodeGenCXX/pragma-loop-safety.cpp | 10 +- clang/test/CodeGenCXX/pragma-loop.cpp | 59 +- clang/test/CodeGenCXX/pragma-unroll-and-jam.cpp | 2 +- clang/test/OpenMP/allocate_messages.cpp | 2 + clang/test/OpenMP/nvptx_allocate_messages.cpp | 6 + clang/test/OpenMP/simd_metadata.c | 6 +- .../symbolizer/scripts/ar_to_bc.sh | 4 +- compiler-rt/test/profile/instrprof-set-dir-mode.c | 6 +- libcxx/include/__tuple | 17 +- libcxx/include/array | 5 +- libcxx/include/chrono | 38 +- libcxx/include/span | 3 +- libcxx/include/tuple | 4 +- libcxx/include/utility | 10 +- libcxx/src/chrono.cpp | 21 +- .../refwrap/refwrap.const/ctor.incomplete.pass.cpp | 41 + .../refwrap.helpers/cref.incomplete.pass.cpp | 42 + .../refwrap.helpers/ref.incomplete.pass.cpp | 42 + .../refwrap.invoke/invoke.incomplete.fail.cpp | 37 + libcxx/test/std/utilities/time/rep.h | 36 + .../time.duration.arithmetic/op_divide=.pass.cpp | 10 + .../op_mod=duration.pass.cpp | 10 + .../time.duration.arithmetic/op_mod=rep.pass.cpp | 15 + .../time.duration.arithmetic/op_times=.pass.cpp | 10 + .../time.duration.nonmember/op_divide_rep.pass.cpp | 16 +- .../time.duration.nonmember/op_mod_rep.pass.cpp | 16 +- .../time.duration.nonmember/op_times_rep.pass.cpp | 16 + .../tuple.helper/tuple.include.array.pass.cpp | 3 +- .../tuple.helper/tuple_element.fail.cpp | 3 +- .../tuple.helper/tuple_element.pass.cpp | 3 +- .../tuple_size_structured_bindings.pass.cpp | 3 +- libcxx/www/cxx2a_status.html | 2 +- lld/COFF/CMakeLists.txt | 1 + lld/COFF/DebugTypes.cpp | 88 ++ lld/COFF/DebugTypes.h | 51 + lld/COFF/InputFiles.cpp | 56 ++ lld/COFF/InputFiles.h | 8 + lld/COFF/PDB.cpp | 97 +- lld/ELF/SyntheticSections.cpp | 119 ++- lld/ELF/SyntheticSections.h | 42 +- lld/ELF/Writer.cpp | 31 +- lldb/include/lldb/API/LLDB.h | 1 + .../gdb_remote_client/TestWriteMemory.py | 29 + .../postmortem/netbsd-core/1lwp_SIGSEGV.aarch64 | Bin 0 -> 9088 bytes .../netbsd-core/1lwp_SIGSEGV.aarch64.core | Bin 0 -> 225728 bytes .../netbsd-core/2lwp_process_SIGSEGV.aarch64 | Bin 0 -> 13192 bytes .../netbsd-core/2lwp_process_SIGSEGV.aarch64.core | Bin 0 -> 246936 bytes .../postmortem/netbsd-core/2lwp_t2_SIGSEGV.aarch64 | Bin 0 -> 11848 bytes .../netbsd-core/2lwp_t2_SIGSEGV.aarch64.core | Bin 0 -> 251904 bytes .../postmortem/netbsd-core/TestNetBSDCore.py | 15 + .../lldbsuite/test/tools/lldb-vscode/vscode.py | 76 +- .../Linux/NativeRegisterContextLinux_x86_64.cpp | 119 ++- .../Linux/NativeRegisterContextLinux_x86_64.h | 3 +- .../Plugins/Process/elf-core/ProcessElfCore.cpp | 26 + .../Plugins/Process/elf-core/RegisterUtilities.h | 5 + .../Plugins/Process/elf-core/ThreadElfCore.cpp | 3 + lldb/source/Target/Process.cpp | 105 +- lldb/unittests/Interpreter/CMakeLists.txt | 5 - .../ScriptInterpreter/Python/CMakeLists.txt | 4 +- llvm/include/llvm/Analysis/CFG.h | 25 +- llvm/include/llvm/CodeGen/MachineBasicBlock.h | 11 + llvm/lib/Analysis/BasicAliasAnalysis.cpp | 2 +- llvm/lib/Analysis/CFG.cpp | 76 +- llvm/lib/Analysis/CaptureTracking.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 5 +- llvm/lib/CodeGen/DwarfEHPrepare.cpp | 2 +- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 13 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 3 +- llvm/lib/Target/AArch64/AArch64SystemOperands.td | 1 + .../Target/AArch64/AsmParser/AArch64AsmParser.cpp | 9 - .../AArch64/Disassembler/AArch64Disassembler.cpp | 27 - llvm/lib/Target/AMDGPU/AMDGPU.h | 6 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 12 +- llvm/lib/Target/AMDGPU/CMakeLists.txt | 2 +- llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp | 417 -------- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 17 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 + llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 5 + llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 221 +++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 + llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 21 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 24 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 104 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 4 + llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 9 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 34 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 6 +- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 45 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 100 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 + llvm/lib/Target/RISCV/RISCVInstrInfo.td | 16 +- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 4 + llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 4 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 9 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 2 + llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 5 + .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 +- llvm/lib/Target/X86/X86FixupLEAs.cpp | 25 +- llvm/lib/Target/X86/X86InstrInfo.td | 3 +- llvm/lib/Target/X86/X86Subtarget.cpp | 6 + llvm/lib/Target/X86/X86Subtarget.h | 3 + .../InstCombine/InstCombineVectorOps.cpp | 9 +- .../InstCombine/InstructionCombining.cpp | 24 + llvm/lib/Transforms/Scalar/LICM.cpp | 27 +- llvm/lib/Transforms/Scalar/LoopPredication.cpp | 43 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 22 +- .../GlobalISel/legalize-load-store-fewerElts.mir | 6 +- .../CodeGen/AArch64/GlobalISel/select-store.mir | 22 + .../CodeGen/AMDGPU/atomic_optimizations_buffer.ll | 5 +- .../AMDGPU/atomic_optimizations_global_pointer.ll | 8 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 4 +- .../AMDGPU/atomic_optimizations_raw_buffer.ll | 4 +- .../AMDGPU/atomic_optimizations_struct_buffer.ll | 4 +- llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll | 32 + llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir | 185 ---- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 3 - llvm/test/CodeGen/AMDGPU/uaddo.ll | 27 + llvm/test/CodeGen/AMDGPU/usubo.ll | 51 + llvm/test/CodeGen/AMDGPU/wqm.mir | 2 +- llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 188 ++++ llvm/test/CodeGen/ARM/fold-stack-adjust.ll | 48 +- llvm/test/CodeGen/ARM/select-imm.ll | 48 +- llvm/test/CodeGen/NVPTX/f16-instructions.ll | 8 +- llvm/test/CodeGen/NVPTX/f16x2-instructions.ll | 13 +- llvm/test/CodeGen/NVPTX/math-intrins.ll | 12 +- llvm/test/CodeGen/RISCV/codemodel-lowering.ll | 80 ++ llvm/test/CodeGen/RISCV/double-br-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/double-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/double-select-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/float-br-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/float-fcmp.ll | 8 - llvm/test/CodeGen/RISCV/float-select-fcmp.ll | 8 - .../Thumb/umulo-128-legalisation-lowering.ll | 235 ++--- .../Thumb/umulo-32-legalisation-lowering.ll | 15 +- llvm/test/CodeGen/X86/fcmp-constant.ll | 278 ++++++ llvm/test/CodeGen/X86/fixup-lea.ll | 190 +++- llvm/test/CodeGen/X86/testb-je-fusion.ll | 303 ++++-- llvm/test/CodeGen/X86/win64-nosse-error.ll | 2 +- llvm/test/MC/AArch64/armv8.5a-mte-error.s | 106 +- llvm/test/MC/AArch64/armv8.5a-mte.s | 42 +- .../AArch64/armv8.5a-mte-unpredictable.txt | 7 - llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt | 31 +- llvm/test/ThinLTO/X86/builtin-nostrip.ll | 59 ++ ...-amdgpu-dx10.ll => inline-amdgpu-dx10-clamp.ll} | 0 .../Transforms/InstCombine/vec-binop-select.ll | 71 +- .../Transforms/InstCombine/vec_gep_scalar_arg.ll | 16 + .../Transforms/InstSimplify/round-intrinsics.ll | 143 +++ llvm/test/Transforms/LoopPredication/basic.ll | 1035 +++++++++++++++----- .../basic_widenable_branch_guards.ll | 490 ++++++++- .../Transforms/LoopPredication/invariant_load.ll | 246 +++++ llvm/test/Transforms/LoopPredication/nested.ll | 223 ++++- .../Transforms/LoopPredication/profitability.ll | 89 +- llvm/test/Transforms/LoopPredication/reverse.ll | 229 ++++- llvm/test/Transforms/LoopPredication/visited.ll | 42 +- llvm/test/Transforms/LoopPredication/widened.ll | 142 ++- llvm/test/tools/llvm-objcopy/ELF/keep-symbol.test | 7 + llvm/tools/llvm-objcopy/CopyConfig.cpp | 4 + llvm/tools/llvm-objcopy/ObjcopyOpts.td | 9 + llvm/unittests/Analysis/CFGTest.cpp | 140 ++- llvm/utils/gn/secondary/lld/COFF/BUILD.gn | 1 + pstl/.clang-format | 3 + pstl/include/pstl/algorithm | 6 +- pstl/include/pstl/execution | 8 +- pstl/include/pstl/internal/algorithm_impl.h | 20 +- pstl/include/pstl/internal/glue_execution_defs.h | 6 +- pstl/include/pstl/internal/numeric_impl.h | 4 +- pstl/include/pstl/internal/parallel_backend.h | 2 +- pstl/include/pstl/internal/parallel_backend_tbb.h | 7 +- pstl/include/pstl/internal/pstl_config.h | 98 +- pstl/include/pstl/memory | 6 +- pstl/include/pstl/numeric | 6 +- 189 files changed, 6782 insertions(+), 2507 deletions(-) create mode 100644 clang/test/CodeGenCXX/pragma-followup_inner.cpp create mode 100644 clang/test/CodeGenCXX/pragma-followup_outer.cpp create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.cons [...] create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.help [...] create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.help [...] create mode 100644 libcxx/test/std/utilities/function.objects/refwrap/refwrap.invo [...] create mode 100644 lld/COFF/DebugTypes.cpp create mode 100644 lld/COFF/DebugTypes.h create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_ [...] create mode 100755 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100755 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100755 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] create mode 100644 lldb/packages/Python/lldbsuite/test/functionalities/postmortem/ [...] delete mode 100644 llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp create mode 100644 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp delete mode 100644 llvm/test/CodeGen/AMDGPU/fix-wwm-liveness.mir create mode 100644 llvm/test/CodeGen/AMDGPU/wwm-reserved.ll create mode 100644 llvm/test/CodeGen/RISCV/codemodel-lowering.ll create mode 100644 llvm/test/CodeGen/X86/fcmp-constant.ll delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt create mode 100644 llvm/test/ThinLTO/X86/builtin-nostrip.ll rename llvm/test/Transforms/Inline/AMDGPU/{inline-amdgpu-dx10.ll => inline-amdgpu- [...] create mode 100644 llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll create mode 100644 llvm/test/Transforms/InstSimplify/round-intrinsics.ll create mode 100644 llvm/test/Transforms/LoopPredication/invariant_load.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits April 2019