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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig
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discards 2956c47 0: good: llvm-linux: 16693
new 53666d2 0: good: llvm-linux: 16693
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allmodconfig
in repository toolchain/ci/binutils-gdb.
from 1c6aafe894 PR24411, Division is not accepted in MEMORY length expression
adds 403b0b61f6 gas: use literals/const16 for xtensa loop relaxation
adds e691a46f7d Automatic date update in version.in
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bfd/version.h | 2 +-
gas/ChangeLog | 10 ++++
gas/config/tc-xtensa.c | 120 ----------------------------------------------
gas/config/xtensa-relax.c | 77 ++++++++++++++++++++---------
4 files changed, 66 insertions(+), 143 deletions(-)
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discards c0ca9dd 0: good: binutils-gcc-linux: all
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unknown user pushed a change to branch master
in repository llvm.
from 4fbffbd5f67 [SLP][X86] Regenerate operandorder tests with arguments on [...]
new 80733cc0e97 [ARM GlobalISel] Support DBG_VALUE
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lib/Target/ARM/ARMRegisterBankInfo.cpp | 7 +++
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 56 ++++++++++++++++++++++
test/CodeGen/ARM/GlobalISel/select-dbg.mir | 57 +++++++++++++++++++++++
3 files changed, 120 insertions(+)
create mode 100644 test/CodeGen/ARM/GlobalISel/select-dbg.mir
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allnoconfig
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discards c387f69 0: good: llvm-linux: all
new f7c6197 0: good: llvm-linux: all
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unknown user pushed a change to branch master
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from 9fcfd99f4 Add dropped ManualDWARFIndex assert()
new 0b310de7f modify-python-lldb.py: (Re)move __len__ and __iter__ support
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.../module_section/TestModuleAndSection.py | 1 +
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scripts/interface/SBModule.i | 23 +++++
scripts/lldb.swig | 6 --
4 files changed, 27 insertions(+), 106 deletions(-)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig
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discards f1e3216 0: good: llvm-linux: 18109
new bec5ac0 0: good: llvm-linux: 18109
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