Tcwg-commits December 2019

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (e9775bb5d81 -> bc5b7217dce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/llvm-project. from e9775bb5d81 Hexagon: Fix missing tablegen mode comment adds 5ce2ca524e9 AMDGPU/GlobalISel: Use SReg_32 for readfirstlane constraining adds 33a1b3d8fce [sanitizer] Link Sanitizer-x86_64-Test-Nolibc with -static adds dce7a362bed [ELF] Improve the condition to create .interp adds a33cab0f06e AMDGPU: Adjust test so it will work with GlobalISel adds c51b45e32ef DebugInfo: Fix rangesBaseAddress DICompileUnit bitcode seri [...] adds 22f34c7f34a lld: Remove explicit copy ops from AssociatedIterator, rely [...] adds f7910496c83 [Intrinsic] Delete tablegen rules of llvm.{sig,}{setjmp,longjmp} adds 044cc919f4b Delete setjmp_undefined_for_msvc workaround after llvm.setj [...] adds 0bc7665d988 [ADT] Fix FoldingSet documentation typos adds f83a8efe879 [mlir] Merge the successor operand count into BlockOperand. adds a3f89648132 [TargetLowering] Update comment to reference the correct co [...] adds d1b51c5de7a [PowerPC] Modify the hasSideEffects of some VSX instruction [...] adds 8612e92ed59 [lldb][NFC] Remove GetASTContext call in ClangDeclVendor adds 128f39da932 Fix crash in getFullyQualifiedName for inline namespace adds 34769e07835 SimplifyDemandedBits - Remove duplicate getOperand() call. NFC. adds a9ad65a2b34 [PowerPC] Change default for unaligned FP access for older [...] adds b6cf400aaea Fix bots after a9ad65a2b34f adds 3b6aec79b2c [X86] Add test cases for v4i64->v4f32 and v8i64->v8f32 stri [...] new e7853a5ce21 [CMake] Fix lld detection after D69685 new 7ca86ee6494 [COFF] Make the autogenerated .weak.<name>.default symbols static new 0acfc493171 Allow redeclaration of __declspec(uuid) new 36fb199ecaa [lldb][NFC] Remove GetASTContext call in ClangPersistentVariables new bc5b7217dce Revert "[COFF] Make the autogenerated .weak.<name>.default [...] The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/AST/QualTypeNames.cpp | 2 +- clang/lib/Sema/SemaDecl.cpp | 4 + clang/lib/Sema/SemaDeclAttr.cpp | 8 +- clang/test/SemaCXX/ms-uuid.cpp | 6 + clang/unittests/Tooling/QualTypeNamesTest.cpp | 11 + compiler-rt/cmake/Modules/AddCompilerRT.cmake | 2 +- .../lib/sanitizer_common/tests/CMakeLists.txt | 2 +- lld/COFF/Chunks.h | 5 - lld/ELF/Writer.cpp | 2 +- lld/test/ELF/dynamic-linker.s | 12 +- lld/test/ELF/ppc64-func-entry-points.s | 4 +- .../Clang/ASTResultSynthesizer.cpp | 13 +- .../ExpressionParser/Clang/ClangDeclVendor.cpp | 15 +- .../ExpressionParser/Clang/ClangDeclVendor.h | 8 +- .../Clang/ClangModulesDeclVendor.cpp | 6 +- .../Clang/ClangPersistentVariables.cpp | 38 ++-- .../Clang/ClangPersistentVariables.h | 12 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp | 11 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.h | 2 +- llvm/include/llvm/ADT/FoldingSet.h | 10 +- llvm/include/llvm/IR/Intrinsics.td | 6 - llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 + llvm/lib/CodeGen/IntrinsicLowering.cpp | 8 - .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 18 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/PowerPC/PPC.td | 6 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 + llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 +- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 1 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 + llvm/test/Assembler/dicompileunit.ll | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 4 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 2 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 2 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 2 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 8 +- llvm/test/CodeGen/AMDGPU/read_register.ll | 16 +- llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll | 3 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 60 ++--- llvm/test/CodeGen/PowerPC/unaligned-floats.ll | 43 ++++ llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 242 +++++++++++++++++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll | 232 ++++++++++++++++++++ llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 28 --- mlir/include/mlir/IR/BlockSupport.h | 2 - mlir/include/mlir/IR/Operation.h | 16 +- mlir/include/mlir/IR/UseDefLists.h | 59 +++-- mlir/lib/IR/Operation.cpp | 67 ++---- mlir/lib/IR/Value.cpp | 33 +++ 55 files changed, 798 insertions(+), 277 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/unaligned-floats.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (45b390436 -> dce989fde)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 45b390436 0: update: llvm-linux: boot new dce989fde 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (45b390436) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-build_llvm/console.log | 12486 ++++++++++++++++---------------- 03-build_linux/console.log | 1760 ++--- 04-boot_linux/console.log | 470 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 29 - console.log | 14848 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 14852 insertions(+), 14881 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug updated (f08a5e4b60a -> ff8cfa9d55b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug in repository toolchain/ci/gcc. from f08a5e4b60a PR c++/92438 * parser.c (cp_parser_constructor_declarator [...] adds 01fefb8e2a9 Daily bump. adds 9b5e7eea888 Add missing target check for fully-masked fold-left reductions adds 09df4e21214 [AArch64] Fix typo in V_INT_CONTAINER adds 616fb840990 Daily bump. adds ff8cfa9d55b PR bootstrap/93074 * plugin/cuda/cuda.h (cuDeviceGetName, [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 10 ++++++++++ gcc/DATESTAMP | 2 +- gcc/config/aarch64/iterators.md | 2 +- gcc/testsuite/ChangeLog | 8 ++++++++ gcc/testsuite/gcc.target/aarch64/sve/mixed_size_10.c | 13 +++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/mixed_size_11.c | 13 +++++++++++++ gcc/tree-vect-loop.c | 12 ++++++++++++ libgomp/ChangeLog | 6 ++++++ libgomp/plugin/cuda/cuda.h | 6 ++++++ 9 files changed, 70 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/mixed_size_10.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/mixed_size_11.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug updated (50aabd639 -> f890a6758)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug in repository toolchain/ci/base-artifacts. discards 50aabd639 0: update: gcc-f08a5e4b60a4383a7b224eb097d5c837a368d8fa: 1 new f890a6758 0: update: gcc-ff8cfa9d55b6078c5054b85ee61728ea4bc253cf: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (50aabd639) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-boots [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 180 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-bootstrap_debug/console.log | 92194 ++++++++++++++-------------- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 92814 ++++++++++++++--------------- jenkins/manifest.sh | 8 +- 7 files changed, 92809 insertions(+), 92829 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (09df4e21214 -> ff8cfa9d55b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/gcc. from 09df4e21214 [AArch64] Fix typo in V_INT_CONTAINER adds 616fb840990 Daily bump. adds ff8cfa9d55b PR bootstrap/93074 * plugin/cuda/cuda.h (cuDeviceGetName, [...] No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- libgomp/ChangeLog | 6 ++++++ libgomp/plugin/cuda/cuda.h | 6 ++++++ 3 files changed, 13 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (ace206a5a5 -> b28a729db1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/binutils-gdb. from ace206a5a5 Remove dead code from TUI adds 1ddaf334cf Automatic date update in version.in adds b28a729db1 [PATCH] Adjust test gdb.ada/ptype_tagged_param.exp for when [...] No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gdb/testsuite/ChangeLog | 8 +++++++ gdb/testsuite/gdb.ada/ptype_tagged_param.exp | 25 +++++++++++++++---- gdb/testsuite/lib/ada.exp | 36 ++++++++++++++++++++++++++++ gdb/testsuite/lib/gnat_debug_info_test.adb | 6 +++++ 5 files changed, 72 insertions(+), 5 deletions(-) create mode 100644 gdb/testsuite/lib/gnat_debug_info_test.adb -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (fba8aee7b -> 8d18e78f7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards fba8aee7b 0: update: binutils-gcc-linux: boot new 8d18e78f7 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (fba8aee7b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 82 +- 03-build_abe-binutils/console.log | 11072 ++++++------ 04-build_abe-stage1/console.log | 19926 +++++++++++---------- 05-build_linux/console.log | 3138 ++-- 06-boot_linux/console.log | 470 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 34847 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 34831 insertions(+), 34848 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (c3d3569d4ca -> 3b6aec79b2c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project. from c3d3569d4ca [mlir] Convert std.and/std.or ops to spv.LogicalAnd/spv.LogicalOr adds d8018233d1e Revert "CWG2352: Allow qualification conversions during ref [...] adds 596012b2567 [mlir][spirv] Update docs regarding how to define new ops a [...] adds e8c5600de8b [PowerPC][LoopVectorize]Add floating point reg usage test adds 1d891a32cf4 Support powerpc and sparc when building without init_array. adds c3dbd782f1e Revert "[ELF] Improve the condition to create .interp" adds b30d87a90ba [mlir][spirv] Add basic definitions for supporting availability adds 9acd9544db9 AMDGPU: Use Register adds e29ae3799ba TII: Fix using Register for a subregister index argument adds e9775bb5d81 Hexagon: Fix missing tablegen mode comment adds 5ce2ca524e9 AMDGPU/GlobalISel: Use SReg_32 for readfirstlane constraining adds 33a1b3d8fce [sanitizer] Link Sanitizer-x86_64-Test-Nolibc with -static adds dce7a362bed [ELF] Improve the condition to create .interp adds a33cab0f06e AMDGPU: Adjust test so it will work with GlobalISel adds c51b45e32ef DebugInfo: Fix rangesBaseAddress DICompileUnit bitcode seri [...] adds 22f34c7f34a lld: Remove explicit copy ops from AssociatedIterator, rely [...] adds f7910496c83 [Intrinsic] Delete tablegen rules of llvm.{sig,}{setjmp,longjmp} adds 044cc919f4b Delete setjmp_undefined_for_msvc workaround after llvm.setj [...] adds 0bc7665d988 [ADT] Fix FoldingSet documentation typos adds f83a8efe879 [mlir] Merge the successor operand count into BlockOperand. adds a3f89648132 [TargetLowering] Update comment to reference the correct co [...] adds d1b51c5de7a [PowerPC] Modify the hasSideEffects of some VSX instruction [...] adds 8612e92ed59 [lldb][NFC] Remove GetASTContext call in ClangDeclVendor adds 128f39da932 Fix crash in getFullyQualifiedName for inline namespace adds 34769e07835 SimplifyDemandedBits - Remove duplicate getOperand() call. NFC. adds a9ad65a2b34 [PowerPC] Change default for unaligned FP access for older [...] adds b6cf400aaea Fix bots after a9ad65a2b34f adds 3b6aec79b2c [X86] Add test cases for v4i64->v4f32 and v8i64->v8f32 stri [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Basic/DiagnosticSemaKinds.td | 3 +- clang/lib/AST/QualTypeNames.cpp | 2 +- clang/lib/Sema/SemaExprCXX.cpp | 2 - clang/lib/Sema/SemaInit.cpp | 8 +- clang/lib/Sema/SemaOverload.cpp | 290 +++++++++--------- clang/test/CXX/drs/dr23xx.cpp | 33 +-- clang/test/CXX/drs/dr4xx.cpp | 11 +- clang/test/SemaObjCXX/arc-overloading.mm | 30 -- .../SemaOpenCL/address-spaces-conversions-cl2.0.cl | 18 +- clang/unittests/Tooling/QualTypeNamesTest.cpp | 11 + clang/www/cxx_dr_status.html | 4 +- clang/www/make_cxx_dr_status | 4 +- compiler-rt/lib/crt/crtbegin.c | 32 +- .../lib/sanitizer_common/tests/CMakeLists.txt | 2 +- lld/COFF/Chunks.h | 5 - .../ExpressionParser/Clang/ClangDeclVendor.cpp | 15 +- .../ExpressionParser/Clang/ClangDeclVendor.h | 8 +- .../Clang/ClangModulesDeclVendor.cpp | 6 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp | 11 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.h | 2 +- llvm/include/llvm/ADT/FoldingSet.h | 10 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +- llvm/include/llvm/IR/Intrinsics.td | 6 - llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 + llvm/lib/CodeGen/IntrinsicLowering.cpp | 8 - .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 18 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 18 +- llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 2 +- llvm/lib/Target/PowerPC/PPC.td | 6 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 + llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 +- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 1 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 + llvm/test/Assembler/dicompileunit.ll | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 4 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 2 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 2 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 2 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 8 +- llvm/test/CodeGen/AMDGPU/read_register.ll | 16 +- llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll | 3 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 60 ++-- llvm/test/CodeGen/PowerPC/unaligned-floats.ll | 43 +++ llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 242 +++++++++++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll | 232 +++++++++++++++ llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- .../Transforms/LoopVectorize/PowerPC/reg-usage.ll | 91 ++++++ llvm/utils/TableGen/IntrinsicEmitter.cpp | 28 -- mlir/docs/Dialects/SPIR-V.md | 50 +++- mlir/include/mlir/Dialect/SPIRV/CMakeLists.txt | 16 +- mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td | 7 + .../mlir/Dialect/SPIRV/SPIRVAvailability.td | 86 ++++++ mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 154 +++++++++- .../mlir/Dialect/SPIRV/SPIRVNonUniformOps.td | 7 + mlir/include/mlir/Dialect/SPIRV/SPIRVOps.h | 23 +- mlir/include/mlir/IR/BlockSupport.h | 2 - mlir/include/mlir/IR/Operation.h | 16 +- mlir/include/mlir/IR/UseDefLists.h | 59 +++- mlir/lib/Dialect/SPIRV/CMakeLists.txt | 1 + mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 8 + mlir/lib/IR/Operation.cpp | 67 +---- mlir/lib/IR/Value.cpp | 33 +++ mlir/test/CMakeLists.txt | 1 + mlir/test/Dialect/CMakeLists.txt | 1 + mlir/test/Dialect/SPIRV/CMakeLists.txt | 14 + mlir/test/Dialect/SPIRV/TestAvailability.cpp | 73 +++++ mlir/test/Dialect/SPIRV/availability.mlir | 31 ++ mlir/tools/mlir-opt/CMakeLists.txt | 1 + mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 328 ++++++++++++++++++++- 78 files changed, 1796 insertions(+), 531 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/unaligned-floats.ll create mode 100644 mlir/include/mlir/Dialect/SPIRV/SPIRVAvailability.td create mode 100644 mlir/test/Dialect/CMakeLists.txt create mode 100644 mlir/test/Dialect/SPIRV/CMakeLists.txt create mode 100644 mlir/test/Dialect/SPIRV/TestAvailability.cpp create mode 100644 mlir/test/Dialect/SPIRV/availability.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (bcfbbdb93 -> eca2539cb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards bcfbbdb93 0: update: llvm-linux: all new eca2539cb 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (bcfbbdb93) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 70 +- 02-build_llvm/console.log | 12626 +++++++++++------------ 03-build_linux/console.log | 8178 +++++++-------- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 29 + console.log | 20915 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 20948 insertions(+), 20890 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig updated (1d891a32cf4 -> 3b6aec79b2c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig in repository toolchain/ci/llvm-project. from 1d891a32cf4 Support powerpc and sparc when building without init_array. adds c3dbd782f1e Revert "[ELF] Improve the condition to create .interp" adds b30d87a90ba [mlir][spirv] Add basic definitions for supporting availability adds 9acd9544db9 AMDGPU: Use Register adds e29ae3799ba TII: Fix using Register for a subregister index argument adds e9775bb5d81 Hexagon: Fix missing tablegen mode comment adds 5ce2ca524e9 AMDGPU/GlobalISel: Use SReg_32 for readfirstlane constraining adds 33a1b3d8fce [sanitizer] Link Sanitizer-x86_64-Test-Nolibc with -static adds dce7a362bed [ELF] Improve the condition to create .interp adds a33cab0f06e AMDGPU: Adjust test so it will work with GlobalISel adds c51b45e32ef DebugInfo: Fix rangesBaseAddress DICompileUnit bitcode seri [...] adds 22f34c7f34a lld: Remove explicit copy ops from AssociatedIterator, rely [...] adds f7910496c83 [Intrinsic] Delete tablegen rules of llvm.{sig,}{setjmp,longjmp} adds 044cc919f4b Delete setjmp_undefined_for_msvc workaround after llvm.setj [...] adds 0bc7665d988 [ADT] Fix FoldingSet documentation typos adds f83a8efe879 [mlir] Merge the successor operand count into BlockOperand. adds a3f89648132 [TargetLowering] Update comment to reference the correct co [...] adds d1b51c5de7a [PowerPC] Modify the hasSideEffects of some VSX instruction [...] adds 8612e92ed59 [lldb][NFC] Remove GetASTContext call in ClangDeclVendor adds 128f39da932 Fix crash in getFullyQualifiedName for inline namespace adds 34769e07835 SimplifyDemandedBits - Remove duplicate getOperand() call. NFC. adds a9ad65a2b34 [PowerPC] Change default for unaligned FP access for older [...] new b6cf400aaea Fix bots after a9ad65a2b34f new 3b6aec79b2c [X86] Add test cases for v4i64->v4f32 and v8i64->v8f32 stri [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/AST/QualTypeNames.cpp | 2 +- clang/unittests/Tooling/QualTypeNamesTest.cpp | 11 + .../lib/sanitizer_common/tests/CMakeLists.txt | 2 +- lld/COFF/Chunks.h | 5 - .../ExpressionParser/Clang/ClangDeclVendor.cpp | 15 +- .../ExpressionParser/Clang/ClangDeclVendor.h | 8 +- .../Clang/ClangModulesDeclVendor.cpp | 6 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp | 11 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.h | 2 +- llvm/include/llvm/ADT/FoldingSet.h | 10 +- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 2 +- llvm/include/llvm/IR/Intrinsics.td | 6 - llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/Bitcode/Reader/MetadataLoader.cpp | 2 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 1 + llvm/lib/CodeGen/IntrinsicLowering.cpp | 8 - .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 8 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 18 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 18 +- llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 2 +- llvm/lib/Target/PowerPC/PPC.td | 6 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 + llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 4 +- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 1 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 + llvm/test/Assembler/dicompileunit.ll | 4 +- .../regbankselect-amdgcn.ds.gws.init.mir | 4 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 2 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 4 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 4 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 2 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 2 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 8 +- llvm/test/CodeGen/AMDGPU/read_register.ll | 16 +- llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll | 3 +- llvm/test/CodeGen/PowerPC/pre-inc-disable.ll | 60 ++-- llvm/test/CodeGen/PowerPC/unaligned-floats.ll | 43 +++ llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 242 +++++++++++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll | 232 +++++++++++++++ llvm/test/DebugInfo/X86/range_reloc.ll | 2 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 28 -- mlir/include/mlir/Dialect/SPIRV/CMakeLists.txt | 16 +- mlir/include/mlir/Dialect/SPIRV/SPIRVAtomicOps.td | 7 + .../mlir/Dialect/SPIRV/SPIRVAvailability.td | 86 ++++++ mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 154 +++++++++- .../mlir/Dialect/SPIRV/SPIRVNonUniformOps.td | 7 + mlir/include/mlir/Dialect/SPIRV/SPIRVOps.h | 23 +- mlir/include/mlir/IR/BlockSupport.h | 2 - mlir/include/mlir/IR/Operation.h | 16 +- mlir/include/mlir/IR/UseDefLists.h | 59 +++- mlir/lib/Dialect/SPIRV/CMakeLists.txt | 1 + mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 8 + mlir/lib/IR/Operation.cpp | 67 +---- mlir/lib/IR/Value.cpp | 33 +++ mlir/test/CMakeLists.txt | 1 + mlir/test/Dialect/CMakeLists.txt | 1 + mlir/test/Dialect/SPIRV/CMakeLists.txt | 14 + mlir/test/Dialect/SPIRV/TestAvailability.cpp | 73 +++++ mlir/test/Dialect/SPIRV/availability.mlir | 31 ++ mlir/tools/mlir-opt/CMakeLists.txt | 1 + mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 328 ++++++++++++++++++++- 65 files changed, 1479 insertions(+), 272 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/unaligned-floats.ll create mode 100644 mlir/include/mlir/Dialect/SPIRV/SPIRVAvailability.td create mode 100644 mlir/test/Dialect/CMakeLists.txt create mode 100644 mlir/test/Dialect/SPIRV/CMakeLists.txt create mode 100644 mlir/test/Dialect/SPIRV/TestAvailability.cpp create mode 100644 mlir/test/Dialect/SPIRV/availability.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits December 2019