Tcwg-commits December 2019

tcwg-commits@lists.linaro.org

5 participants
9704 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (aa91b86c6 -> 117e31c9f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. discards aa91b86c6 0: update: binutils-gcc-linux: all new 117e31c9f 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (aa91b86c6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 432 +- 03-build_abe-binutils/console.log | 11085 ++++++----- 04-build_abe-stage1/console.log | 15883 ++++++++-------- 05-build_linux/console.log | 7720 ++++---- 06-boot_linux/console.log | 8 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 35302 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 35308 insertions(+), 35304 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (9577eace3e8 -> 26b996a95cc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/gcc. from 9577eace3e8 Daily bump. adds 8a969c076ad Catch division by zero errors in array sizes. adds 8541e44c90a 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds e509dbe5090 * fi.po: Update. adds 26b996a95cc Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 11 + gcc/fortran/arith.c | 6 + gcc/fortran/decl.c | 31 +- gcc/fortran/gfortran.h | 2 + gcc/po/ChangeLog | 4 + gcc/po/fi.po | 654 ++++++++++++++------------- gcc/testsuite/ChangeLog | 6 + gcc/testsuite/gfortran.dg/arith_divide_2.f90 | 9 + 9 files changed, 395 insertions(+), 330 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/arith_divide_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (9c09f91fc -> d4a0c9694)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 9c09f91fc 0: update: binutils-gcc-linux: boot new d4a0c9694 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9c09f91fc) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 416 +- 03-build_abe-binutils/console.log | 10997 ++++++------- 04-build_abe-stage1/console.log | 17596 ++++++++++----------- 05-build_linux/console.log | 650 +- 06-boot_linux/console.log | 482 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 30368 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 30373 insertions(+), 30346 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (cde071c4bfb -> 70f8dd4cf60)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig in repository toolchain/ci/llvm-project. from cde071c4bfb [mlir] Update mlir/CMakeLists.txt to install *.td files adds c926d96fcab [X86] Make the AVX1 check lines in vec-strict-inttofp-256.l [...] adds 0007f9da7c0 [lldb][NFC] Delete static versions of ClangASTContext::Crea [...] adds f7d9584c56d Fix formatting in previous commits adds 6991d5728f1 [lldb][NFC] Make integer types functions in ClangASTContext [...] adds b1fb07ddbaa [lldb][NFC] Simplify ClangASTContext::GetTypeForDecl adds 5edb40c0220 [SelectionDAG] Disallow indirect "i" constraint adds 599d0709100 [X86] Remove dyn_casts to ConstantSDNode for operand 1 of X [...] adds b2f19320dc1 [X86] Use isOneConstant to simplify some code. NFC adds 266cd7717c8 [X86] Use APInt::isOneValue and ConstantSDNode::isOne. NFC adds 874a8004f93 [PowerPC] Exploit the rlwinm instructions for "and" with constant adds eadc97b0ec8 [CMake] Added remote test execution support into CrossWinTo [...] adds 6f9b4c6826d [SelectionDAT] Simplify SelectionDAGBuilder::visitInlineAsm adds 45acc35ac21 [ELF][PPC64] Implement IPLT code sequence for non-preemptib [...] adds fb2944bd7f8 [ELF][PPC32] Implement IPLT code sequence for non-preemptib [...] adds bb87364f26c [ELF][PPC64] Improve "call lacks nop" diagnostic and make i [...] adds 34fe8d04511 [Attributor] Use `changeUseAfterManifest` in AAValueSimplif [...] adds 65661908cb6 [NFC] Add test for load-insert-store pattern adds b47b35ff51b [Diagnostic] Add ftabstop to -Wmisleading-indentation adds 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj No new revisions were added by this update. Summary of changes: .../unittests/clang-query/QueryParserTest.cpp | 16 +- clang/cmake/caches/CrossWinToARMLinux.cmake | 30 +- clang/lib/ASTMatchers/Dynamic/Parser.cpp | 3 +- clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 177 +++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 ++-- clang/test/OpenMP/parallel_codegen.cpp | 117 ++-- clang/test/Parser/ms-inline-asm.c | 5 + clang/test/Parser/warn-misleading-indentation.cpp | 83 ++- lld/ELF/Arch/PPC.cpp | 12 +- lld/ELF/Arch/PPC64.cpp | 10 +- lld/ELF/InputSection.cpp | 12 +- lld/ELF/Thunks.cpp | 29 +- lld/ELF/Thunks.h | 5 + ...ptable.s => ppc32-ifunc-nonpreemptible-nopic.s} | 21 +- ...emptable.s => ppc32-ifunc-nonpreemptible-pic.s} | 36 +- lld/test/ELF/ppc64-bsymbolic-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-tail-call.s | 8 +- lld/test/ELF/ppc64-ifunc.s | 95 ++- lld/test/ELF/ppc64-toc-relax-ifunc.s | 4 +- lldb/include/lldb/Symbol/ClangASTContext.h | 46 +- .../Clang/ClangExpressionDeclMap.cpp | 4 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 7 +- lldb/source/Symbol/ClangASTContext.cpp | 119 ++-- llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 4 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 10 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 + llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 - llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 1 - llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 1 - llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 4 - .../Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 24 + llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 21 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 1 - llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 1 - .../Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 1 - llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++--- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 - llvm/lib/Target/X86/X86ISelLowering.cpp | 223 +++--- llvm/lib/Target/X86/X86ISelLowering.h | 4 +- llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 +++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 ++ .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 ++++++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 +++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 ++++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/and-mask.ll | 5 +- llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 4 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 4 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------- .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 ++++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 +++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 +++--- llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 710 +++++++++++++++---- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-07-02-array-indexing.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 2 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Transforms/InstCombine/load-insert-store.ll | 98 +++ llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/tools/opt/opt.cpp | 13 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 ++++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 145 files changed, 6417 insertions(+), 1724 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c copy lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptible- [...] rename lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptibl [...] create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/Transforms/InstCombine/load-insert-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (7da6cdcf0 -> 9987aca5a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 7da6cdcf0 0: update: llvm-linux: boot new 9987aca5a 0: update: llvm-70f8dd4cf604b2be3488895ef0d261154c1c1124: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7da6cdcf0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 193 +- 02-build_llvm/console.log | 12530 ++++++++-------- 03-build_linux/console.log | 17196 +++++++++++----------- 04-boot_linux/console.log | 4 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 29 - console.log | 29962 +++++++++++++++++++------------------- jenkins/manifest.sh | 11 +- 8 files changed, 29615 insertions(+), 30320 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (b1fb07ddbaa -> 6185dc0eb3a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/llvm-project. from b1fb07ddbaa [lldb][NFC] Simplify ClangASTContext::GetTypeForDecl adds 5edb40c0220 [SelectionDAG] Disallow indirect "i" constraint adds 599d0709100 [X86] Remove dyn_casts to ConstantSDNode for operand 1 of X [...] adds b2f19320dc1 [X86] Use isOneConstant to simplify some code. NFC adds 266cd7717c8 [X86] Use APInt::isOneValue and ConstantSDNode::isOne. NFC adds 874a8004f93 [PowerPC] Exploit the rlwinm instructions for "and" with constant adds eadc97b0ec8 [CMake] Added remote test execution support into CrossWinTo [...] adds 6f9b4c6826d [SelectionDAT] Simplify SelectionDAGBuilder::visitInlineAsm adds 45acc35ac21 [ELF][PPC64] Implement IPLT code sequence for non-preemptib [...] adds fb2944bd7f8 [ELF][PPC32] Implement IPLT code sequence for non-preemptib [...] adds bb87364f26c [ELF][PPC64] Improve "call lacks nop" diagnostic and make i [...] adds 34fe8d04511 [Attributor] Use `changeUseAfterManifest` in AAValueSimplif [...] adds 65661908cb6 [NFC] Add test for load-insert-store pattern adds b47b35ff51b [Diagnostic] Add ftabstop to -Wmisleading-indentation adds 36ae255663c [opt] Fix run-twice crash and detection problem adds cd2a73a9f01 [MCP] Add stats for backward copy propagation. NFC. adds 94a24e7a401 [MIPS GlobalISel] Select bswap adds dbc136e0fe7 [MIPS GlobalISel] Select bitreverse adds 4a188fdfa79 [OpenCL] Add mipmap builtin functions adds 8232497c313 [ARM][THUMB2] Allow emitting T3 types of add and sub adds 1b6286b945a [LV][NFC] Some refactoring and renaming to facilitate next change. adds 948e745270d [LV][NFC] Keep dominator tree up to date during vectorization. adds a5a141544d0 [ARM] MVE sink ICmp test. NFC adds b4abe7afbf5 [ARM] Sink splat to ICmp adds 32cc14100e8 Revert "[MIPS GlobalISel] Select bitreverse" adds 0f0330a7870 [PowerPC] Legalize rounding nodes adds 491cfa4250d AMDGPU/GlobalISel: Account for G_PHI result bank adds 58bcf511070 AMDGPU: Generate check lines adds 9e1a2a668b9 AMDGPU: Improve llvm.round.f64 lowering for CI+ adds 9fd31fdbd30 GlobalISel: moreElementsVector for FP min/max adds 18240c3cd63 AMDGPU/GlobalISel: Add select test for fexp2 adds f33fd9648c4 [ARM][Thumb][FIX] Add unwinding information to t4 adds 987eb8e26cc [InstCombine] propagate sign argument through nested copysigns adds 1247865fe02 AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz adds 98f72a5107c [MIPS GlobalISel] Select bitreverse. Recommit adds ee3eebba0d3 [InstCombine] remove stale comment on test; NFC adds 03b9f0a5e19 Ignore "no-frame-pointer-elim" and "no-frame-pointer-elim-n [...] adds 48e0e68edb3 AMDGPU/GlobalISel: Re-use MRI available in selector adds 0c5bee8fdd4 [test] do not parse ls output for file size; NFCI adds 47a2fd2df4f [X86] Add X86ISD::PCMPGT to SimplifyMultipleUseDemandedBits [...] adds 94d08feaeff TableGen: Fix assert on PatFrags with predicate code adds 7fa0bfe7d58 AMDGPU/GlobalISel: Select mul24 intrinsics adds 4a7aa252a32 [X86][AsmParser] re-introduce 'offset' operator adds 000c6a5038b [OpenMP] Use the OpenMPIRBuilder for `omp cancel` adds 10fedd94b43 [OpenMP] Use the OpenMPIRBuilder for `omp parallel` adds 0bd3cc42485 [PowerPC][docs] Update Embedded PowerPC docs in Compiler Wr [...] adds bc48af8c575 [libomptarget][nfc] Change unintentional target_impl prefix [...] adds 6bd1fcd7959 [OpenMP][FIX] Generalize a test check line adds 07be32961a6 Remove a redundant `default:` on an exhaustive switch(enum). adds 8b23b2bbd96 [CodeGen] Use CreateFNeg in buildFMulAdd adds 70f8dd4cf60 [CodeGen] Use IRBuilder::CreateFNeg for __builtin_conj new 6185dc0eb3a [X86] Add test case for PR44412. NFC The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/cmake/caches/CrossWinToARMLinux.cmake | 30 +- clang/lib/CodeGen/CGBuiltin.cpp | 7 +- clang/lib/CodeGen/CGExprScalar.cpp | 15 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 95 +++ clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 177 +++++ clang/lib/Sema/SemaStmtAsm.cpp | 7 +- clang/test/CodeGen/complex-builtins-2.c | 20 + clang/test/CodeGen/fp-contract-pragma.cpp | 15 + clang/test/CodeGen/ms-inline-asm-64.c | 4 +- clang/test/CodeGen/ms-inline-asm.c | 12 +- clang/test/CodeGen/ms-inline-asm.cpp | 2 +- clang/test/OpenMP/cancel_codegen.cpp | 119 ++-- clang/test/OpenMP/parallel_codegen.cpp | 117 ++-- clang/test/Parser/ms-inline-asm.c | 5 + clang/test/Parser/warn-misleading-indentation.cpp | 83 ++- lld/ELF/Arch/PPC.cpp | 12 +- lld/ELF/Arch/PPC64.cpp | 10 +- lld/ELF/InputSection.cpp | 12 +- lld/ELF/Thunks.cpp | 29 +- lld/ELF/Thunks.h | 5 + ...ptable.s => ppc32-ifunc-nonpreemptible-nopic.s} | 21 +- ...emptable.s => ppc32-ifunc-nonpreemptible-pic.s} | 36 +- lld/test/ELF/ppc64-bsymbolic-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-restore.s | 2 +- lld/test/ELF/ppc64-error-toc-tail-call.s | 8 +- lld/test/ELF/ppc64-ifunc.s | 95 ++- lld/test/ELF/ppc64-toc-relax-ifunc.s | 4 +- llvm/docs/CompilerWriterInfo.rst | 12 +- llvm/docs/ReleaseNotes.rst | 5 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 + llvm/include/llvm/CodeGen/TargetLowering.h | 4 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 18 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 29 +- llvm/include/llvm/IR/AutoUpgrade.h | 5 + llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h | 8 +- llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h | 47 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 10 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 1 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 111 ++- llvm/lib/CodeGen/MachineCopyPropagation.cpp | 6 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 + llvm/lib/CodeGen/TargetOptionsImpl.cpp | 14 +- llvm/lib/Frontend/OpenMP/OMPConstants.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 138 +++- llvm/lib/IR/AutoUpgrade.cpp | 20 + llvm/lib/MC/MCParser/AsmParser.cpp | 52 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 18 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 36 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 7 +- llvm/lib/Target/AMDGPU/VOP2Instructions.td | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 2 + llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 - llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 4 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 75 +- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 1 - llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp | 1 - llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 17 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 1 + llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 4 - .../Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 24 + llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 21 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 15 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 37 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 1 - llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 1 - .../Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 1 - llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 216 +++--- llvm/lib/Target/X86/AsmParser/X86Operand.h | 20 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 8 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 - llvm/lib/Target/X86/X86ISelLowering.cpp | 223 +++--- llvm/lib/Target/X86/X86ISelLowering.h | 4 +- llvm/lib/Transforms/IPO/Attributor.cpp | 6 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 10 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 227 +++--- llvm/lib/Transforms/Vectorize/VPlan.cpp | 10 +- llvm/lib/Transforms/Vectorize/VPlan.h | 4 +- llvm/test/Bitcode/upgrade-frame-pointer.ll | 33 + .../GlobalISel/inst-select-amdgcn.fmad.ftz.mir | 233 +++++++ .../GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 ++ .../AMDGPU/GlobalISel/inst-select-fexp2.mir | 42 ++ .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 21 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 42 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 96 ++- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 14 +- llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll | 762 ++++++++++++++++++++- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir | 88 +++ .../Mips/GlobalISel/instruction-select/bswap.mir | 30 + .../Mips/GlobalISel/legalizer/bitreverse.mir | 215 ++++++ .../CodeGen/Mips/GlobalISel/legalizer/bswap.mir | 101 +++ .../CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll | 184 +++++ llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll | 68 ++ .../Mips/GlobalISel/regbankselect/bswap.mir | 28 + llvm/test/CodeGen/PowerPC/and-mask.ll | 5 +- llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll | 2 +- llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 4 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 4 +- llvm/test/CodeGen/PowerPC/rounding-ops.ll | 8 +- llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll | 561 +++++++++++++++ .../PowerPC/vector-constrained-fp-intrinsics.ll | 372 +++------- .../cond-vector-reduce-mve-codegen.ll | 17 +- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 280 ++++---- llvm/test/CodeGen/Thumb2/emit-unwinding.ll | 15 + llvm/test/CodeGen/Thumb2/large-call.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 615 +++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 3 +- llvm/test/CodeGen/X86/ms-inline-asm.ll | 2 +- llvm/test/CodeGen/X86/offset-operator.ll | 15 + llvm/test/CodeGen/X86/pr44412.ll | 36 + llvm/test/CodeGen/X86/sadd_sat.ll | 4 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 140 ++-- llvm/test/CodeGen/X86/ssub_sat.ll | 10 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 220 +++--- llvm/test/MC/X86/pr32530.s | 13 + llvm/test/TableGen/predicate-patfags.td | 63 ++ .../ArgumentPromotion/2008-07-02-array-indexing.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow.ll | 2 +- .../Attributor/ArgumentPromotion/control-flow2.ll | 4 +- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 2 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- llvm/test/Transforms/InstCombine/copysign.ll | 5 +- .../Transforms/InstCombine/load-insert-store.ll | 98 +++ llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- .../tools/yaml2obj/ELF/custom-null-section.yaml | 4 +- llvm/tools/opt/opt.cpp | 13 +- llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 120 ++++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 26 +- .../deviceRTLs/amdgcn/src/target_impl.h | 4 +- .../libomptarget/deviceRTLs/common/src/libcall.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 6 +- 139 files changed, 5786 insertions(+), 1486 deletions(-) create mode 100644 clang/test/CodeGen/complex-builtins-2.c copy lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptible- [...] rename lld/test/ELF/{ppc32-gnu-ifunc-nonpreemptable.s => ppc32-ifunc-nonpreemptibl [...] create mode 100644 llvm/test/Bitcode/upgrade-frame-pointer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir create mode 100644 llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitreverse.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/bswap.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bswap.mir create mode 100644 llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll create mode 100644 llvm/test/CodeGen/X86/offset-operator.ll create mode 100644 llvm/test/CodeGen/X86/pr44412.ll create mode 100644 llvm/test/MC/X86/pr32530.s create mode 100644 llvm/test/TableGen/predicate-patfags.td create mode 100644 llvm/test/Transforms/InstCombine/load-insert-store.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (f5d5b0195 -> a77f230a4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards f5d5b0195 0: update: llvm-linux: all new a77f230a4 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f5d5b0195) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 184 +- 02-build_llvm/console.log | 12518 +++++++++++++++++------------------ 03-build_linux/console.log | 685 +- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 10 +- console.log | 13409 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13390 insertions(+), 13436 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (9577eace3e8 -> 26b996a95cc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/gcc. from 9577eace3e8 Daily bump. adds 8a969c076ad Catch division by zero errors in array sizes. adds 8541e44c90a 2019-12-30 Thomas Koenig <tkoenig(a)gcc.gnu.org> adds e509dbe5090 * fi.po: Update. new 26b996a95cc Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 11 + gcc/fortran/arith.c | 6 + gcc/fortran/decl.c | 31 +- gcc/fortran/gfortran.h | 2 + gcc/po/ChangeLog | 4 + gcc/po/fi.po | 654 ++++++++++++++------------- gcc/testsuite/ChangeLog | 6 + gcc/testsuite/gfortran.dg/arith_divide_2.f90 | 9 + 9 files changed, 395 insertions(+), 330 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/arith_divide_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (064cf1ebf -> 8656a3b1e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards 064cf1ebf 0: update: binutils-gcc-linux: boot new 8656a3b1e 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (064cf1ebf) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 184 +- 02-prepare_abe/console.log | 410 +- 03-build_abe-binutils/console.log | 10759 ++++++------- 04-build_abe-stage1/console.log | 18327 +++++++++++---------- 05-build_linux/console.log | 884 +- 06-boot_linux/console.log | 416 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 30990 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 30999 insertions(+), 30999 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

[gcc] branch gcc-9-branch updated (e509dbe5090 -> 26b996a95cc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-9-branch in repository gcc. from e509dbe5090 * fi.po: Update. new 26b996a95cc Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 10 months

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits December 2019