Tcwg-commits December 2019

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (3cb934c94e5 -> ba1cdba4c48)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project. from 3cb934c94e5 [OPENMP][DOCS]Update status of OpenMP 5.0 features, NFC. adds a21beccea20 [X86] Add STRICT versions of CVTTP2SI, CVTTP2UI, CMPM, and CMPP. adds 64c6bb37832 test: ensure that we dead-strip in the linker adds 020ca0cf2f1 [mlir] Fix -Wunneeded-internal-declaration adds c06e53119b1 [X86] Use 128-bit vector instructions for f32/f64->i64 conv [...] adds fc356dcc11c [compiler-rt] Adapt stop-the-world for ptrace changes in Ne [...] adds 4b8232d4f0b [compiler-rt] Adapt for ptrace(2) changes in NetBSD-9.99.30 adds ab8a7a29bf1 [lldb] Adapt for NetBSD-9.99.30 ptrace(2) API changes adds 1f054d667e2 AMDGPU/GlobalISel: Fix mapping and selection of llvm.amdgcn [...] adds 3732f4e093f [OPENMP]Add extra checks and initialization for clause modifier. adds 502a77f125f Migrate function attribute "no-frame-pointer-elim" to "fram [...] adds eb16435b5e5 Migrate function attribute "no-frame-pointer-elim-non-leaf" [...] adds a36ddf0aa9d Migrate function attribute "no-frame-pointer-elim"="false" [...] adds 9f6b13e5cce [Support] Fix behavior of StringRef::count with overlapping [...] adds c853c73d3de [Thumb][test] Fix CodeGen/Thumb/PR17309.ll after llvmorg-1 [...] adds 1ac7c50ded4 [WinEH] Delete addFnAttr("no-frame-pointer-elim") which see [...] adds 583ef13f0be [MCJIT] Migrate function attribute "no-frame-pointer-elim" [...] adds 58f324a468f [Attributor] Function level undefined behavior attribute adds 5732f56bbd2 [Attributor] UB Attribute now handles all instructions that [...] adds 52b5fe5f45b [compiler-rt] [netbsd] Define _RTLD_SOURCE to fix build adds 27dc4c319b5 [X86FixupSetCC] Use MachineInstr::readRegister/definesRegis [...] adds 1d5d074aef2 [Attributor] Reach optimistic fixpoint in AAValueSimplify [...] adds 1497a4350e2 [MLIR][NFC] Insert const_cast to avoid warning adds 8304781cae9 Add missing strict_fp_to_int adds 604d7fbfc1e [llvm-readobj/llvm-readelf][test] - Add testing for EI_OSAB [...] adds 1a2d2b492a3 [llvm-readobj] - Merge `gnu-symbols.test` to `symbols.test` [...] adds 80c45e49c33 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. new aff6c9db9a9 [compiler-rt] [netbsd] Correct the fallback definition of P [...] new ba1cdba4c48 [llvm-nm] Display STT_GNU_IFUNC as 'i' The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/Parse/ParseOpenMP.cpp | 9 +- clang/lib/Sema/SemaOpenMP.cpp | 8 + clang/test/CodeGen/backend-unsupported-error.ll | 2 +- .../include/sanitizer/netbsd_syscall_hooks.h | 2 +- .../sanitizer_common/sanitizer_linux_libcdep.cpp | 4 + .../sanitizer_platform_limits_netbsd.cpp | 14 + .../sanitizer_platform_limits_netbsd.h | 11 + .../sanitizer_stoptheworld_netbsd_libcdep.cpp | 12 +- .../sanitizer_common/sanitizer_syscalls_netbsd.inc | 22 +- compiler-rt/utils/generate_netbsd_syscalls.awk | 18 +- lld/test/COFF/Inputs/undefined-symbol-lto-a.ll | 4 +- lld/test/COFF/Inputs/undefined-symbol-lto-b.ll | 2 +- lld/test/COFF/lto-cpu-string.ll | 2 +- lld/test/ELF/lto/cpu-string.ll | 2 +- lld/test/ELF/ppc64-ifunc.s | 4 +- lld/test/wasm/Inputs/debuginfo1.ll | 6 +- lld/test/wasm/Inputs/debuginfo2.ll | 2 +- lld/test/wasm/debug-removed-fn.ll | 2 +- .../test/functionalities/dead-strip/Makefile | 1 + .../Plugins/Process/NetBSD/NativeProcessNetBSD.cpp | 12 +- .../Plugins/Process/NetBSD/NativeThreadNetBSD.cpp | 11 + llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 163 +++++------ llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 19 +- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 58 ++++ llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 58 ++++ llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 93 +++++++ llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 165 +++++++++++ ...x9_mad_type_dev.rst => gfx900_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx900_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx900_src32_1.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx904_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx904_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx904_src32_1.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx906_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx906_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx906_src32_1.rst | 17 ++ llvm/docs/AMDGPU/gfx906_src32_2.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_addr_buf.rst | 22 ++ ...gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} | 10 +- ...gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst | 21 ++ ...d_type_dev.rst => gfx908_dst_flat_atomic32.rst} | 12 +- ...x9_mad_type_dev.rst => gfx908_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx908_offset_buf.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx908_opt.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_ret.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} | 10 +- llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 19 ++ llvm/docs/AMDGPU/gfx908_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx908_src32_1.rst | 17 ++ llvm/docs/AMDGPU/gfx908_src32_2.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} | 9 +- llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 22 ++ ...{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPUModifierSyntax.rst | 55 +++- llvm/docs/AMDGPUOperandSyntax.rst | 60 ++++ llvm/docs/AMDGPUUsage.rst | 38 ++- llvm/docs/SourceLevelDebugging.rst | 2 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 26 ++ .../ExecutionEngine/ExecutionEngineBindings.cpp | 6 +- llvm/lib/Support/StringRef.cpp | 9 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 6 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 1 + llvm/lib/Target/X86/X86FixupSetCC.cpp | 18 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 23 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 186 +++++++------ llvm/lib/Target/X86/X86ISelLowering.h | 3 + llvm/lib/Target/X86/X86InstrAVX512.td | 82 +++--- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 25 +- llvm/lib/Target/X86/X86InstrSSE.td | 52 ++-- llvm/lib/Target/X86/X86WinEHState.cpp | 5 - llvm/lib/Transforms/IPO/Attributor.cpp | 125 ++++++++- .../test/Analysis/BranchProbabilityInfo/pr22718.ll | 6 +- .../CostModel/SystemZ/intrinsic-cost-crash.ll | 2 +- .../constant_functions_multi_dim.ll | 4 +- .../Analysis/DependenceAnalysis/MIVCheckConst.ll | 2 +- .../NonCanonicalizedSubscript.ll | 2 +- .../invariant.group-bug.ll | 4 +- llvm/test/Analysis/MemorySSA/pr28880.ll | 2 +- llvm/test/Analysis/MemorySSA/pr39197.ll | 2 +- llvm/test/Analysis/MemorySSA/pr40038.ll | 2 +- llvm/test/Analysis/ScalarEvolution/pr22674.ll | 2 +- .../ScalarEvolution/scev-canonical-mode.ll | 2 +- .../Analysis/TypeBasedAliasAnalysis/PR17620.ll | 4 +- .../Analysis/TypeBasedAliasAnalysis/tbaa-path.ll | 2 +- llvm/test/Bitcode/DILocation-implicit-code.ll | 4 +- llvm/test/Bitcode/drop-debug-info.3.5.ll | 2 +- llvm/test/Bitcode/upgrade-tbaa.ll | 2 +- llvm/test/BugPoint/func-attrs-keyval.ll | 2 +- llvm/test/BugPoint/func-attrs.ll | 4 +- .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 2 +- .../CodeGen/AArch64/GlobalISel/inline-memmove.mir | 2 +- .../CodeGen/AArch64/GlobalISel/inline-memset.mir | 2 +- .../aarch64-2014-08-11-MachineCombinerCrash.ll | 2 +- .../AArch64/aarch64-a57-fp-load-balancing.ll | 4 +- .../AArch64/aarch64-fix-cortex-a53-835769.ll | 4 +- .../CodeGen/AArch64/aarch64-mov-debug-locs.mir | 4 +- .../test/CodeGen/AArch64/arm64-detect-vec-redux.ll | 2 +- .../AArch64/arm64-fma-combine-with-fpfusion.ll | 2 +- .../CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll | 2 +- .../CodeGen/AArch64/arm64-misched-basic-A53.ll | 2 +- .../CodeGen/AArch64/arm64-misched-basic-A57.ll | 2 +- llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll | 4 +- .../AArch64/arm64-triv-disjoint-mem-access.ll | 2 +- .../CodeGen/AArch64/branch-relax-block-size.mir | 2 +- llvm/test/CodeGen/AArch64/consthoist-gep.ll | 2 +- llvm/test/CodeGen/AArch64/cxx-tlscc.ll | 2 +- .../test/CodeGen/AArch64/dag-combine-invaraints.ll | 4 +- llvm/test/CodeGen/AArch64/large-stack.ll | 2 +- .../AArch64/loopvectorize_pr33804_double.ll | 2 +- .../CodeGen/AArch64/machine-outliner-all-stack.mir | 2 +- .../machine-outliner-compatible-candidates.mir | 2 +- .../AArch64/machine-outliner-drop-stack.mir | 2 +- .../CodeGen/AArch64/machine-outliner-regsave.mir | 2 +- .../CodeGen/AArch64/machine-outliner-remarks.ll | 2 +- .../machine-outliner-retaddr-sign-regsave.mir | 2 +- .../machine-outliner-retaddr-sign-sp-mod.mir | 2 +- .../CodeGen/AArch64/machine-outliner-size-info.mir | 2 +- .../AArch64/machine-outliner-unsafe-stack-call.mir | 2 +- llvm/test/CodeGen/AArch64/machine-outliner.mir | 2 +- llvm/test/CodeGen/AArch64/preferred-alignment.ll | 4 +- .../test/CodeGen/AArch64/sched-past-vector-ldst.ll | 2 +- llvm/test/CodeGen/AArch64/stack_guard_remat.ll | 2 +- .../test/CodeGen/AArch64/vector_merge_dep_check.ll | 2 +- llvm/test/CodeGen/AArch64/win64_vararg.ll | 2 +- llvm/test/CodeGen/AArch64/wineh-frame5.mir | 4 +- llvm/test/CodeGen/AArch64/wineh-frame6.mir | 4 +- llvm/test/CodeGen/AArch64/wineh-frame7.mir | 4 +- llvm/test/CodeGen/AArch64/wineh-frame8.mir | 2 +- llvm/test/CodeGen/AArch64/wineh5.mir | 4 +- llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir | 4 +- .../CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 2 +- llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | 2 +- llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll | 2 +- llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll | 2 +- llvm/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll | 2 +- llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll | 2 +- .../CodeGen/ARM/2016-05-01-RegScavengerAssert.ll | 2 +- llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir | 4 +- llvm/test/CodeGen/ARM/Windows/wineh-basic.ll | 4 +- llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll | 24 +- llvm/test/CodeGen/ARM/arm-storebytesmerge.ll | 2 +- llvm/test/CodeGen/ARM/byval_load_align.ll | 4 +- llvm/test/CodeGen/ARM/call-tc.ll | 20 +- llvm/test/CodeGen/ARM/cfguard-module-flag.ll | 2 +- llvm/test/CodeGen/ARM/clang-section.ll | 8 +- llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll | 4 +- llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll | 2 +- llvm/test/CodeGen/ARM/constantpool-promote.ll | 4 +- llvm/test/CodeGen/ARM/cxx-tlscc.ll | 14 +- llvm/test/CodeGen/ARM/debug-info-arg.ll | 2 +- llvm/test/CodeGen/ARM/disable-fp-elim.ll | 4 +- llvm/test/CodeGen/ARM/dwarf-unwind.ll | 2 +- llvm/test/CodeGen/ARM/early-cfi-sections.ll | 2 +- llvm/test/CodeGen/ARM/global-merge-1.ll | 6 +- llvm/test/CodeGen/ARM/hello.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt10.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt5.ll | 4 +- llvm/test/CodeGen/ARM/insn-sched1.ll | 2 +- llvm/test/CodeGen/ARM/isel-v8i32-crash.ll | 2 +- llvm/test/CodeGen/ARM/ldrd.ll | 18 +- llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll | 2 +- llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll | 2 +- llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll | 4 +- llvm/test/CodeGen/ARM/memfunc.ll | 18 +- llvm/test/CodeGen/ARM/noreturn.ll | 10 +- llvm/test/CodeGen/ARM/out-of-registers.ll | 2 +- llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir | 4 +- .../CodeGen/ARM/stack-protector-bmovpcb_call.ll | 4 +- llvm/test/CodeGen/ARM/stack-size-section.ll | 2 +- llvm/test/CodeGen/ARM/stack_guard_remat.ll | 2 +- llvm/test/CodeGen/ARM/struct-byval-frame-index.ll | 2 +- llvm/test/CodeGen/ARM/swiftself.ll | 12 +- llvm/test/CodeGen/ARM/unschedule-first-call.ll | 2 +- llvm/test/CodeGen/ARM/urem-opt-size.ll | 2 +- llvm/test/CodeGen/ARM/v7k-abi-align.ll | 22 +- llvm/test/CodeGen/ARM/vector-spilling.ll | 2 +- llvm/test/CodeGen/ARM/vldm-sched-a9.ll | 2 +- llvm/test/CodeGen/ARM/warn-stack.ll | 4 +- llvm/test/CodeGen/BPF/BTF/binary-format.ll | 2 +- llvm/test/CodeGen/BPF/BTF/char-no-debuginfo.ll | 2 +- llvm/test/CodeGen/BPF/BTF/extern-global-var.ll | 2 +- llvm/test/CodeGen/BPF/BTF/filename.ll | 2 +- llvm/test/CodeGen/BPF/BTF/func-func-ptr.ll | 2 +- llvm/test/CodeGen/BPF/BTF/func-non-void.ll | 2 +- llvm/test/CodeGen/BPF/BTF/func-source.ll | 2 +- llvm/test/CodeGen/BPF/BTF/func-typedef.ll | 2 +- llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll | 2 +- llvm/test/CodeGen/BPF/BTF/func-void.ll | 2 +- llvm/test/CodeGen/BPF/BTF/local-var.ll | 2 +- .../CodeGen/BPF/BTF/static-var-derived-type.ll | 2 +- llvm/test/CodeGen/BPF/BTF/static-var-inited-sec.ll | 2 +- llvm/test/CodeGen/BPF/BTF/static-var-inited.ll | 2 +- .../CodeGen/BPF/BTF/static-var-readonly-sec.ll | 2 +- llvm/test/CodeGen/BPF/BTF/static-var-readonly.ll | 2 +- llvm/test/CodeGen/BPF/BTF/static-var-sec.ll | 2 +- .../CodeGen/BPF/BTF/static-var-zerolen-array.ll | 2 +- llvm/test/CodeGen/BPF/BTF/static-var.ll | 2 +- llvm/test/CodeGen/BPF/CORE/intrinsic-array.ll | 4 +- llvm/test/CodeGen/BPF/CORE/intrinsic-struct.ll | 4 +- llvm/test/CodeGen/BPF/CORE/intrinsic-union.ll | 4 +- llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll | 2 +- .../CodeGen/BPF/CORE/offset-reloc-multilevel.ll | 2 +- .../BPF/CORE/offset-reloc-struct-anonymous.ll | 2 +- .../CodeGen/BPF/CORE/offset-reloc-struct-array.ll | 2 +- llvm/test/CodeGen/BPF/CORE/offset-reloc-union.ll | 2 +- llvm/test/CodeGen/BPF/dwarfdump.ll | 2 +- llvm/test/CodeGen/BPF/objdump_two_funcs.ll | 2 +- llvm/test/CodeGen/BPF/reloc-btf-2.ll | 2 +- llvm/test/CodeGen/BPF/reloc-btf.ll | 2 +- llvm/test/CodeGen/BPF/warn-stack.ll | 4 +- llvm/test/CodeGen/BPF/xadd.ll | 2 +- llvm/test/CodeGen/Generic/DbgValueAggregate.ll | 2 +- llvm/test/CodeGen/Generic/cfi-sections.ll | 4 +- llvm/test/CodeGen/Hexagon/NVJumpCmp.ll | 2 +- llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll | 2 +- llvm/test/CodeGen/Hexagon/alu64.ll | 2 +- llvm/test/CodeGen/Hexagon/base-offset-addr.ll | 2 +- llvm/test/CodeGen/Hexagon/base-offset-post.ll | 2 +- llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll | 4 +- llvm/test/CodeGen/Hexagon/builtin-prefetch.ll | 2 +- llvm/test/CodeGen/Hexagon/cfi-offset.ll | 2 +- llvm/test/CodeGen/Hexagon/cmp-extend.ll | 2 +- llvm/test/CodeGen/Hexagon/cmp.ll | 2 +- llvm/test/CodeGen/Hexagon/constp-combine-neg.ll | 2 +- llvm/test/CodeGen/Hexagon/constp-extract.ll | 2 +- llvm/test/CodeGen/Hexagon/constp-physreg.ll | 2 +- llvm/test/CodeGen/Hexagon/dead-store-stack.ll | 4 +- llvm/test/CodeGen/Hexagon/dealloc_return.ll | 2 +- .../CodeGen/Hexagon/early-if-conversion-bug1.ll | 4 +- llvm/test/CodeGen/Hexagon/ehabi.ll | 2 +- llvm/test/CodeGen/Hexagon/fminmax.ll | 2 +- llvm/test/CodeGen/Hexagon/fpelim-basic.ll | 4 +- llvm/test/CodeGen/Hexagon/hasfp-crash1.ll | 2 +- llvm/test/CodeGen/Hexagon/hasfp-crash2.ll | 2 +- .../Hexagon/hexagon_vector_loop_carried_reuse.ll | 2 +- .../hexagon_vector_loop_carried_reuse_constant.ll | 2 +- llvm/test/CodeGen/Hexagon/hwloop-crit-edge.ll | 2 +- llvm/test/CodeGen/Hexagon/hwloop-preheader.ll | 2 +- llvm/test/CodeGen/Hexagon/insert4.ll | 2 +- llvm/test/CodeGen/Hexagon/jt-in-text.ll | 2 +- llvm/test/CodeGen/Hexagon/mem-fi-add.ll | 4 +- llvm/test/CodeGen/Hexagon/memops-stack.ll | 4 +- llvm/test/CodeGen/Hexagon/pic-regusage.ll | 2 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| 2 +- polly/test/ScopInfo/intrinsics.ll | 2 +- .../ScopInfo/long-sequence-of-error-blocks-2.ll | 6 +- .../test/ScopInfo/long-sequence-of-error-blocks.ll | 6 +- polly/test/ScopInfo/memcpy-raw-source.ll | 2 +- .../test/ScopInfo/mismatching-array-dimensions.ll | 2 +- polly/test/ScopInfo/multidim_srem.ll | 2 +- polly/test/ScopInfo/remarks.ll | 4 +- .../ScopInfo/scev-div-with-evaluatable-divisor.ll | 2 +- polly/test/ScopInfo/unnamed_stmts.ll | 2 +- polly/test/Simplify/phi_in_regionstmt.ll | 2 +- 983 files changed, 3656 insertions(+), 2270 deletions(-) create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_addr_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_dst_flat_atomic32.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_offset_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_opt.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_ret.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} (52%) rename llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} (52%) create mode 100644 llvm/test/Transforms/Attributor/undefined_behavior.ll create mode 100644 llvm/test/tools/llvm-nm/ifunc.test delete mode 100644 llvm/test/tools/llvm-readobj/ELF/Inputs/relocs.obj.elf-x86_64 delete mode 100644 llvm/test/tools/llvm-readobj/ELF/Inputs/symbols-proc-specific.e [...] create mode 100644 llvm/test/tools/llvm-readobj/ELF/file-header-abi-version.test create mode 100644 llvm/test/tools/llvm-readobj/ELF/file-header-os-abi.test delete mode 100644 llvm/test/tools/llvm-readobj/ELF/gnu-symbols.test -- To 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4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (cfb74e3d -> 7b3eeec5)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards cfb74e3d 0: update: llvm-linux: boot new 7b3eeec5 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cfb74e3d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-build_llvm/console.log | 12614 +++++++++++++-------------- 03-build_linux/console.log | 4684 +++++----- 04-boot_linux/console.log | 410 +- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 29 - console.log | 17815 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 17790 insertions(+), 17848 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig updated (35f54868a08 -> 8a77631cd23)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig in repository toolchain/ci/gcc. from 35f54868a08 Daily bump. adds 8a77631cd23 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig updated (f00c7390 -> fdf3d115)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allnoconfig in repository toolchain/ci/base-artifacts. discards f00c7390 0: update: binutils-gcc-linux: boot new fdf3d115 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f00c7390) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-prepare_abe/console.log | 396 +- 03-build_abe-binutils/console.log | 10657 +++++++-------- 04-build_abe-stage1/console.log | 14120 ++++++++++--------- 05-build_linux/console.log | 734 +- 07-check_regression/console.log | 10 +- 08-update_baseline/console.log | 10 +- console.log | 26229 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 9 files changed, 26189 insertions(+), 26195 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (0d47399167e -> 80c45e49c33)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project. from 0d47399167e GlobalISel: Update syntax in debug printing adds 93dc40dddde [OPENMP50]Basic support for conditional lastprivate. adds 3cb934c94e5 [OPENMP][DOCS]Update status of OpenMP 5.0 features, NFC. adds a21beccea20 [X86] Add STRICT versions of CVTTP2SI, CVTTP2UI, CMPM, and CMPP. adds 64c6bb37832 test: ensure that we dead-strip in the linker adds 020ca0cf2f1 [mlir] Fix -Wunneeded-internal-declaration adds c06e53119b1 [X86] Use 128-bit vector instructions for f32/f64->i64 conv [...] adds fc356dcc11c [compiler-rt] Adapt stop-the-world for ptrace changes in Ne [...] adds 4b8232d4f0b [compiler-rt] Adapt for ptrace(2) changes in NetBSD-9.99.30 adds ab8a7a29bf1 [lldb] Adapt for NetBSD-9.99.30 ptrace(2) API changes adds 1f054d667e2 AMDGPU/GlobalISel: Fix mapping and selection of llvm.amdgcn [...] adds 3732f4e093f [OPENMP]Add extra checks and initialization for clause modifier. adds 502a77f125f Migrate function attribute "no-frame-pointer-elim" to "fram [...] adds eb16435b5e5 Migrate function attribute "no-frame-pointer-elim-non-leaf" [...] adds a36ddf0aa9d Migrate function attribute "no-frame-pointer-elim"="false" [...] adds 9f6b13e5cce [Support] Fix behavior of StringRef::count with overlapping [...] adds c853c73d3de [Thumb][test] Fix CodeGen/Thumb/PR17309.ll after llvmorg-1 [...] adds 1ac7c50ded4 [WinEH] Delete addFnAttr("no-frame-pointer-elim") which see [...] adds 583ef13f0be [MCJIT] Migrate function attribute "no-frame-pointer-elim" [...] adds 58f324a468f [Attributor] Function level undefined behavior attribute adds 5732f56bbd2 [Attributor] UB Attribute now handles all instructions that [...] adds 52b5fe5f45b [compiler-rt] [netbsd] Define _RTLD_SOURCE to fix build adds 27dc4c319b5 [X86FixupSetCC] Use MachineInstr::readRegister/definesRegis [...] adds 1d5d074aef2 [Attributor] Reach optimistic fixpoint in AAValueSimplify [...] adds 1497a4350e2 [MLIR][NFC] Insert const_cast to avoid warning adds 8304781cae9 Add missing strict_fp_to_int adds 604d7fbfc1e [llvm-readobj/llvm-readelf][test] - Add testing for EI_OSAB [...] adds 1a2d2b492a3 [llvm-readobj] - Merge `gnu-symbols.test` to `symbols.test` [...] adds 80c45e49c33 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. No new revisions were added by this update. Summary of changes: clang/docs/OpenMPSupport.rst | 4 +- clang/include/clang/AST/OpenMPClause.h | 34 ++- clang/include/clang/Basic/DiagnosticSemaKinds.td | 3 + clang/include/clang/Basic/OpenMPKinds.def | 7 + clang/include/clang/Basic/OpenMPKinds.h | 7 + clang/include/clang/Parse/Parser.h | 7 +- clang/include/clang/Sema/Sema.h | 15 +- clang/lib/AST/OpenMPClause.cpp | 18 +- clang/lib/Basic/OpenMPKinds.cpp | 17 +- clang/lib/Parse/ParseOpenMP.cpp | 81 ++++-- clang/lib/Sema/SemaOpenMP.cpp | 69 +++-- clang/lib/Sema/TreeTransform.h | 10 +- clang/lib/Serialization/ASTReader.cpp | 4 + clang/lib/Serialization/ASTWriter.cpp | 3 + clang/test/CodeGen/backend-unsupported-error.ll | 2 +- ...istribute_parallel_for_lastprivate_messages.cpp | 11 +- ...bute_parallel_for_simd_lastprivate_messages.cpp | 15 +- .../distribute_simd_lastprivate_messages.cpp | 15 +- clang/test/OpenMP/for_lastprivate_messages.cpp | 13 +- .../test/OpenMP/for_simd_lastprivate_messages.cpp | 17 +- .../master_taskloop_lastprivate_messages.cpp | 10 +- .../test/OpenMP/master_taskloop_simd_ast_print.cpp | 2 +- .../master_taskloop_simd_lastprivate_messages.cpp | 14 +- clang/test/OpenMP/parallel_for_ast_print.cpp | 4 +- .../OpenMP/parallel_for_lastprivate_messages.cpp | 12 +- clang/test/OpenMP/parallel_for_simd_ast_print.cpp | 4 +- .../parallel_for_simd_lastprivate_messages.cpp | 14 +- ...rallel_master_taskloop_lastprivate_messages.cpp | 10 +- .../parallel_master_taskloop_simd_ast_print.cpp | 2 +- ...l_master_taskloop_simd_lastprivate_messages.cpp | 10 +- .../parallel_sections_lastprivate_messages.cpp | 12 +- .../test/OpenMP/sections_lastprivate_messages.cpp | 14 +- clang/test/OpenMP/simd_ast_print.cpp | 4 +- clang/test/OpenMP/simd_lastprivate_messages.cpp | 13 +- .../target_parallel_for_lastprivate_messages.cpp | 10 +- ...rget_parallel_for_simd_lastprivate_messages.cpp | 16 +- clang/test/OpenMP/target_simd_ast_print.cpp | 4 +- .../OpenMP/target_simd_lastprivate_messages.cpp | 14 +- ...arget_teams_distribute_lastprivate_messages.cpp | 8 +- ...istribute_parallel_for_lastprivate_messages.cpp | 7 +- ...bute_parallel_for_simd_lastprivate_messages.cpp | 4 + ..._teams_distribute_simd_lastprivate_messages.cpp | 4 + .../test/OpenMP/taskloop_lastprivate_messages.cpp | 10 +- clang/test/OpenMP/taskloop_simd_ast_print.cpp | 2 +- .../OpenMP/taskloop_simd_lastprivate_messages.cpp | 14 +- .../teams_distribute_lastprivate_messages.cpp | 10 +- ...istribute_parallel_for_lastprivate_messages.cpp | 10 +- ...bute_parallel_for_simd_lastprivate_messages.cpp | 10 +- .../teams_distribute_simd_lastprivate_messages.cpp | 10 +- .../include/sanitizer/netbsd_syscall_hooks.h | 2 +- .../sanitizer_common/sanitizer_linux_libcdep.cpp | 4 + .../sanitizer_platform_limits_netbsd.cpp | 14 + .../sanitizer_platform_limits_netbsd.h | 11 + .../sanitizer_stoptheworld_netbsd_libcdep.cpp | 12 +- .../sanitizer_common/sanitizer_syscalls_netbsd.inc | 22 +- compiler-rt/utils/generate_netbsd_syscalls.awk | 18 +- lld/test/COFF/Inputs/undefined-symbol-lto-a.ll | 4 +- lld/test/COFF/Inputs/undefined-symbol-lto-b.ll | 2 +- lld/test/COFF/lto-cpu-string.ll | 2 +- lld/test/ELF/lto/cpu-string.ll | 2 +- lld/test/wasm/Inputs/debuginfo1.ll | 6 +- lld/test/wasm/Inputs/debuginfo2.ll | 2 +- lld/test/wasm/debug-removed-fn.ll | 2 +- .../test/functionalities/dead-strip/Makefile | 1 + .../Plugins/Process/NetBSD/NativeProcessNetBSD.cpp | 12 +- .../Plugins/Process/NetBSD/NativeThreadNetBSD.cpp | 11 + llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 163 +++++------ llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 19 +- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 58 ++++ llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 58 ++++ llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 93 +++++++ llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 165 +++++++++++ ...x9_mad_type_dev.rst => gfx900_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx900_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx900_src32_1.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx904_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx904_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx904_src32_1.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx906_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx906_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx906_src32_1.rst | 17 ++ llvm/docs/AMDGPU/gfx906_src32_2.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_addr_buf.rst | 22 ++ ...gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} | 10 +- ...gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst | 21 ++ ...d_type_dev.rst => gfx908_dst_flat_atomic32.rst} | 12 +- ...x9_mad_type_dev.rst => gfx908_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx908_offset_buf.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx908_opt.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_ret.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} | 10 +- llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 19 ++ llvm/docs/AMDGPU/gfx908_src32_0.rst | 17 ++ llvm/docs/AMDGPU/gfx908_src32_1.rst | 17 ++ llvm/docs/AMDGPU/gfx908_src32_2.rst | 17 ++ .../{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} | 9 +- llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 22 ++ ...{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPUModifierSyntax.rst | 55 +++- llvm/docs/AMDGPUOperandSyntax.rst | 60 ++++ llvm/docs/AMDGPUUsage.rst | 38 ++- llvm/docs/SourceLevelDebugging.rst | 2 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 26 ++ .../ExecutionEngine/ExecutionEngineBindings.cpp | 6 +- llvm/lib/Support/StringRef.cpp | 9 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 6 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 1 + llvm/lib/Target/X86/X86FixupSetCC.cpp | 18 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 23 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 186 +++++++------ llvm/lib/Target/X86/X86ISelLowering.h | 3 + llvm/lib/Target/X86/X86InstrAVX512.td | 82 +++--- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 25 +- llvm/lib/Target/X86/X86InstrSSE.td | 52 ++-- llvm/lib/Target/X86/X86WinEHState.cpp | 5 - llvm/lib/Transforms/IPO/Attributor.cpp | 125 ++++++++- .../test/Analysis/BranchProbabilityInfo/pr22718.ll | 6 +- .../CostModel/SystemZ/intrinsic-cost-crash.ll | 2 +- .../constant_functions_multi_dim.ll | 4 +- .../Analysis/DependenceAnalysis/MIVCheckConst.ll | 2 +- .../NonCanonicalizedSubscript.ll | 2 +- .../invariant.group-bug.ll | 4 +- llvm/test/Analysis/MemorySSA/pr28880.ll | 2 +- llvm/test/Analysis/MemorySSA/pr39197.ll | 2 +- llvm/test/Analysis/MemorySSA/pr40038.ll | 2 +- llvm/test/Analysis/ScalarEvolution/pr22674.ll | 2 +- .../ScalarEvolution/scev-canonical-mode.ll | 2 +- .../Analysis/TypeBasedAliasAnalysis/PR17620.ll | 4 +- .../Analysis/TypeBasedAliasAnalysis/tbaa-path.ll | 2 +- llvm/test/Bitcode/DILocation-implicit-code.ll | 4 +- llvm/test/Bitcode/drop-debug-info.3.5.ll | 2 +- llvm/test/Bitcode/upgrade-tbaa.ll | 2 +- llvm/test/BugPoint/func-attrs-keyval.ll | 2 +- llvm/test/BugPoint/func-attrs.ll | 4 +- .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 2 +- .../CodeGen/AArch64/GlobalISel/inline-memmove.mir | 2 +- .../CodeGen/AArch64/GlobalISel/inline-memset.mir | 2 +- .../aarch64-2014-08-11-MachineCombinerCrash.ll | 2 +- .../AArch64/aarch64-a57-fp-load-balancing.ll | 4 +- .../AArch64/aarch64-fix-cortex-a53-835769.ll | 4 +- .../CodeGen/AArch64/aarch64-mov-debug-locs.mir | 4 +- .../test/CodeGen/AArch64/arm64-detect-vec-redux.ll | 2 +- .../AArch64/arm64-fma-combine-with-fpfusion.ll | 2 +- .../CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll | 2 +- .../CodeGen/AArch64/arm64-misched-basic-A53.ll | 2 +- .../CodeGen/AArch64/arm64-misched-basic-A57.ll | 2 +- llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll | 4 +- .../AArch64/arm64-triv-disjoint-mem-access.ll | 2 +- .../CodeGen/AArch64/branch-relax-block-size.mir | 2 +- llvm/test/CodeGen/AArch64/consthoist-gep.ll | 2 +- llvm/test/CodeGen/AArch64/cxx-tlscc.ll | 2 +- .../test/CodeGen/AArch64/dag-combine-invaraints.ll | 4 +- llvm/test/CodeGen/AArch64/large-stack.ll | 2 +- .../AArch64/loopvectorize_pr33804_double.ll | 2 +- .../CodeGen/AArch64/machine-outliner-all-stack.mir | 2 +- .../machine-outliner-compatible-candidates.mir | 2 +- .../AArch64/machine-outliner-drop-stack.mir | 2 +- .../CodeGen/AArch64/machine-outliner-regsave.mir | 2 +- .../CodeGen/AArch64/machine-outliner-remarks.ll | 2 +- .../machine-outliner-retaddr-sign-regsave.mir | 2 +- .../machine-outliner-retaddr-sign-sp-mod.mir | 2 +- .../CodeGen/AArch64/machine-outliner-size-info.mir | 2 +- .../AArch64/machine-outliner-unsafe-stack-call.mir | 2 +- llvm/test/CodeGen/AArch64/machine-outliner.mir | 2 +- llvm/test/CodeGen/AArch64/preferred-alignment.ll | 4 +- .../test/CodeGen/AArch64/sched-past-vector-ldst.ll | 2 +- llvm/test/CodeGen/AArch64/stack_guard_remat.ll | 2 +- .../test/CodeGen/AArch64/vector_merge_dep_check.ll | 2 +- llvm/test/CodeGen/AArch64/win64_vararg.ll | 2 +- llvm/test/CodeGen/AArch64/wineh-frame5.mir | 4 +- llvm/test/CodeGen/AArch64/wineh-frame6.mir | 4 +- llvm/test/CodeGen/AArch64/wineh-frame7.mir | 4 +- llvm/test/CodeGen/AArch64/wineh-frame8.mir | 2 +- llvm/test/CodeGen/AArch64/wineh5.mir | 4 +- llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir | 4 +- .../CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir | 2 +- llvm/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | 2 +- llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll | 2 +- llvm/test/CodeGen/ARM/2010-12-07-PEIBug.ll | 2 +- llvm/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll | 2 +- llvm/test/CodeGen/ARM/2014-05-14-DwarfEHCrash.ll | 2 +- .../CodeGen/ARM/2016-05-01-RegScavengerAssert.ll | 2 +- llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir | 4 +- llvm/test/CodeGen/ARM/Windows/wineh-basic.ll | 4 +- llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll | 24 +- llvm/test/CodeGen/ARM/arm-storebytesmerge.ll | 2 +- llvm/test/CodeGen/ARM/byval_load_align.ll | 4 +- llvm/test/CodeGen/ARM/call-tc.ll | 20 +- llvm/test/CodeGen/ARM/cfguard-module-flag.ll | 2 +- llvm/test/CodeGen/ARM/clang-section.ll | 8 +- llvm/test/CodeGen/ARM/coalesce-dbgvalue.ll | 4 +- llvm/test/CodeGen/ARM/constantpool-promote-dbg.ll | 2 +- llvm/test/CodeGen/ARM/constantpool-promote.ll | 4 +- llvm/test/CodeGen/ARM/cxx-tlscc.ll | 14 +- llvm/test/CodeGen/ARM/debug-info-arg.ll | 2 +- llvm/test/CodeGen/ARM/disable-fp-elim.ll | 4 +- llvm/test/CodeGen/ARM/dwarf-unwind.ll | 2 +- llvm/test/CodeGen/ARM/early-cfi-sections.ll | 2 +- llvm/test/CodeGen/ARM/global-merge-1.ll | 6 +- llvm/test/CodeGen/ARM/hello.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt10.ll | 2 +- llvm/test/CodeGen/ARM/ifcvt5.ll | 4 +- llvm/test/CodeGen/ARM/insn-sched1.ll | 2 +- llvm/test/CodeGen/ARM/isel-v8i32-crash.ll | 2 +- llvm/test/CodeGen/ARM/ldrd.ll | 18 +- llvm/test/CodeGen/ARM/loopvectorize_pr33804.ll | 2 +- llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll | 2 +- llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll | 4 +- llvm/test/CodeGen/ARM/memfunc.ll | 18 +- llvm/test/CodeGen/ARM/noreturn.ll | 10 +- llvm/test/CodeGen/ARM/out-of-registers.ll | 2 +- llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir | 4 +- .../CodeGen/ARM/stack-protector-bmovpcb_call.ll | 4 +- llvm/test/CodeGen/ARM/stack-size-section.ll | 2 +- llvm/test/CodeGen/ARM/stack_guard_remat.ll | 2 +- llvm/test/CodeGen/ARM/struct-byval-frame-index.ll | 2 +- llvm/test/CodeGen/ARM/swiftself.ll | 12 +- llvm/test/CodeGen/ARM/unschedule-first-call.ll | 2 +- llvm/test/CodeGen/ARM/urem-opt-size.ll | 2 +- llvm/test/CodeGen/ARM/v7k-abi-align.ll | 22 +- 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| 2 +- .../CodeGen/BPF/BTF/static-var-zerolen-array.ll | 2 +- llvm/test/CodeGen/BPF/BTF/static-var.ll | 2 +- llvm/test/CodeGen/BPF/CORE/intrinsic-array.ll | 4 +- llvm/test/CodeGen/BPF/CORE/intrinsic-struct.ll | 4 +- llvm/test/CodeGen/BPF/CORE/intrinsic-union.ll | 4 +- llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll | 2 +- .../CodeGen/BPF/CORE/offset-reloc-multilevel.ll | 2 +- .../BPF/CORE/offset-reloc-struct-anonymous.ll | 2 +- .../CodeGen/BPF/CORE/offset-reloc-struct-array.ll | 2 +- llvm/test/CodeGen/BPF/CORE/offset-reloc-union.ll | 2 +- llvm/test/CodeGen/BPF/dwarfdump.ll | 2 +- llvm/test/CodeGen/BPF/objdump_two_funcs.ll | 2 +- llvm/test/CodeGen/BPF/reloc-btf-2.ll | 2 +- llvm/test/CodeGen/BPF/reloc-btf.ll | 2 +- llvm/test/CodeGen/BPF/warn-stack.ll | 4 +- llvm/test/CodeGen/BPF/xadd.ll | 2 +- llvm/test/CodeGen/Generic/DbgValueAggregate.ll | 2 +- llvm/test/CodeGen/Generic/cfi-sections.ll | 4 +- llvm/test/CodeGen/Hexagon/NVJumpCmp.ll | 2 +- llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll | 2 +- llvm/test/CodeGen/Hexagon/alu64.ll | 2 +- llvm/test/CodeGen/Hexagon/base-offset-addr.ll | 2 +- llvm/test/CodeGen/Hexagon/base-offset-post.ll | 2 +- llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll | 4 +- llvm/test/CodeGen/Hexagon/builtin-prefetch.ll | 2 +- llvm/test/CodeGen/Hexagon/cfi-offset.ll | 2 +- llvm/test/CodeGen/Hexagon/cmp-extend.ll | 2 +- llvm/test/CodeGen/Hexagon/cmp.ll | 2 +- llvm/test/CodeGen/Hexagon/constp-combine-neg.ll | 2 +- llvm/test/CodeGen/Hexagon/constp-extract.ll | 2 +- llvm/test/CodeGen/Hexagon/constp-physreg.ll | 2 +- llvm/test/CodeGen/Hexagon/dead-store-stack.ll | 4 +- llvm/test/CodeGen/Hexagon/dealloc_return.ll | 2 +- .../CodeGen/Hexagon/early-if-conversion-bug1.ll | 4 +- llvm/test/CodeGen/Hexagon/ehabi.ll | 2 +- llvm/test/CodeGen/Hexagon/fminmax.ll | 2 +- llvm/test/CodeGen/Hexagon/fpelim-basic.ll | 4 +- llvm/test/CodeGen/Hexagon/hasfp-crash1.ll | 2 +- llvm/test/CodeGen/Hexagon/hasfp-crash2.ll | 2 +- .../Hexagon/hexagon_vector_loop_carried_reuse.ll | 2 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llvm/test/CodeGen/Hexagon/swp-epilog-phi10.ll | 2 +- llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll | 2 +- llvm/test/CodeGen/Hexagon/swp-stages4.ll | 2 +- llvm/test/CodeGen/Hexagon/usr-ovf-dep.ll | 2 +- llvm/test/CodeGen/Hexagon/v60Intrins.ll | 2 +- llvm/test/CodeGen/Hexagon/v60small.ll | 2 +- llvm/test/CodeGen/Hexagon/v6vec-vprint.ll | 2 +- llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll | 4 +- llvm/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll | 4 +- llvm/test/CodeGen/Hexagon/vect/vect-extract.ll | 2 +- llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll | 2 +- llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll | 2 +- llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll | 2 +- llvm/test/CodeGen/Hexagon/vect/vect-xor.ll | 2 +- llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir | 2 +- llvm/test/CodeGen/MIR/X86/dead-register-flag.mir | 2 +- ...expected-metadata-node-after-debug-location.mir | 2 +- .../X86/expected-metadata-node-after-exclaim.mir | 2 +- .../MIR/X86/fixed-stack-memory-operands.mir | 2 +- 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100644 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_addr_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_dst_flat_atomic32.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_offset_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_opt.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_ret.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} (52%) rename llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} (52%) create mode 100644 llvm/test/Transforms/Attributor/undefined_behavior.ll delete mode 100644 llvm/test/tools/llvm-readobj/ELF/Inputs/relocs.obj.elf-x86_64 delete mode 100644 llvm/test/tools/llvm-readobj/ELF/Inputs/symbols-proc-specific.e [...] create mode 100644 llvm/test/tools/llvm-readobj/ELF/file-header-abi-version.test create mode 100644 llvm/test/tools/llvm-readobj/ELF/file-header-os-abi.test delete mode 100644 llvm/test/tools/llvm-readobj/ELF/gnu-symbols.test -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (f4c4ec68 -> 613cf43f)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards f4c4ec68 0: update: llvm-linux: 16 new 613cf43f 0: update: llvm-linux: 16 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f4c4ec68) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 70 +- 02-build_llvm/console.log | 12562 +++++++++++++++++------------------ 03-build_linux/console.log | 834 +-- 05-check_regression/console.log | 10 +- 06-update_baseline/console.log | 10 +- console.log | 13486 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 13490 insertions(+), 13490 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (29c4171e2d3 -> d5dcc0eb2ca)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from 29c4171e2d3 [C++] Make same_type_p return false for gnu_vector_type_p d [...] adds f8f558f90d9 Restrict 'c-c++-common/goacc/mdc-1.c' to LP64, LLP64 adds 149098b6ab7 Daily bump. adds 328b3b1eb27 PR go/93020 libgo: Hurd portability patches adds 0c6a3e049a4 rs6000: re-enable web and rnreg with -funroll-loops adds 675d15755fb Daily bump. adds d5dcc0eb2ca Define HAVE_ for math long double functions declared in vxw [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 5 + gcc/DATESTAMP | 2 +- gcc/config/rs6000/rs6000.c | 15 +- gcc/go/gofrontend/MERGE | 2 +- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/c-c++-common/goacc/mdc-1.c | 3 +- libgo/go/internal/poll/errno_unix.go | 2 +- libgo/go/os/export_unix_test.go | 2 +- libgo/go/runtime/os_hurd.go | 2 +- libgo/go/syscall/export_unix_test.go | 2 +- libstdc++-v3/ChangeLog | 7 + libstdc++-v3/configure | 1104 ++++++++++++++++++++++++++++++ libstdc++-v3/crossconfig.m4 | 62 ++ 13 files changed, 1201 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (e76ff63653 -> b68476f136)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from e76ff63653 Fix compilation of Readline on mingw.org's MinGW adds c71a963d8e Automatic date update in version.in adds ebd1c6d1d3 ubsan: arm: shift exponent 32 is too large for 32-bit type ' [...] adds b68476f136 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- opcodes/ChangeLog | 4 ++++ opcodes/arm-dis.c | 6 +++--- 3 files changed, 8 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (cc9616ce -> 166de17c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards cc9616ce 0: update: binutils-gcc-linux: all new 166de17c 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cc9616ce) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 10856 ++++++----- 04-build_abe-stage1/console.log | 16229 +++++++++-------- 05-build_linux/console.log | 7718 ++++---- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 35447 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 35409 insertions(+), 35463 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (29c4171e2d3 -> d5dcc0eb2ca)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/gcc. from 29c4171e2d3 [C++] Make same_type_p return false for gnu_vector_type_p d [...] adds f8f558f90d9 Restrict 'c-c++-common/goacc/mdc-1.c' to LP64, LLP64 adds 149098b6ab7 Daily bump. adds 328b3b1eb27 PR go/93020 libgo: Hurd portability patches adds 0c6a3e049a4 rs6000: re-enable web and rnreg with -funroll-loops adds 675d15755fb Daily bump. adds d5dcc0eb2ca Define HAVE_ for math long double functions declared in vxw [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 5 + gcc/DATESTAMP | 2 +- gcc/config/rs6000/rs6000.c | 15 +- gcc/go/gofrontend/MERGE | 2 +- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/c-c++-common/goacc/mdc-1.c | 3 +- libgo/go/internal/poll/errno_unix.go | 2 +- libgo/go/os/export_unix_test.go | 2 +- libgo/go/runtime/os_hurd.go | 2 +- libgo/go/syscall/export_unix_test.go | 2 +- libstdc++-v3/ChangeLog | 7 + libstdc++-v3/configure | 1104 ++++++++++++++++++++++++++++++ libstdc++-v3/crossconfig.m4 | 62 ++ 13 files changed, 1201 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 11 months

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