Tcwg-commits December 2019

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[gcc] branch aoliva/testme updated (ff3217f5878 -> 094f2af3d0e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch aoliva/testme in repository gcc. discards ff3217f5878 revamp dump and aux output names new 094f2af3d0e revamp dump and aux output names This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ff3217f5878) \ N -- N -- N refs/heads/aoliva/testme (094f2af3d0e) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/doc/invoke.texi | 49 +++++++++++-------------------------------------- 1 file changed, 11 insertions(+), 38 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig updated (1a2d2b492a3 -> 54c52242034)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig in repository toolchain/ci/llvm-project. from 1a2d2b492a3 [llvm-readobj] - Merge `gnu-symbols.test` to `symbols.test` [...] adds 80c45e49c33 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. adds aff6c9db9a9 [compiler-rt] [netbsd] Correct the fallback definition of P [...] adds ba1cdba4c48 [llvm-nm] Display STT_GNU_IFUNC as 'i' adds 2498d882598 [X86] Merge together some common code in LowerFP_TO_INT now [...] adds caf460d979a [lldb][NFC] Use StringRef in ClangASTContext::GetBuiltinTyp [...] adds 4af5b23db30 [X86FixupSetCC] Remember the preceding eflags defining inst [...] adds c5b4a2386b5 [X86] Use zero vector to extend to 512-bits for strict_fp_t [...] adds f9c3c5da19a [OpenMP][IR-Builder] Introduce the finalization stack adds 2e6c15d1e7a Make lazyload_metadata.ll resilient to the addition of new [...] adds e4add9727b4 [OpenMP][IR-Builder] Introduce "pragma omp parallel" code g [...] adds cb6e84fe368 test commit adds b082a2952f6 Revert "test commit" adds 472bded3eda [X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend adds 6cf6f7dc96d Revert "Make lazyload_metadata.ll resilient to the addition [...] adds 6d88b7d6e71 [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 adds d1f41b2ca99 [NFC][LoopFusion] Fix printing of the guard branch. Reviewe [...] adds e973783916d [NFC][PowerPC] Add a function tryAndWithMask to handle all [...] adds 6599d004679 [Bitstream] Delete skipAbbreviatedField which duplicates re [...] adds 1b57749a533 [PowerPC] stop folding if result rlwinm mask is wrap while [...] adds d2a8e14177f Fix the MLIR Vim syntax file: the keyword group was missing adds 073cdb23904 [clang][test] Minor fixes in testcase absolute-paths-symlinks.c adds b036f557cee [lldb] Remove some calls to GetASTContext adds 54c52242034 [compiler-rt] Disable QSORT interception on watchOS and tvOS. No new revisions were added by this update. Summary of changes: clang/lib/CodeGen/CGOpenMPRuntime.cpp | 66 +- clang/test/Frontend/absolute-paths-symlinks.c | 8 +- .../sanitizer_platform_interceptors.h | 15 +- .../sanitizer_platform_limits_netbsd.cpp | 4 +- lld/test/ELF/ppc64-ifunc.s | 4 +- lldb/include/lldb/Symbol/ClangASTContext.h | 6 +- .../Clang/ClangExpressionDeclMap.cpp | 25 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 4 +- .../source/Plugins/SymbolFile/PDB/PDBASTParser.cpp | 21 +- lldb/source/Symbol/ClangASTContext.cpp | 93 +- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 163 +-- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 19 +- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 58 + llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 58 + llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 93 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 165 +++ ...x9_mad_type_dev.rst => gfx900_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx900_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx900_src32_1.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx904_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx904_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx904_src32_1.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx906_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx906_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_2.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_addr_buf.rst | 22 + ...gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} | 10 +- ...gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst | 21 + ...d_type_dev.rst => gfx908_dst_flat_atomic32.rst} | 12 +- ...x9_mad_type_dev.rst => gfx908_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx908_offset_buf.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx908_opt.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_ret.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} | 10 +- llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 19 + llvm/docs/AMDGPU/gfx908_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_2.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} | 9 +- llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 22 + ...{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPUModifierSyntax.rst | 55 +- llvm/docs/AMDGPUOperandSyntax.rst | 60 + llvm/docs/AMDGPUUsage.rst | 38 +- llvm/include/llvm/Frontend/OpenMP/OMPConstants.h | 18 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 106 +- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 28 + llvm/lib/Bitstream/Reader/BitstreamReader.cpp | 38 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 15 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 336 ++++- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 231 ++-- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 2 + llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 + llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 8 +- llvm/lib/Target/X86/X86FixupSetCC.cpp | 32 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 171 ++- llvm/lib/Target/X86/X86ISelLowering.h | 1 + llvm/lib/Target/X86/X86InstrAVX512.td | 30 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 9 + llvm/lib/Target/X86/X86InstrSSE.td | 12 +- llvm/lib/Transforms/Scalar/LoopFuse.cpp | 7 +- llvm/test/CodeGen/PowerPC/CSR-fit.ll | 8 +- .../CodeGen/PowerPC/MCSE-caller-preserved-reg.ll | 2 +- llvm/test/CodeGen/PowerPC/csr-split.ll | 6 +- llvm/test/CodeGen/PowerPC/fold-rlwinm.mir | 15 + llvm/test/CodeGen/PowerPC/machine-pre.ll | 2 +- .../test/CodeGen/PowerPC/not-fixed-frame-object.ll | 2 +- .../PowerPC/ppcf128-constrained-fp-intrinsics.ll | 8 +- llvm/test/CodeGen/PowerPC/pr43527.ll | 2 +- llvm/test/CodeGen/PowerPC/pr44183.ll | 2 +- llvm/test/CodeGen/PowerPC/sjlj.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-1.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-3.ll | 2 +- llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll | 2 +- .../PowerPC/vector-constrained-fp-intrinsics.ll | 64 +- llvm/test/CodeGen/X86/fp-intrinsics.ll | 40 +- llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll | 1305 ++++++++++++++++++++ llvm/test/CodeGen/X86/fp80-strict-scalar.ll | 270 ++++ llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll | 3 +- llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll | 86 +- llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll | 646 ++++++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 421 +++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll | 390 ++++++ .../X86/vector-constrained-fp-intrinsics.ll | 342 +++-- llvm/test/LTO/Resolution/X86/ifunc.ll | 2 +- llvm/test/tools/llvm-nm/ifunc.test | 27 + llvm/tools/llvm-nm/llvm-nm.cpp | 13 +- llvm/unittests/Frontend/CMakeLists.txt | 1 + llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 324 ++++- mlir/utils/vim/syntax/mlir.vim | 6 +- 118 files changed, 5649 insertions(+), 966 deletions(-) create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_addr_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_dst_flat_atomic32.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_offset_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_opt.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_ret.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} (52%) rename llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} (52%) create mode 100644 llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll create mode 100644 llvm/test/tools/llvm-nm/ifunc.test -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig updated (4f21aa5a -> d561d2df)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards 4f21aa5a 0: update: llvm-linux: all new d561d2df 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4f21aa5a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-build_llvm/console.log | 12516 +++++++++++++++++------------------ 03-build_linux/console.log | 836 +-- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 13524 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13528 insertions(+), 13528 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (1a2d2b492a3 -> 54c52242034)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig in repository toolchain/ci/llvm-project. from 1a2d2b492a3 [llvm-readobj] - Merge `gnu-symbols.test` to `symbols.test` [...] adds 80c45e49c33 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. adds aff6c9db9a9 [compiler-rt] [netbsd] Correct the fallback definition of P [...] adds ba1cdba4c48 [llvm-nm] Display STT_GNU_IFUNC as 'i' adds 2498d882598 [X86] Merge together some common code in LowerFP_TO_INT now [...] adds caf460d979a [lldb][NFC] Use StringRef in ClangASTContext::GetBuiltinTyp [...] adds 4af5b23db30 [X86FixupSetCC] Remember the preceding eflags defining inst [...] adds c5b4a2386b5 [X86] Use zero vector to extend to 512-bits for strict_fp_t [...] adds f9c3c5da19a [OpenMP][IR-Builder] Introduce the finalization stack adds 2e6c15d1e7a Make lazyload_metadata.ll resilient to the addition of new [...] adds e4add9727b4 [OpenMP][IR-Builder] Introduce "pragma omp parallel" code g [...] adds cb6e84fe368 test commit adds b082a2952f6 Revert "test commit" adds 472bded3eda [X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend adds 6cf6f7dc96d Revert "Make lazyload_metadata.ll resilient to the addition [...] adds 6d88b7d6e71 [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 adds d1f41b2ca99 [NFC][LoopFusion] Fix printing of the guard branch. Reviewe [...] adds e973783916d [NFC][PowerPC] Add a function tryAndWithMask to handle all [...] adds 6599d004679 [Bitstream] Delete skipAbbreviatedField which duplicates re [...] adds 1b57749a533 [PowerPC] stop folding if result rlwinm mask is wrap while [...] adds d2a8e14177f Fix the MLIR Vim syntax file: the keyword group was missing adds 073cdb23904 [clang][test] Minor fixes in testcase absolute-paths-symlinks.c adds b036f557cee [lldb] Remove some calls to GetASTContext adds 54c52242034 [compiler-rt] Disable QSORT interception on watchOS and tvOS. No new revisions were added by this update. Summary of changes: clang/lib/CodeGen/CGOpenMPRuntime.cpp | 66 +- clang/test/Frontend/absolute-paths-symlinks.c | 8 +- .../sanitizer_platform_interceptors.h | 15 +- .../sanitizer_platform_limits_netbsd.cpp | 4 +- lld/test/ELF/ppc64-ifunc.s | 4 +- lldb/include/lldb/Symbol/ClangASTContext.h | 6 +- .../Clang/ClangExpressionDeclMap.cpp | 25 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 4 +- .../source/Plugins/SymbolFile/PDB/PDBASTParser.cpp | 21 +- lldb/source/Symbol/ClangASTContext.cpp | 93 +- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 163 +-- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 19 +- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 58 + llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 58 + llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 93 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 165 +++ ...x9_mad_type_dev.rst => gfx900_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx900_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx900_src32_1.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx904_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx904_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx904_src32_1.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx906_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx906_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_2.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_addr_buf.rst | 22 + ...gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} | 10 +- ...gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst | 21 + ...d_type_dev.rst => gfx908_dst_flat_atomic32.rst} | 12 +- ...x9_mad_type_dev.rst => gfx908_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx908_offset_buf.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx908_opt.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_ret.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} | 10 +- llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 19 + llvm/docs/AMDGPU/gfx908_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_2.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} | 9 +- llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 22 + ...{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPUModifierSyntax.rst | 55 +- llvm/docs/AMDGPUOperandSyntax.rst | 60 + llvm/docs/AMDGPUUsage.rst | 38 +- llvm/include/llvm/Frontend/OpenMP/OMPConstants.h | 18 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 106 +- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 28 + llvm/lib/Bitstream/Reader/BitstreamReader.cpp | 38 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 15 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 336 ++++- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 231 ++-- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 2 + llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 + llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 8 +- llvm/lib/Target/X86/X86FixupSetCC.cpp | 32 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 171 ++- llvm/lib/Target/X86/X86ISelLowering.h | 1 + llvm/lib/Target/X86/X86InstrAVX512.td | 30 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 9 + llvm/lib/Target/X86/X86InstrSSE.td | 12 +- llvm/lib/Transforms/Scalar/LoopFuse.cpp | 7 +- llvm/test/CodeGen/PowerPC/CSR-fit.ll | 8 +- .../CodeGen/PowerPC/MCSE-caller-preserved-reg.ll | 2 +- llvm/test/CodeGen/PowerPC/csr-split.ll | 6 +- llvm/test/CodeGen/PowerPC/fold-rlwinm.mir | 15 + llvm/test/CodeGen/PowerPC/machine-pre.ll | 2 +- .../test/CodeGen/PowerPC/not-fixed-frame-object.ll | 2 +- .../PowerPC/ppcf128-constrained-fp-intrinsics.ll | 8 +- llvm/test/CodeGen/PowerPC/pr43527.ll | 2 +- llvm/test/CodeGen/PowerPC/pr44183.ll | 2 +- llvm/test/CodeGen/PowerPC/sjlj.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-1.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-3.ll | 2 +- llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll | 2 +- .../PowerPC/vector-constrained-fp-intrinsics.ll | 64 +- llvm/test/CodeGen/X86/fp-intrinsics.ll | 40 +- llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll | 1305 ++++++++++++++++++++ llvm/test/CodeGen/X86/fp80-strict-scalar.ll | 270 ++++ llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll | 3 +- llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll | 86 +- llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll | 646 ++++++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 421 +++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll | 390 ++++++ .../X86/vector-constrained-fp-intrinsics.ll | 342 +++-- llvm/test/LTO/Resolution/X86/ifunc.ll | 2 +- llvm/test/tools/llvm-nm/ifunc.test | 27 + llvm/tools/llvm-nm/llvm-nm.cpp | 13 +- llvm/unittests/Frontend/CMakeLists.txt | 1 + llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 324 ++++- mlir/utils/vim/syntax/mlir.vim | 6 +- 118 files changed, 5649 insertions(+), 966 deletions(-) create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_addr_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_dst_flat_atomic32.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_offset_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_opt.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_ret.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} (52%) rename llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} (52%) create mode 100644 llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll create mode 100644 llvm/test/tools/llvm-nm/ifunc.test -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (29b52bbf -> 2fc0f994)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 29b52bbf 2: update: llvm-linux: all new 2fc0f994 2: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (29b52bbf) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-build_llvm/console.log | 12588 ++++++++-------- 03-build_linux/console.log | 17532 +++++++++++----------- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 90 +- console.log | 30282 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 30286 insertions(+), 30286 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (1a2d2b492a3 -> 54c52242034)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/llvm-project. from 1a2d2b492a3 [llvm-readobj] - Merge `gnu-symbols.test` to `symbols.test` [...] adds 80c45e49c33 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. adds aff6c9db9a9 [compiler-rt] [netbsd] Correct the fallback definition of P [...] adds ba1cdba4c48 [llvm-nm] Display STT_GNU_IFUNC as 'i' adds 2498d882598 [X86] Merge together some common code in LowerFP_TO_INT now [...] adds caf460d979a [lldb][NFC] Use StringRef in ClangASTContext::GetBuiltinTyp [...] adds 4af5b23db30 [X86FixupSetCC] Remember the preceding eflags defining inst [...] adds c5b4a2386b5 [X86] Use zero vector to extend to 512-bits for strict_fp_t [...] adds f9c3c5da19a [OpenMP][IR-Builder] Introduce the finalization stack adds 2e6c15d1e7a Make lazyload_metadata.ll resilient to the addition of new [...] adds e4add9727b4 [OpenMP][IR-Builder] Introduce "pragma omp parallel" code g [...] adds cb6e84fe368 test commit adds b082a2952f6 Revert "test commit" adds 472bded3eda [X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend adds 6cf6f7dc96d Revert "Make lazyload_metadata.ll resilient to the addition [...] adds 6d88b7d6e71 [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 adds d1f41b2ca99 [NFC][LoopFusion] Fix printing of the guard branch. Reviewe [...] adds e973783916d [NFC][PowerPC] Add a function tryAndWithMask to handle all [...] adds 6599d004679 [Bitstream] Delete skipAbbreviatedField which duplicates re [...] adds 1b57749a533 [PowerPC] stop folding if result rlwinm mask is wrap while [...] adds d2a8e14177f Fix the MLIR Vim syntax file: the keyword group was missing adds 073cdb23904 [clang][test] Minor fixes in testcase absolute-paths-symlinks.c adds b036f557cee [lldb] Remove some calls to GetASTContext adds 54c52242034 [compiler-rt] Disable QSORT interception on watchOS and tvOS. No new revisions were added by this update. Summary of changes: clang/lib/CodeGen/CGOpenMPRuntime.cpp | 66 +- clang/test/Frontend/absolute-paths-symlinks.c | 8 +- .../sanitizer_platform_interceptors.h | 15 +- .../sanitizer_platform_limits_netbsd.cpp | 4 +- lld/test/ELF/ppc64-ifunc.s | 4 +- lldb/include/lldb/Symbol/ClangASTContext.h | 6 +- .../Clang/ClangExpressionDeclMap.cpp | 25 +- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 4 +- .../source/Plugins/SymbolFile/PDB/PDBASTParser.cpp | 21 +- lldb/source/Symbol/ClangASTContext.cpp | 93 +- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 163 +-- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 15 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 19 +- llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst | 58 + llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst | 58 + llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 93 ++ llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 165 +++ ...x9_mad_type_dev.rst => gfx900_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx900_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx900_src32_1.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx904_mad_type_dev.rst} | 2 +- ...ad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx904_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx904_src32_1.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} | 10 +- ...x9_mad_type_dev.rst => gfx906_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx906_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx906_src32_2.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_addr_buf.rst | 22 + ...gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} | 10 +- ...gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} | 10 +- llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst | 21 + ...d_type_dev.rst => gfx908_dst_flat_atomic32.rst} | 12 +- ...x9_mad_type_dev.rst => gfx908_mad_type_dev.rst} | 2 +- ...ype_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} | 9 +- ...9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} | 9 +- ...ad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} | 9 +- llvm/docs/AMDGPU/gfx908_offset_buf.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx908_opt.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_ret.rst} | 9 +- .../{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} | 10 +- llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 19 + llvm/docs/AMDGPU/gfx908_src32_0.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_1.rst | 17 + llvm/docs/AMDGPU/gfx908_src32_2.rst | 17 + .../{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} | 9 +- llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 22 + ...{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} | 10 +- ...{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} | 10 +- .../{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} | 10 +- llvm/docs/AMDGPUModifierSyntax.rst | 55 +- llvm/docs/AMDGPUOperandSyntax.rst | 60 + llvm/docs/AMDGPUUsage.rst | 38 +- llvm/include/llvm/Frontend/OpenMP/OMPConstants.h | 18 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 106 +- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 28 + llvm/lib/Bitstream/Reader/BitstreamReader.cpp | 38 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 15 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 336 ++++- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 231 ++-- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 2 + llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 + llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 8 +- llvm/lib/Target/X86/X86FixupSetCC.cpp | 32 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 171 ++- llvm/lib/Target/X86/X86ISelLowering.h | 1 + llvm/lib/Target/X86/X86InstrAVX512.td | 30 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 9 + llvm/lib/Target/X86/X86InstrSSE.td | 12 +- llvm/lib/Transforms/Scalar/LoopFuse.cpp | 7 +- llvm/test/CodeGen/PowerPC/CSR-fit.ll | 8 +- .../CodeGen/PowerPC/MCSE-caller-preserved-reg.ll | 2 +- llvm/test/CodeGen/PowerPC/csr-split.ll | 6 +- llvm/test/CodeGen/PowerPC/fold-rlwinm.mir | 15 + llvm/test/CodeGen/PowerPC/machine-pre.ll | 2 +- .../test/CodeGen/PowerPC/not-fixed-frame-object.ll | 2 +- .../PowerPC/ppcf128-constrained-fp-intrinsics.ll | 8 +- llvm/test/CodeGen/PowerPC/pr43527.ll | 2 +- llvm/test/CodeGen/PowerPC/pr44183.ll | 2 +- llvm/test/CodeGen/PowerPC/sjlj.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-1.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-3.ll | 2 +- llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll | 2 +- .../PowerPC/vector-constrained-fp-intrinsics.ll | 64 +- llvm/test/CodeGen/X86/fp-intrinsics.ll | 40 +- llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll | 1305 ++++++++++++++++++++ llvm/test/CodeGen/X86/fp80-strict-scalar.ll | 270 ++++ llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll | 3 +- llvm/test/CodeGen/X86/vec-strict-fptoint-512.ll | 86 +- llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll | 646 ++++++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll | 421 +++++++ llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll | 390 ++++++ .../X86/vector-constrained-fp-intrinsics.ll | 342 +++-- llvm/test/LTO/Resolution/X86/ifunc.ll | 2 +- llvm/test/tools/llvm-nm/ifunc.test | 27 + llvm/tools/llvm-nm/llvm-nm.cpp | 13 +- llvm/unittests/Frontend/CMakeLists.txt | 1 + llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp | 324 ++++- mlir/utils/vim/syntax/mlir.vim | 6 +- 118 files changed, 5649 insertions(+), 966 deletions(-) create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX900.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX904.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst create mode 100644 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx900_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx900_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx900_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx904_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx904_src32_1.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx904_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx906_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx906_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_type_dev.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vdst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx906_vsrc32_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_addr_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_adst512_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc1024_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc128_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_asrc512_0.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_data_buf_atomic32.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_dst_flat_atomic32.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mad_type_dev.rst} (94%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_dpp_sdwa_abs_neg.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_sdwa_sext.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_mod_vop3_abs_neg.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_offset_buf.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_opt.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_ret.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_rsrc_buf.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_0.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_1.rst create mode 100644 llvm/docs/AMDGPU/gfx908_src32_2.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_src32_3.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_type_dev.rst} (52%) create mode 100644 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vasrc64_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdata32_0.rst} (52%) copy llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vdst32_0.rst} (52%) rename llvm/docs/AMDGPU/{gfx9_mad_type_dev.rst => gfx908_vsrc32_0.rst} (52%) create mode 100644 llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll create mode 100644 llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll create mode 100644 llvm/test/tools/llvm-nm/ifunc.test -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (56a8e0af -> d3a55bb5)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/base-artifacts. discards 56a8e0af 2: update: llvm-linux: 18309 new d3a55bb5 2: update: llvm-linux: 18309 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (56a8e0af) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-n [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 198 +- 02-build_llvm/console.log | 12518 +++++++++++++++++----------------- 03-build_linux/console.log | 1240 ++-- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 6 +- console.log | 13964 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 13968 insertions(+), 13968 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allyesconfig updated (d5dcc0eb2ca -> f08a5e4b60a)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allyesconfig in repository toolchain/ci/gcc. from d5dcc0eb2ca Define HAVE_ for math long double functions declared in vxw [...] adds 972abb9944c Daily bump. adds f08a5e4b60a PR c++/92438 * parser.c (cp_parser_constructor_declarator [...] No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 7 +++++++ gcc/cp/parser.c | 17 ++++++++++++++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/ext/attrib61.C | 26 ++++++++++++++++++++++++++ 5 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ext/attrib61.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allyesconfig updated (b68476f136 -> 8ce18f9cdf)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allyesconfig in repository toolchain/ci/binutils-gdb. from b68476f136 Automatic date update in version.in adds 3142e908d0 Fix printing ULONGEST variables on x86-32 adds f096cbc296 Automatic date update in version.in adds f5311f2509 pe_bfd_read_buildid memory leak adds cef2097a87 Add profiling outputs to .gitignore adds e5af216040 asan: som: heap-buffer-overflow adds 6c2ca6c25d ubsan: v850: left shift cannot be represented in type 'int' adds 100b122fc1 ubsan: crx: index 5 out of bounds for type 'operand_desc const[5]' adds 8ce18f9cdf Avoid ubsan bug complaining about &p->field No new revisions were added by this update. Summary of changes: .gitignore | 3 ++ ChangeLog | 4 ++ bfd/ChangeLog | 21 ++++++++++ bfd/peicode.h | 2 + bfd/som.c | 100 ++++++++++++++++++++++++----------------------- bfd/version.h | 2 +- gdb/ChangeLog | 7 ++++ gdb/dwarf2read.c | 6 +-- ld/ChangeLog | 19 +++++++++ ld/emultempl/alphaelf.em | 2 +- ld/emultempl/mmo.em | 2 +- ld/emultempl/pe.em | 2 +- ld/emultempl/pep.em | 2 +- ld/emultempl/ppc32elf.em | 2 +- ld/emultempl/spuelf.em | 4 +- ld/ldelf.c | 6 +-- ld/ldlang.c | 30 +++++++------- opcodes/ChangeLog | 10 +++++ opcodes/crx-dis.c | 2 +- opcodes/v850-dis.c | 14 +++---- 20 files changed, 155 insertions(+), 85 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allyesconfig updated (1ff10020 -> 585ef2c0)

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