Tcwg-commits October 2019

tcwg-commits@lists.linaro.org

6 participants
13959 discussions

[gcc] branch gcc-9-branch updated (54b97aff264 -> 01b6b5c9099)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-9-branch in repository gcc. from 54b97aff264 Daily bump. new 01b6b5c9099 Avoid gimple body modifications while streaming. Backport [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 24 ++++++++++ gcc/gimple-streamer-out.c | 10 ++--- gcc/lto-streamer-out.c | 110 ++++++++++++++++++++++++---------------------- gcc/lto-streamer.h | 1 + gcc/lto/ChangeLog | 10 +++++ gcc/lto/lto.c | 7 +++ gcc/passes.c | 37 +++------------- gcc/tree-dfa.c | 10 ++--- gcc/tree-dfa.h | 2 +- gcc/tree-ssa-dse.c | 2 +- gcc/tree-ssa-math-opts.c | 2 +- 11 files changed, 120 insertions(+), 95 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (e1ad18eeeed -> 541ec0fe275)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from e1ad18eeeed PR target/85969 * config/avr/gen-avr-mmcu-specs.c (str_pr [...] adds 3c585034cfd Fix compilation with Clang adds 4badc652b89 Use implicitly-defined copy operations for test iterators adds 991edac437a PR c++/91581 - ICE in exception-specification of defaulted ctor. adds 71046993786 Daily bump. adds 9da6344fa93 Fix false dependence of scalar operation vrcp/vsqrt/vrsqrt/ [...] adds 541ec0fe275 Adjust predicates and constraints of scalar insns. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 64 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/i386.md | 67 +++---- gcc/config/i386/sse.md | 205 +++++++++++++++------ gcc/config/i386/subst.md | 4 +- gcc/testsuite/ChangeLog | 11 ++ gcc/testsuite/g++.dg/cpp0x/noexcept55.C | 8 + gcc/testsuite/gcc.target/i386/pr87007-4.c | 18 ++ gcc/testsuite/gcc.target/i386/pr87007-5.c | 18 ++ libstdc++-v3/ChangeLog | 13 ++ libstdc++-v3/include/bits/allocator.h | 4 +- .../20_util/allocator/requirements/constexpr.cc | 28 +++ libstdc++-v3/testsuite/util/testsuite_iterators.h | 89 ++++----- 13 files changed, 391 insertions(+), 140 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept55.C create mode 100644 gcc/testsuite/gcc.target/i386/pr87007-4.c create mode 100644 gcc/testsuite/gcc.target/i386/pr87007-5.c create mode 100644 libstdc++-v3/testsuite/20_util/allocator/requirements/constexpr.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (5c49f2cd78 -> 6f69abb049)

by git＠git.linaro.org

5 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig updated (c5a1cad8 -> 3fd0e9d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards c5a1cad8 0: update: binutils-gcc-linux: all new 3fd0e9d6 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c5a1cad8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 165 +- 02-prepare_abe/console.log | 240 +- 03-build_abe-binutils/console.log | 11645 +++++++------- 04-build_abe-stage1/console.log | 15506 +++++++++--------- 05-build_linux/console.log | 2590 ++-- 06-boot_linux/console.log | 6 +- console.log | 30160 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 8 files changed, 30186 insertions(+), 30138 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (de79836312e -> 82b82e39c45)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project. from de79836312e [FPEnv] Teach the IRBuilder about correct use of the strict [...] adds 5934cd11ea3 [TableGen] Add asserts to make sure default values match pr [...] adds 7a2b704bf0c [Sema][Typo Correction] Fix another infinite loop on ambiguity adds 4d18b4a7c4f [SCEV] Add a clarifying comment around ExitLimit construction adds 96601ec28b7 ValueObject: Fix a crash related to children address type c [...] adds 197b7b24c33 [NFC][libomptarget] move remaining device specific code out [...] adds 118ceea5c36 Crt files are special cased by name when dealing with ctor [...] adds c35b358b741 AMDGPU/GlobalISel: Legalize FDIV16 adds e6c145e0548 [DAGCombiner] widen zext of popcount based on target support adds 3dd0a896b64 [X86] Add a check for SSE2 to the top of combineReductionTo [...] adds 72105b9dcd6 Fix compilation error in ObjectFileMachO::ParseSymtab adds 0877dd14e4e [Driver] Force llvm to install its handlers before lldb's adds c9c18e5a319 [AMDGPU] Disallow dpp combining for dpp instructions withou [...] adds d4303b38616 [AMDGPU] Fold AGPR reg_sequence initializers adds 074af2daf5f [llvm-objcopy][MachO] Add support for min os version load commands adds 2724d9e1296 build: remove `LLVM_CXX_STD` extension point adds 3c7c3717932 [CVP] add test for poison propagation bug (PR43802); NFC adds a4783ef58d3 [Alignment][NFC] getMemoryOpCost uses MaybeAlign adds cc0b9647b76 [LLD][ThinLTO] Handle GUID collision in import global processing adds 64c1f6602a0 Revert "Add an instruction marker field to the ExtraInfo in [...] adds a6e1de4afc5 [gicombiner] Add parse failure tests for defs/match adds 1ce552f3ef8 AMDGPU: Fix the broken dominator tree when creating waterfa [...] adds 171cf5302f4 AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG adds 03de2f84fc4 [ARM] Uses "Sun Style" syntax for section switching adds e8a0a0904b2 [Alignment][NFC] Convert AllocaInst to MaybeAlign adds 1a276d1e8c5 GlobalISel: Implement widenScalar for G_INSERT_VECTOR_ELT adds c7dcacf16a6 [AMDGPU] Fixed asan failure in SIFoldOperands adds a6b0219fc4a Revert "[ARM] Uses "Sun Style" syntax for section switching" adds 738af7a6241 Add the ability to pass extra args to a Python breakpoi [...] adds 0e4d4153115 Update version number in llvm python bindings adds e070cf81196 [x86] add tests for extractelement with undef index (PR42689); NFC adds a27c998c006 [BPF] fix a CO-RE issue with -mattr=+alu32 adds 7913126a08e [globalisel] Add LLVMDev 2019 talks and links for the 2017 talks adds 27887bc1e7a [globalisel] Fix typo in 'Add LLVMDev 2019 talks and links [...] adds 4c0251da149 [AMDGPU] Enable SGPR copy folding adds 73a7a55c0ec lldb/COFF: Create a separate "section" for the file header adds 27fdf8a29d1 [lit] Don't fail when printing test output with special chars adds 7c603a41e20 lldb/minidump: Refactor memory region computation code adds 8da20560ab0 [clang][DependencyScanning] 80-col. adds 10b5cd8ed52 [LLDB] Fix inline variable only used in assertion. (NFC) adds feab0334f57 [globalisel] Restructure the GlobalISel documentation adds 6c89392592c Use __builtin_strlen in constexpr StringRef ctor with MSVC adds 5a3c657f3e8 Fix after 738af7a6241c98164625b9cd1ba9f8af4e36f197 adds a88591cff46 [libFuzzer] Enable extra counters for Fuchsia. adds f3ad8ae7b73 [lit] Move sharding logic into separate function adds 4c47617627f [SDAG] fold extract_vector_elt with undef index adds dd501045cde [Clang][Bundler] Error reporting improvements adds 27e2c8faec6 Add Record::getValueAsOptionalDef(). adds baf91d02da6 [NFC] Add a tablegen node for the root of the AST node hier [...] adds 93b29d3882b Revert "[Clang][Bundler] Error reporting improvements" adds 4141bb50a87 [ORC] Avoid SymbolStringPtr copies in DynamicLibrarySearchG [...] adds edb1a1de1b7 Reland "[Clang][Bundler] Error reporting improvements" adds a6a37e820cf [X86][GISel] Fix typo in comment. NFC adds 5e307808557 Correct size_t format specifier adds e921ede5406 [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. adds 05a9e344ee3 [YAMLTraits] - Revert a change committed by a mistake in D68983 adds 073ab70b72f [ObjectYAML] - Do not use auto. NFC. adds 9231e443445 fix lldb build with -DLLVM_ENABLE_MODULES=On (missing #include) adds 82b82e39c45 Add all the issues to be voted upon in Belfast No new revisions were added by this update. Summary of changes: clang/include/clang/Basic/CommentNodes.td | 38 +- clang/include/clang/Basic/DeclNodes.td | 184 ++-- clang/include/clang/Basic/StmtNodes.td | 440 +++++----- clang/include/clang/Basic/TypeNodes.td | 114 ++- .../DependencyScanning/DependencyScanningTool.h | 9 +- clang/lib/Sema/SemaExprCXX.cpp | 5 +- .../DependencyScanning/DependencyScanningTool.cpp | 8 +- clang/test/Driver/clang-offload-bundler.c | 32 +- clang/test/Sema/typo-correction-ambiguity.c | 14 + .../clang-offload-bundler/ClangOffloadBundler.cpp | 409 ++++----- clang/utils/TableGen/ClangASTEmitters.h | 39 + clang/utils/TableGen/ClangASTNodesEmitter.cpp | 119 +-- clang/utils/TableGen/ClangAttrEmitter.cpp | 14 +- clang/utils/TableGen/ClangTypeNodesEmitter.cpp | 24 +- clang/utils/TableGen/TableGen.cpp | 7 +- compiler-rt/lib/fuzzer/FuzzerExtraCounters.cpp | 2 +- libcxx/www/upcoming_meeting.html | 97 ++- lld/ELF/OutputSections.cpp | 26 +- lld/test/ELF/ctors_dtors_priority.s | 18 +- lldb/include/lldb/API/SBBreakpoint.h | 3 + lldb/include/lldb/API/SBBreakpointLocation.h | 7 +- lldb/include/lldb/API/SBBreakpointName.h | 7 +- lldb/include/lldb/API/SBStructuredData.h | 3 + lldb/include/lldb/Core/PropertiesBase.td | 2 + lldb/include/lldb/Core/ValueObject.h | 1 + .../include/lldb/Expression/ExpressionSourceCode.h | 1 + .../Interpreter/OptionGroupPythonClassWithDict.h | 20 +- lldb/include/lldb/Interpreter/ScriptInterpreter.h | 31 +- lldb/include/lldb/Target/MemoryRegionInfo.h | 30 +- .../breakpoint_command/TestBreakpointCommand.py | 8 +- .../TestBreakpointCommandsFromPython.py | 83 +- .../breakpoint/breakpoint_command/bktptcmd.py | 18 + lldb/scripts/Python/python-wrapper.swig | 17 +- lldb/scripts/interface/SBBreakpoint.i | 8 + lldb/scripts/interface/SBBreakpointLocation.i | 11 +- lldb/scripts/interface/SBBreakpointName.i | 4 + lldb/source/API/SBBreakpoint.cpp | 34 +- lldb/source/API/SBBreakpointLocation.cpp | 31 +- lldb/source/API/SBBreakpointName.cpp | 37 +- lldb/source/Commands/CommandObjectBreakpoint.cpp | 8 +- .../Commands/CommandObjectBreakpointCommand.cpp | 48 +- lldb/source/Commands/CommandObjectThread.cpp | 12 +- lldb/source/Commands/Options.td | 7 - lldb/source/Core/ValueObject.cpp | 53 ++ lldb/source/Core/ValueObjectVariable.cpp | 45 - .../Interpreter/OptionGroupPythonClassWithDict.cpp | 61 +- lldb/source/Interpreter/ScriptInterpreter.cpp | 12 +- .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 7 +- .../Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp | 25 +- .../Plugins/Process/minidump/MinidumpParser.cpp | 72 +- .../Plugins/Process/minidump/MinidumpParser.h | 10 +- .../Plugins/Process/minidump/ProcessMinidump.cpp | 41 +- .../Plugins/Process/minidump/ProcessMinidump.h | 3 + .../Python/ScriptInterpreterPython.cpp | 105 ++- .../Python/ScriptInterpreterPython.h | 8 + .../Python/ScriptInterpreterPythonImpl.h | 22 +- lldb/source/Target/CMakeLists.txt | 1 + lldb/source/Target/MemoryRegionInfo.cpp | 20 + lldb/test/Shell/Minidump/memory-region.yaml | 49 ++ .../Shell/ObjectFile/PECOFF/export-dllfunc.yaml | 10 +- .../PECOFF/{subsections.yaml => sections.yaml} | 48 +- .../Shell/SymbolFile/DWARF/DW_OP_piece-struct.s | 113 +++ lldb/tools/driver/Driver.cpp | 19 + .../Process/minidump/MinidumpParserTest.cpp | 163 ++-- .../ScriptInterpreter/Python/PythonTestSuite.cpp | 3 +- lldb/utils/TableGen/LLDBPropertyDefEmitter.cpp | 15 + llvm/CMakeLists.txt | 4 + llvm/bindings/python/llvm/common.py | 4 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 28 - llvm/docs/CMake.rst | 14 +- llvm/docs/FuzzingLLVM.rst | 2 +- llvm/docs/GlobalISel.rst | 940 --------------------- llvm/docs/GlobalISel/GMIR.rst | 158 ++++ llvm/docs/GlobalISel/IRTranslator.rst | 57 ++ llvm/docs/GlobalISel/InstructionSelect.rst | 98 +++ llvm/docs/GlobalISel/Legalizer.rst | 351 ++++++++ llvm/docs/GlobalISel/Pipeline.rst | 82 ++ llvm/docs/GlobalISel/Porting.rst | 21 + llvm/docs/GlobalISel/RegBankSelect.rst | 73 ++ llvm/docs/GlobalISel/Resources.rst | 11 + llvm/docs/GlobalISel/index.rst | 94 +++ llvm/docs/Reference.rst | 6 +- llvm/include/llvm/ADT/StringRef.h | 8 +- llvm/include/llvm/Analysis/ScalarEvolution.h | 3 + llvm/include/llvm/Analysis/TargetTransformInfo.h | 9 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 2 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 9 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 10 +- llvm/include/llvm/CodeGen/MachineFunction.h | 19 +- llvm/include/llvm/CodeGen/MachineInstr.h | 62 +- .../llvm/ExecutionEngine/Orc/ExecutionUtils.h | 2 +- llvm/include/llvm/IR/Instructions.h | 4 +- llvm/include/llvm/Support/YAMLTraits.h | 3 +- llvm/include/llvm/TableGen/Record.h | 6 + llvm/lib/Analysis/TargetTransformInfo.cpp | 10 +- llvm/lib/AsmParser/LLParser.cpp | 3 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 16 +- llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 32 +- llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h | 2 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 25 + llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 5 +- llvm/lib/CodeGen/MachineFunction.cpp | 20 +- llvm/lib/CodeGen/MachineInstr.cpp | 146 ++-- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 + llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 7 +- .../CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +- llvm/lib/CodeGen/SjLjEHPrepare.cpp | 6 +- llvm/lib/IR/Instructions.cpp | 27 +- llvm/lib/ObjectYAML/ELFEmitter.cpp | 2 +- llvm/lib/TableGen/Record.cpp | 15 + .../Target/AArch64/AArch64TargetTransformInfo.cpp | 8 +- .../Target/AArch64/AArch64TargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 2 + llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 15 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 78 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 5 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 3 +- llvm/lib/Target/AMDGPU/FLATInstructions.td | 85 +- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 3 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 161 +++- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 - llvm/lib/Target/AMDGPU/SIISelLowering.h | 8 + llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 28 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 11 + llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 179 ++-- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 8 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 +- llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp | 15 +- .../Target/Hexagon/HexagonTargetTransformInfo.cpp | 31 +- .../Target/Hexagon/HexagonTargetTransformInfo.h | 5 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 11 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 2 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 4 +- .../Target/SystemZ/SystemZTargetTransformInfo.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 + llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 21 +- llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 5 +- llvm/lib/Transforms/Scalar/SROA.cpp | 21 +- llvm/lib/Transforms/Utils/FunctionImportUtils.cpp | 16 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 10 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 14 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 4 +- .../inst-select-amdgpu-atomic-cmpxchg-flat.mir | 374 ++++++++ .../legalize-atomic-cmpxchg-with-success.mir | 21 +- .../AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir | 96 ++- ...lize-fast-unsafe-fdiv.mir => legalize-fdiv.mir} | 468 +++++++--- .../GlobalISel/legalize-insert-vector-elt.mir | 48 ++ llvm/test/CodeGen/AMDGPU/dpp_combine.mir | 16 + llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir | 48 ++ .../AMDGPU/i1_copy_phi_with_phi_incoming_value.mir | 140 +++ .../CodeGen/AMDGPU/indirect-addressing-si-noopt.ll | 4 - llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 368 +++++++- .../vgpr-descriptor-waterfall-loop-idom-update.ll | 48 ++ llvm/test/CodeGen/BPF/CORE/field-reloc-alu32.ll | 73 ++ llvm/test/CodeGen/BPF/CORE/intrinsic-array.ll | 1 + .../BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll | 12 +- .../BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-existence-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-existence-2.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-existence-3.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-lshift-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-lshift-2.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-rshift-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-rshift-2.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-rshift-3.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-signedness-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-signedness-2.ll | 12 +- .../BPF/CORE/intrinsic-fieldinfo-signedness-3.ll | 9 +- llvm/test/CodeGen/BPF/CORE/intrinsic-struct.ll | 1 + llvm/test/CodeGen/BPF/CORE/intrinsic-union.ll | 1 + .../CodeGen/BPF/CORE/offset-reloc-access-str.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-array-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-array-2.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-struct-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-struct-2.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-struct-3.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-union-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-union-2.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-end-load.ll | 6 +- llvm/test/CodeGen/BPF/CORE/offset-reloc-end-ret.ll | 3 +- .../CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll | 1 + .../CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-global-1.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-global-2.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-global-3.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-ignore.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-middle-chain.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-multi-array-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-multi-array-2.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-multilevel.ll | 6 +- .../CodeGen/BPF/CORE/offset-reloc-pointer-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-pointer-2.ll | 2 + .../BPF/CORE/offset-reloc-struct-anonymous.ll | 8 +- .../CodeGen/BPF/CORE/offset-reloc-struct-array.ll | 6 +- .../CodeGen/BPF/CORE/offset-reloc-typedef-array.ll | 2 + .../BPF/CORE/offset-reloc-typedef-struct.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-typedef-union.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-typedef.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-union.ll | 6 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 15 +- llvm/test/CodeGen/WebAssembly/simd.ll | 32 +- llvm/test/CodeGen/X86/extractelement-index.ll | 24 + llvm/test/CodeGen/X86/label-heapallocsite.ll | 43 +- llvm/test/CodeGen/X86/taildup-heapallocsite.ll | 21 +- .../TableGen/GICombinerEmitter/defs-invalid.td | 42 + .../TableGen/GICombinerEmitter/match-invalid.td | 71 ++ llvm/test/ThinLTO/X86/Inputs/guid_collision.ll | 12 + llvm/test/ThinLTO/X86/guid_collision.ll | 17 + .../CorrelatedValuePropagation/phi-common-val.ll | 27 + .../MachO/Inputs/min_iphoneos_version_lc.yaml | 15 + .../MachO/Inputs/min_macos_version_lc.yaml | 15 + .../MachO/Inputs/min_tvos_version_lc.yaml | 15 + .../MachO/Inputs/min_watchos_version_lc.yaml | 15 + .../MachO/min-version-load-commands.test | 20 + .../llvm-objcopy/MachO/MachOLayoutBuilder.cpp | 3 + llvm/unittests/CodeGen/MachineInstrTest.cpp | 144 ---- llvm/utils/TableGen/GICombinerEmitter.cpp | 3 + llvm/utils/lit/lit/cl_arguments.py | 3 + llvm/utils/lit/lit/display.py | 15 +- llvm/utils/lit/lit/main.py | 51 +- llvm/utils/lit/lit/run.py | 3 + llvm/utils/lit/lit/util.py | 2 + .../tests/Inputs/shtest-shell/stdout-encoding.txt | 7 + llvm/utils/lit/tests/max-failures.py | 2 +- llvm/utils/lit/tests/shtest-shell.py | 14 +- .../deviceRTLs/nvptx/src/omptarget-nvptx.h | 22 +- .../deviceRTLs/nvptx/src/target_impl.h | 15 + 233 files changed, 5595 insertions(+), 3155 deletions(-) create mode 100644 clang/test/Sema/typo-correction-ambiguity.c create mode 100644 clang/utils/TableGen/ClangASTEmitters.h create mode 100644 lldb/source/Target/MemoryRegionInfo.cpp create mode 100644 lldb/test/Shell/Minidump/memory-region.yaml rename lldb/test/Shell/ObjectFile/PECOFF/{subsections.yaml => sections.yaml} (65%) create mode 100644 lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-struct.s delete mode 100644 llvm/docs/GlobalISel.rst create mode 100644 llvm/docs/GlobalISel/GMIR.rst create mode 100644 llvm/docs/GlobalISel/IRTranslator.rst create mode 100644 llvm/docs/GlobalISel/InstructionSelect.rst create mode 100644 llvm/docs/GlobalISel/Legalizer.rst create mode 100644 llvm/docs/GlobalISel/Pipeline.rst create mode 100644 llvm/docs/GlobalISel/Porting.rst create mode 100644 llvm/docs/GlobalISel/RegBankSelect.rst create mode 100644 llvm/docs/GlobalISel/Resources.rst create mode 100644 llvm/docs/GlobalISel/index.rst create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-c [...] rename llvm/test/CodeGen/AMDGPU/GlobalISel/{legalize-fast-unsafe-fdiv.mir => legal [...] create mode 100644 llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir create mode 100644 llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir create mode 100644 llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/field-reloc-alu32.ll create mode 100644 llvm/test/TableGen/GICombinerEmitter/defs-invalid.td create mode 100644 llvm/test/TableGen/GICombinerEmitter/match-invalid.td create mode 100644 llvm/test/ThinLTO/X86/Inputs/guid_collision.ll create mode 100644 llvm/test/ThinLTO/X86/guid_collision.ll create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_iphoneos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_macos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_tvos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_watchos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/min-version-load-commands.test create mode 100644 llvm/utils/lit/tests/Inputs/shtest-shell/stdout-encoding.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (d29f622a -> a475e922)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards d29f622a 0: update: llvm-linux: 16 new a475e922 0: update: llvm-linux: 16 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d29f622a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 52 +- 02-build_llvm/console.log | 13194 ++++++++++++++++++------------------ 03-build_linux/console.log | 840 +-- 06-update_baseline/console.log | 8 +- console.log | 14094 +++++++++++++++++++-------------------- jenkins/manifest.sh | 8 +- 6 files changed, 14092 insertions(+), 14104 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (e1ad18eeeed -> 541ec0fe275)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/gcc. from e1ad18eeeed PR target/85969 * config/avr/gen-avr-mmcu-specs.c (str_pr [...] adds 3c585034cfd Fix compilation with Clang adds 4badc652b89 Use implicitly-defined copy operations for test iterators adds 991edac437a PR c++/91581 - ICE in exception-specification of defaulted ctor. adds 71046993786 Daily bump. adds 9da6344fa93 Fix false dependence of scalar operation vrcp/vsqrt/vrsqrt/ [...] adds 541ec0fe275 Adjust predicates and constraints of scalar insns. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 64 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/i386.md | 67 +++---- gcc/config/i386/sse.md | 205 +++++++++++++++------ gcc/config/i386/subst.md | 4 +- gcc/testsuite/ChangeLog | 11 ++ gcc/testsuite/g++.dg/cpp0x/noexcept55.C | 8 + gcc/testsuite/gcc.target/i386/pr87007-4.c | 18 ++ gcc/testsuite/gcc.target/i386/pr87007-5.c | 18 ++ libstdc++-v3/ChangeLog | 13 ++ libstdc++-v3/include/bits/allocator.h | 4 +- .../20_util/allocator/requirements/constexpr.cc | 28 +++ libstdc++-v3/testsuite/util/testsuite_iterators.h | 89 ++++----- 13 files changed, 391 insertions(+), 140 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept55.C create mode 100644 gcc/testsuite/gcc.target/i386/pr87007-4.c create mode 100644 gcc/testsuite/gcc.target/i386/pr87007-5.c create mode 100644 libstdc++-v3/testsuite/20_util/allocator/requirements/constexpr.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (5c49f2cd78 -> 6f69abb049)

by git＠git.linaro.org

5 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (b130db47 -> 9548355f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards b130db47 0: update: binutils-gcc-linux: all new 9548355f 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b130db47) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 10345 ++++++----- 04-build_abe-stage1/console.log | 20140 +++++++++++----------- 05-build_linux/console.log | 2304 +-- 06-boot_linux/console.log | 2 +- console.log | 33446 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 8 files changed, 33441 insertions(+), 33412 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig updated (abd89c243a4 -> 82b82e39c45)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig in repository toolchain/ci/llvm-project. from abd89c243a4 build: reindent text (NFC) adds b85b4e5a6f8 Add an instruction marker field to the ExtraInfo in MachineInstrs. adds 8e567b0730f [clangd] Revert define-inline action changes to un-break wi [...] adds b74d7e5cccb [PowerPC] add test for popcnt with any_extend; NFC adds fd667b860e9 [libcxx] [test] Run `chmod +x` on executables when testing via SSH adds a153233caf6 gn build: Merge 8e567b0730f adds de79836312e [FPEnv] Teach the IRBuilder about correct use of the strict [...] adds 5934cd11ea3 [TableGen] Add asserts to make sure default values match pr [...] adds 7a2b704bf0c [Sema][Typo Correction] Fix another infinite loop on ambiguity adds 4d18b4a7c4f [SCEV] Add a clarifying comment around ExitLimit construction adds 96601ec28b7 ValueObject: Fix a crash related to children address type c [...] adds 197b7b24c33 [NFC][libomptarget] move remaining device specific code out [...] adds 118ceea5c36 Crt files are special cased by name when dealing with ctor [...] adds c35b358b741 AMDGPU/GlobalISel: Legalize FDIV16 adds e6c145e0548 [DAGCombiner] widen zext of popcount based on target support adds 3dd0a896b64 [X86] Add a check for SSE2 to the top of combineReductionTo [...] adds 72105b9dcd6 Fix compilation error in ObjectFileMachO::ParseSymtab adds 0877dd14e4e [Driver] Force llvm to install its handlers before lldb's adds c9c18e5a319 [AMDGPU] Disallow dpp combining for dpp instructions withou [...] adds d4303b38616 [AMDGPU] Fold AGPR reg_sequence initializers adds 074af2daf5f [llvm-objcopy][MachO] Add support for min os version load commands adds 2724d9e1296 build: remove `LLVM_CXX_STD` extension point adds 3c7c3717932 [CVP] add test for poison propagation bug (PR43802); NFC adds a4783ef58d3 [Alignment][NFC] getMemoryOpCost uses MaybeAlign adds cc0b9647b76 [LLD][ThinLTO] Handle GUID collision in import global processing adds 64c1f6602a0 Revert "Add an instruction marker field to the ExtraInfo in [...] adds a6e1de4afc5 [gicombiner] Add parse failure tests for defs/match adds 1ce552f3ef8 AMDGPU: Fix the broken dominator tree when creating waterfa [...] adds 171cf5302f4 AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG adds 03de2f84fc4 [ARM] Uses "Sun Style" syntax for section switching adds e8a0a0904b2 [Alignment][NFC] Convert AllocaInst to MaybeAlign adds 1a276d1e8c5 GlobalISel: Implement widenScalar for G_INSERT_VECTOR_ELT adds c7dcacf16a6 [AMDGPU] Fixed asan failure in SIFoldOperands adds a6b0219fc4a Revert "[ARM] Uses "Sun Style" syntax for section switching" adds 738af7a6241 Add the ability to pass extra args to a Python breakpoi [...] adds 0e4d4153115 Update version number in llvm python bindings adds e070cf81196 [x86] add tests for extractelement with undef index (PR42689); NFC adds a27c998c006 [BPF] fix a CO-RE issue with -mattr=+alu32 adds 7913126a08e [globalisel] Add LLVMDev 2019 talks and links for the 2017 talks adds 27887bc1e7a [globalisel] Fix typo in 'Add LLVMDev 2019 talks and links [...] adds 4c0251da149 [AMDGPU] Enable SGPR copy folding adds 73a7a55c0ec lldb/COFF: Create a separate "section" for the file header adds 27fdf8a29d1 [lit] Don't fail when printing test output with special chars adds 7c603a41e20 lldb/minidump: Refactor memory region computation code adds 8da20560ab0 [clang][DependencyScanning] 80-col. adds 10b5cd8ed52 [LLDB] Fix inline variable only used in assertion. (NFC) adds feab0334f57 [globalisel] Restructure the GlobalISel documentation adds 6c89392592c Use __builtin_strlen in constexpr StringRef ctor with MSVC adds 5a3c657f3e8 Fix after 738af7a6241c98164625b9cd1ba9f8af4e36f197 adds a88591cff46 [libFuzzer] Enable extra counters for Fuchsia. adds f3ad8ae7b73 [lit] Move sharding logic into separate function adds 4c47617627f [SDAG] fold extract_vector_elt with undef index adds dd501045cde [Clang][Bundler] Error reporting improvements adds 27e2c8faec6 Add Record::getValueAsOptionalDef(). adds baf91d02da6 [NFC] Add a tablegen node for the root of the AST node hier [...] adds 93b29d3882b Revert "[Clang][Bundler] Error reporting improvements" adds 4141bb50a87 [ORC] Avoid SymbolStringPtr copies in DynamicLibrarySearchG [...] adds edb1a1de1b7 Reland "[Clang][Bundler] Error reporting improvements" adds a6a37e820cf [X86][GISel] Fix typo in comment. NFC adds 5e307808557 Correct size_t format specifier adds e921ede5406 [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. adds 05a9e344ee3 [YAMLTraits] - Revert a change committed by a mistake in D68983 adds 073ab70b72f [ObjectYAML] - Do not use auto. NFC. adds 9231e443445 fix lldb build with -DLLVM_ENABLE_MODULES=On (missing #include) adds 82b82e39c45 Add all the issues to be voted upon in Belfast No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/ClangdServer.cpp | 2 +- clang-tools-extra/clangd/refactor/Tweak.cpp | 8 +- clang-tools-extra/clangd/refactor/Tweak.h | 6 +- .../clangd/refactor/tweaks/CMakeLists.txt | 1 - .../clangd/refactor/tweaks/DefineInline.cpp | 393 --------- .../clangd/unittests/TweakTesting.cpp | 44 +- clang-tools-extra/clangd/unittests/TweakTesting.h | 22 +- clang-tools-extra/clangd/unittests/TweakTests.cpp | 704 --------------- clang/include/clang/Basic/CommentNodes.td | 38 +- clang/include/clang/Basic/DeclNodes.td | 184 ++-- clang/include/clang/Basic/StmtNodes.td | 440 +++++----- clang/include/clang/Basic/TypeNodes.td | 114 ++- .../DependencyScanning/DependencyScanningTool.h | 9 +- clang/lib/Sema/SemaExprCXX.cpp | 5 +- .../DependencyScanning/DependencyScanningTool.cpp | 8 +- clang/test/Driver/clang-offload-bundler.c | 32 +- clang/test/Sema/typo-correction-ambiguity.c | 14 + .../clang-offload-bundler/ClangOffloadBundler.cpp | 409 ++++----- clang/utils/TableGen/ClangASTEmitters.h | 39 + clang/utils/TableGen/ClangASTNodesEmitter.cpp | 119 +-- clang/utils/TableGen/ClangAttrEmitter.cpp | 14 +- clang/utils/TableGen/ClangTypeNodesEmitter.cpp | 24 +- clang/utils/TableGen/TableGen.cpp | 7 +- compiler-rt/lib/fuzzer/FuzzerExtraCounters.cpp | 2 +- libcxx/utils/libcxx/test/executor.py | 20 +- libcxx/www/upcoming_meeting.html | 97 ++- lld/ELF/OutputSections.cpp | 26 +- lld/test/ELF/ctors_dtors_priority.s | 18 +- lldb/include/lldb/API/SBBreakpoint.h | 3 + lldb/include/lldb/API/SBBreakpointLocation.h | 7 +- lldb/include/lldb/API/SBBreakpointName.h | 7 +- lldb/include/lldb/API/SBStructuredData.h | 3 + lldb/include/lldb/Core/PropertiesBase.td | 2 + lldb/include/lldb/Core/ValueObject.h | 1 + .../include/lldb/Expression/ExpressionSourceCode.h | 1 + .../Interpreter/OptionGroupPythonClassWithDict.h | 20 +- lldb/include/lldb/Interpreter/ScriptInterpreter.h | 31 +- lldb/include/lldb/Target/MemoryRegionInfo.h | 30 +- .../breakpoint_command/TestBreakpointCommand.py | 8 +- .../TestBreakpointCommandsFromPython.py | 83 +- .../breakpoint/breakpoint_command/bktptcmd.py | 18 + lldb/scripts/Python/python-wrapper.swig | 17 +- lldb/scripts/interface/SBBreakpoint.i | 8 + lldb/scripts/interface/SBBreakpointLocation.i | 11 +- lldb/scripts/interface/SBBreakpointName.i | 4 + lldb/source/API/SBBreakpoint.cpp | 34 +- lldb/source/API/SBBreakpointLocation.cpp | 31 +- lldb/source/API/SBBreakpointName.cpp | 37 +- lldb/source/Commands/CommandObjectBreakpoint.cpp | 8 +- .../Commands/CommandObjectBreakpointCommand.cpp | 48 +- lldb/source/Commands/CommandObjectThread.cpp | 12 +- lldb/source/Commands/Options.td | 7 - lldb/source/Core/ValueObject.cpp | 53 ++ lldb/source/Core/ValueObjectVariable.cpp | 45 - .../Interpreter/OptionGroupPythonClassWithDict.cpp | 61 +- lldb/source/Interpreter/ScriptInterpreter.cpp | 12 +- .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 7 +- .../Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.cpp | 25 +- .../Plugins/Process/minidump/MinidumpParser.cpp | 72 +- .../Plugins/Process/minidump/MinidumpParser.h | 10 +- .../Plugins/Process/minidump/ProcessMinidump.cpp | 41 +- .../Plugins/Process/minidump/ProcessMinidump.h | 3 + .../Python/ScriptInterpreterPython.cpp | 105 ++- .../Python/ScriptInterpreterPython.h | 8 + .../Python/ScriptInterpreterPythonImpl.h | 22 +- lldb/source/Target/CMakeLists.txt | 1 + lldb/source/Target/MemoryRegionInfo.cpp | 20 + lldb/test/Shell/Minidump/memory-region.yaml | 49 ++ .../Shell/ObjectFile/PECOFF/export-dllfunc.yaml | 10 +- .../PECOFF/{subsections.yaml => sections.yaml} | 48 +- .../Shell/SymbolFile/DWARF/DW_OP_piece-struct.s | 113 +++ lldb/tools/driver/Driver.cpp | 19 + .../Process/minidump/MinidumpParserTest.cpp | 163 ++-- .../ScriptInterpreter/Python/PythonTestSuite.cpp | 3 +- lldb/utils/TableGen/LLDBPropertyDefEmitter.cpp | 15 + llvm/CMakeLists.txt | 4 + llvm/bindings/python/llvm/common.py | 4 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 28 - llvm/docs/CMake.rst | 14 +- llvm/docs/FuzzingLLVM.rst | 2 +- llvm/docs/GlobalISel.rst | 940 --------------------- llvm/docs/GlobalISel/GMIR.rst | 158 ++++ llvm/docs/GlobalISel/IRTranslator.rst | 57 ++ llvm/docs/GlobalISel/InstructionSelect.rst | 98 +++ llvm/docs/GlobalISel/Legalizer.rst | 351 ++++++++ llvm/docs/GlobalISel/Pipeline.rst | 82 ++ llvm/docs/GlobalISel/Porting.rst | 21 + llvm/docs/GlobalISel/RegBankSelect.rst | 73 ++ llvm/docs/GlobalISel/Resources.rst | 11 + llvm/docs/GlobalISel/index.rst | 94 +++ llvm/docs/Reference.rst | 6 +- llvm/include/llvm/ADT/StringRef.h | 8 +- llvm/include/llvm/Analysis/ScalarEvolution.h | 3 + llvm/include/llvm/Analysis/TargetTransformInfo.h | 9 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 2 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 9 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 10 +- .../llvm/ExecutionEngine/Orc/ExecutionUtils.h | 2 +- llvm/include/llvm/IR/IRBuilder.h | 22 + llvm/include/llvm/IR/Instructions.h | 4 +- llvm/include/llvm/Support/YAMLTraits.h | 3 +- llvm/include/llvm/TableGen/Record.h | 6 + llvm/lib/Analysis/TargetTransformInfo.cpp | 10 +- llvm/lib/AsmParser/LLParser.cpp | 3 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 25 + llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 + llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +- llvm/lib/CodeGen/SjLjEHPrepare.cpp | 6 +- llvm/lib/IR/Instructions.cpp | 27 +- llvm/lib/ObjectYAML/ELFEmitter.cpp | 2 +- llvm/lib/TableGen/Record.cpp | 15 + .../Target/AArch64/AArch64TargetTransformInfo.cpp | 8 +- .../Target/AArch64/AArch64TargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 2 + llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 15 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 78 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 5 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 3 +- llvm/lib/Target/AMDGPU/FLATInstructions.td | 85 +- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 3 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 161 +++- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 - llvm/lib/Target/AMDGPU/SIISelLowering.h | 8 + llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 28 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 11 + llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 179 ++-- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 8 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 +- llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp | 15 +- .../Target/Hexagon/HexagonTargetTransformInfo.cpp | 31 +- .../Target/Hexagon/HexagonTargetTransformInfo.h | 5 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 11 +- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h | 2 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 4 +- .../Target/SystemZ/SystemZTargetTransformInfo.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 + llvm/lib/Target/X86/X86InstructionSelector.cpp | 2 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 21 +- llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 5 +- llvm/lib/Transforms/Scalar/SROA.cpp | 21 +- llvm/lib/Transforms/Utils/FunctionImportUtils.cpp | 16 +- llvm/lib/Transforms/Utils/InlineFunction.cpp | 10 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 14 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 4 +- .../inst-select-amdgpu-atomic-cmpxchg-flat.mir | 374 ++++++++ .../legalize-atomic-cmpxchg-with-success.mir | 21 +- .../AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir | 96 ++- ...lize-fast-unsafe-fdiv.mir => legalize-fdiv.mir} | 468 +++++++--- .../GlobalISel/legalize-insert-vector-elt.mir | 48 ++ llvm/test/CodeGen/AMDGPU/dpp_combine.mir | 16 + llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir | 48 ++ .../AMDGPU/i1_copy_phi_with_phi_incoming_value.mir | 140 +++ .../CodeGen/AMDGPU/indirect-addressing-si-noopt.ll | 4 - llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 368 +++++++- .../vgpr-descriptor-waterfall-loop-idom-update.ll | 48 ++ llvm/test/CodeGen/BPF/CORE/field-reloc-alu32.ll | 73 ++ llvm/test/CodeGen/BPF/CORE/intrinsic-array.ll | 1 + .../BPF/CORE/intrinsic-fieldinfo-byte-size-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-byte-size-2.ll | 12 +- .../BPF/CORE/intrinsic-fieldinfo-byte-size-3.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-existence-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-existence-2.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-existence-3.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-lshift-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-lshift-2.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-rshift-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-rshift-2.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-rshift-3.ll | 9 +- .../BPF/CORE/intrinsic-fieldinfo-signedness-1.ll | 15 +- .../BPF/CORE/intrinsic-fieldinfo-signedness-2.ll | 12 +- .../BPF/CORE/intrinsic-fieldinfo-signedness-3.ll | 9 +- llvm/test/CodeGen/BPF/CORE/intrinsic-struct.ll | 1 + llvm/test/CodeGen/BPF/CORE/intrinsic-union.ll | 1 + .../CodeGen/BPF/CORE/offset-reloc-access-str.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-array-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-array-2.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-struct-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-struct-2.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-struct-3.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-union-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-cast-union-2.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-end-load.ll | 6 +- llvm/test/CodeGen/BPF/CORE/offset-reloc-end-ret.ll | 3 +- .../CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll | 1 + .../CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-global-1.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-global-2.ll | 2 + .../test/CodeGen/BPF/CORE/offset-reloc-global-3.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-ignore.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-middle-chain.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-multi-array-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-multi-array-2.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-multilevel.ll | 6 +- .../CodeGen/BPF/CORE/offset-reloc-pointer-1.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-pointer-2.ll | 2 + .../BPF/CORE/offset-reloc-struct-anonymous.ll | 8 +- .../CodeGen/BPF/CORE/offset-reloc-struct-array.ll | 6 +- .../CodeGen/BPF/CORE/offset-reloc-typedef-array.ll | 2 + .../BPF/CORE/offset-reloc-typedef-struct.ll | 2 + .../CodeGen/BPF/CORE/offset-reloc-typedef-union.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-typedef.ll | 2 + llvm/test/CodeGen/BPF/CORE/offset-reloc-union.ll | 6 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 55 +- llvm/test/CodeGen/WebAssembly/simd.ll | 32 +- llvm/test/CodeGen/X86/extractelement-index.ll | 24 + .../TableGen/GICombinerEmitter/defs-invalid.td | 42 + .../TableGen/GICombinerEmitter/match-invalid.td | 71 ++ llvm/test/ThinLTO/X86/Inputs/guid_collision.ll | 12 + llvm/test/ThinLTO/X86/guid_collision.ll | 17 + .../CorrelatedValuePropagation/phi-common-val.ll | 27 + .../MachO/Inputs/min_iphoneos_version_lc.yaml | 15 + .../MachO/Inputs/min_macos_version_lc.yaml | 15 + .../MachO/Inputs/min_tvos_version_lc.yaml | 15 + .../MachO/Inputs/min_watchos_version_lc.yaml | 15 + .../MachO/min-version-load-commands.test | 20 + .../llvm-objcopy/MachO/MachOLayoutBuilder.cpp | 3 + llvm/unittests/IR/IRBuilderTest.cpp | 9 + llvm/utils/TableGen/GICombinerEmitter.cpp | 3 + .../clangd/refactor/tweaks/BUILD.gn | 1 - llvm/utils/lit/lit/cl_arguments.py | 3 + llvm/utils/lit/lit/display.py | 15 +- llvm/utils/lit/lit/main.py | 51 +- llvm/utils/lit/lit/run.py | 3 + llvm/utils/lit/lit/util.py | 2 + .../tests/Inputs/shtest-shell/stdout-encoding.txt | 7 + llvm/utils/lit/tests/max-failures.py | 2 +- llvm/utils/lit/tests/shtest-shell.py | 14 +- .../deviceRTLs/nvptx/src/omptarget-nvptx.h | 22 +- .../deviceRTLs/nvptx/src/target_impl.h | 15 + 233 files changed, 5529 insertions(+), 3973 deletions(-) delete mode 100644 clang-tools-extra/clangd/refactor/tweaks/DefineInline.cpp create mode 100644 clang/test/Sema/typo-correction-ambiguity.c create mode 100644 clang/utils/TableGen/ClangASTEmitters.h create mode 100644 lldb/source/Target/MemoryRegionInfo.cpp create mode 100644 lldb/test/Shell/Minidump/memory-region.yaml rename lldb/test/Shell/ObjectFile/PECOFF/{subsections.yaml => sections.yaml} (65%) create mode 100644 lldb/test/Shell/SymbolFile/DWARF/DW_OP_piece-struct.s delete mode 100644 llvm/docs/GlobalISel.rst create mode 100644 llvm/docs/GlobalISel/GMIR.rst create mode 100644 llvm/docs/GlobalISel/IRTranslator.rst create mode 100644 llvm/docs/GlobalISel/InstructionSelect.rst create mode 100644 llvm/docs/GlobalISel/Legalizer.rst create mode 100644 llvm/docs/GlobalISel/Pipeline.rst create mode 100644 llvm/docs/GlobalISel/Porting.rst create mode 100644 llvm/docs/GlobalISel/RegBankSelect.rst create mode 100644 llvm/docs/GlobalISel/Resources.rst create mode 100644 llvm/docs/GlobalISel/index.rst create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-c [...] rename llvm/test/CodeGen/AMDGPU/GlobalISel/{legalize-fast-unsafe-fdiv.mir => legal [...] create mode 100644 llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir create mode 100644 llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir create mode 100644 llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/field-reloc-alu32.ll create mode 100644 llvm/test/TableGen/GICombinerEmitter/defs-invalid.td create mode 100644 llvm/test/TableGen/GICombinerEmitter/match-invalid.td create mode 100644 llvm/test/ThinLTO/X86/Inputs/guid_collision.ll create mode 100644 llvm/test/ThinLTO/X86/guid_collision.ll create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_iphoneos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_macos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_tvos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/Inputs/min_watchos_version_lc.yaml create mode 100644 llvm/test/tools/llvm-objcopy/MachO/min-version-load-commands.test create mode 100644 llvm/utils/lit/tests/Inputs/shtest-shell/stdout-encoding.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 7 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits October 2019