Tcwg-commits August 2018

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[binutils-gdb] branch binutils-2_31-branch updated (d8d43263de -> 6cfa38dcca)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch binutils-2_31-branch in repository binutils-gdb. from d8d43263de Automatic date update in version.in new 6cfa38dcca Automatic date update in version.in The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[llvm] branch stable updated (81aee6ad323 -> 8b1a840e1ea)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch stable in repository llvm. from 81aee6ad323 Cherry-pick @=r331237 to google/stable for 2018-04-24 adds 8d30eefaa82 AMDGPU/R600: Move int_r600_store_stream_output to the publi [...] adds 22fafe6262a Fix PluginsTests failure on Windows buildbots by enabling i [...] adds c2341723b51 [CostModel][X86] Remove hard coded SDIV/UDIV vector costs adds bf540e5abf5 [ADT] Make filter_iterator support bidirectional iteration adds 2339c939d32 [codeview] Ignore .cv_loc directives at the end of a function adds fa6d83b0efb Revert "[SCEV] Make computeExitLimit more simple and more p [...] adds e40f6e7cc78 [x86] NFC: Add tests for idiomatic usage patterns of SSE4.2 [...] adds e6b928e47ef [x86] Allow folding unaligned memory operands into pcmp[ei] [...] adds 9c7aaf79c7b [X86] Remove alignment restriction on loading folding of pc [...] adds 70356d01bed [X86] Print 'tbyte ptr' instead of 'xword ptr' for f80mem i [...] adds 185e3b30158 [cmake] Make linker detection take flags into account adds 9821cf74ede [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + [...] adds c5330c71212 [AArch64][SVE] Asm: Negative tests for all LD1 gather (scal [...] adds be4cc030a18 [AsmMatcher] Extend PredicateMethod with optional Diagnosti [...] adds d2276970d84 [LoopInterchange] Ignore debug intrinsics during legality checks. adds bc5698ba250 [RISCV] Implement isLegalAddressingMode for RISC-V adds a3c21b0537b [NVPTX] Deduplicate code. No functionality change. adds 7940af08536 [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 inst [...] adds bf50bde3b17 [Tablegen] Simplify code in CodeGenSchedule. NFCI adds 3797a2a785d [RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.ll adds e79c7309951 [RISCV] Implement isLegalAddImmediate adds 22648bee7c7 [RISCV] Implement isLegalICmpImmediate adds 9cb52f974c2 [X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153 adds 9ead1e23d40 [RISCV] Implement isTruncateFree adds daa39fa1446 [TTI, AArch64] Add transpose shuffle kind adds 0faf8b4d623 [RISCV] Add test case showing suboptimal codegen when loadi [...] adds cdb6162eae2 [RISCV] Implement isZextFree adds 4965d63ae58 [SLP] Add tests for transposable binary operations adds fbcfd868946 [DAGCombiner] refactor FP->int->FP folds; NFC adds 91250e2b2c5 [NVPTX] Make the legalizer expand shufflevector of <2 x half> adds 72eae93f498 [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot adds 3b2f0b2c7e6 [x86] add tests to show potential opt-out of ftrunc optimiz [...] adds ac6d1cea2c1 [DAGCombiner] limit ftrunc optimizations with function attribute adds ce17a9d46b7 [mips] Correct the definitions of some control instructions adds 3d681a99a40 [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increm [...] adds 33005b401f4 [mips] Fix a test case which is keeping the expensive check [...] adds 588fa1cad77 [WebAssembly] Implement getRelocationValueString() adds 5fad6ea6c23 [docs] provide the specific sanitizer option to detect junk [...] adds cc3b83d8d1f [WebAssembly] objdump: Don't assume all relocations have symbols adds f4dab0c2a91 Enable EliminateAvailableExternally pass for -O1 adds 1cd3240882b Update stale comment in AsmWriter.cpp adds 37dc08589c4 [llvm-objcopy] Add --localize-symbol option adds b8d7c9d778c Revert "Enable EliminateAvailableExternally pass for -O1" adds 7d80a6294a8 [GlobalMerge] Fix a typo adds 421a0c12e3d [Tablegen] SubtargetEmitter: move the logic that prints pre [...] adds 14598cb5bea [WebAssembly] Add version to object file metadata adds 32642131702 Fix a bug that prevents global variables from having a DW_O [...] adds 16388e77fc9 augmenting description for fcmp fmf - NFC adds 5b92658eab7 [llvm-objcopy] Implement --redefine-sym option adds fb0b830464e [NFC][InstCombine] Regenerate rem.ll test adds a98558c3866 [NFC][InstCombine] rem.ll: add a few commutative tests. adds 709bf508a90 [AArch64] Fix scavenged spill slot base when stack realignm [...] adds e2f88d3b9a1 Specify REQUIRES: default_triple in a few tests adds 2e7b4c5405d AMDGPU: Consolidate SubtargetPredicate definitions adds 901e22891db AMDGPU: Extend extract_vector_elt fneg combine to fabs adds ee52da49b0d DAG: Fix not legalizing vector fcanonicalizes adds db159759834 [WebAssembly] Write DWARF data into wasm object file adds 5f68be89e4b [mips] Accept 32-bit offsets for lb and lbu commands adds 7d6aa56ead5 [InstCombine][NFC] Autogenerate checks in add2.ll adds cbf3f54dff9 [InstCombine][NFC] add2.ll: add a few commutative checks. adds 9fad7326f23 [GlobalISel] Reporting rules covered as part of the Instruc [...] adds 607345d051b Add test cases to prepare for the optimization that simplif [...] adds 03f69e2059e [InstCombine] Simplify Add with remainder expressions as operands. adds 99f635bea8c Revert "Fix a bug that prevents global variables from havin [...] adds 0f767de451d [InstCombine][NFC] Regenerate checks in and-or-not.ll adds 25d4db48523 Fix WAsm dwarfdump.ll test on Windows adds 0f3f12ec789 [InstCombine][NFC] Regenerate checks in or-xor.ll adds 8b02b588cb9 [x86] Revert r330322 (& r330323): Lowering x86 adds/addus/s [...] adds d602d5b93e0 [Docs] Escape the @ symbol, so that it appears in documenta [...] adds 891b01ba295 [MCA] [NFC] Remove unused Index formal from ResourceManager [...] adds c64f4dbfe31 [SimplifyLibcalls] Replace locked IO with unlocked IO adds bfeca0b1206 [WebAssembly] Section symbols must have local binding adds 4f72fc1174b typo adds c37837519dd [MachineOutliner] Don't outline from functions with a secti [...] adds 677e33fc8cf [LowerTypeTests] Mark .cfi.jumptable nounwind. adds d0cb2418452 Revert "[SimplifyLibcalls] Replace locked IO with unlocked IO" adds fe97d18817f [SCEV] Introduce bulk umin creation utilities adds 7ebdaa5e109 [SCEV] Add trivial case handling for umin utilities. NFC. adds 0059657b9aa [mips] Add support for Virtualization ASE adds 90b5ec2f8c1 [IR] Do not assume that function pointers are aligned adds 3b36f77f20f [ARM] Enable misched for R52. adds 38ee805f387 [RISCV] Add remat.ll test case adds 3a0e81d0140 [ARM] Codegen for v8.2A dot product intrinsics adds 4f0010fac23 [mips] Fix how compiler fuse instructions to fmadd/fmsub adds 5139b77fb91 [X86] Replace some system instruction instregex single matc [...] adds 937d9c92192 [NVPTX] Turn on Loop/SLP vectorization adds 748ab1eecfb [AArch64] Codegen for v8.2A dot product intrinsics adds 05bf903bd8e [LoopInterchange] Allow some loops with PHI nodes in the ex [...] adds 98eb0b86705 [SystemZ] Remove scheduling info from some Pseudo instruct [...] adds bd3f6f82e44 [CMake] Enable warnings for runtimes adds 3f9ed1ace43 [AArch64] Place the first ldp at the end when ReverseCSRRes [...] adds 92f209bb4f1 [MC] Allow MCAssembler to be constructed without all subcom [...] adds 80e97ed5822 [MC] Modify MCAsmStreamer to always build MCAssembler. NFCI. adds e43061bb3d9 [mips] Analyze and provide selection patterns microMIPSR6 branches adds 1914c078e33 [X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler [...] adds b2d1a403437 [MC] Provide default value for IsResolved. adds 81262185f8b [X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes adds 9ef9fcf66c4 [MC] Undo spurious commit added into r331052. adds 534e40103f6 [docs] add fp-cast-overflow-workaround options to release notes adds 7b018587636 [LoopGuardWidening] Split out a loop pass version of GuardWidening adds 38e21b14cb4 [GuardWidening] Add some clarifying comments about heuristi [...] adds fbad418d179 [AMDGPU][Waitcnt] Update a few tests to use default waitcnt [...] adds b5e2d41d5d1 [X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle int [...] adds a7632db848d [CodeGen] Use RegUnits to track register aliases (NFC) adds 384d8a7924c [llvm-objcopy] Add --globalize-symbol option adds 0fb24c145bf [llvm-objcopy] Add --weaken-symbol (-W) option adds 9378c2c1c00 [globalisel][legalizerinfo] Add support for legalization ba [...] adds e76c8192cb3 [PostRASink] extend the live-in check for all aliased registers adds c541b9362d9 Attempt to fix build failure after r331071 using std::make_tuple adds 1c0f86d3849 [LV] Common duplicate vector load/store address calculation (NFC) adds 1e6776e94bc ELFObjectWriter: Allow one unique symver per symbol adds 4ae479c7098 [MustExecute/LICM] Special case first instruction in throwi [...] adds b151c0a66a5 [LICM] Reduce nesting with an early return [NFC] adds 959d9259f68 Attempt to fix remaining build failures after r331071 by ch [...] adds ae8da5c9b0d [Reassociate] add a test with debug info; NFC adds 4bce98cf1d8 [X86] Merge some x87 instruction instregex single matches. NFCI. adds a9bc2db4f52 [PatternMatch] Stabilize the matching order of commutative [...] adds 73de5c1a0b6 Fix a bug in GlobalOpt's handling of DIExpressions. adds 2c33602f655 [FastISel] Fix local value sinking algorithmic complexity adds d2717415862 [FastISel] Actually enable local value sinking by default adds e41979a9cea Fix a bug that prevents global variables from having a DW_O [...] adds 7b0ac2c3d94 [X86] Make the STTNI flag intrinsics use the flags from pcm [...] adds 971993b371e [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor adds 72a0048d96b [LoopGuardWidening] Make PostDomTree optional adds 1898130f0dc [MachineOutliner] Add defs to calls + don't track liveness [...] adds c16075d9bd7 [SCEV] Reduce the number of invocation to non trivial getEx [...] adds 281bdac7f28 [NFC] Add some tests that demonstrate unrecognized three-wa [...] adds 87faffc7c18 [X86] Rename BNDMOV instructions and hide redundant instruc [...] adds 4daa1867cbf [X86] Remove REX.W from 64-bit mode BND instructions. adds 3f6034f46a9 [SCEV] Touch the unsused stats variables for product build. adds 762f485791f [X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDS [...] adds 12eeab5f684 [X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU. adds 00a047825e7 [X86][HW] Cleanup Haswell model. NFCI. adds da1f4275f62 [X86][SSE] Stop hard coding some instruction scheduler classes. adds 27505b427b8 [llvm-mca][X86] Add shift/rotate resource tests to all rele [...] adds 407eee0424f [llvm-mca][X86] Add double shift resource tests to all rele [...] adds df14a5b448e [X86] Remove unnecessary shift/rotate folded InstRW overrides. adds 4147eac22fe [InstCombine][NFC] Add tests for variable mask canonicaliza [...] adds 20230f9b428 [InstCombine] Canonicalize variable mask in masked merge adds cb994145314 [LLVM-C] Miscellaneous Cleanups in DIBuilder Bindings adds dc034412969 [globalisel][legalizerinfo] Introduce dedicated extending l [...] adds d585032b63b [X86] Remove unnecessary rotate-carry folded InstRW overrides. adds 6f7f5298e9e [X86] Restrict many of the InstAliases to either to only at [...] adds e2e5efbda0b [LLVM-C] Add DIBuilder bindings to create import declarations adds 63033d33c83 s/LLVM_ON_WIN32/_WIN32/, llvm adds c4f20790872 [X86] Use getX86SubSuperRegister in addGR32orGR64Operands i [...] adds a89b59631cf Update my email address and description. adds 4d8bcba14b9 [LLVM-C] Eliminate an unused variable in a test. adds bbb21f3a9e9 [X86] Remove unnecessary InstAliases. NFCI adds d9a4b27a8f5 [X86] Remove SLDT64m instruction. adds 519e2e52fa1 [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in [...] adds 8784c51c371 [NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file adds f690766686d [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models adds 497385919fe [X86] Remove unnecessary add/adc+sub/sbb InstRW overrides. adds 48d44aec6d8 [X86] Merge more instregex single matches to reduce InstrRW [...] adds c33c392d270 [llvm-mca][X86] Add BT resource tests to all models adds 1f8d9bb5140 [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + [...] adds f410192f884 [AArch64][AsmParser] NFC: Cleanup of addOperands functions adds 72f83b0b830 [X86] Remove unnecessary BT InstRW overrides. adds e803a9e5883 [X86] Make 64-bit sysret/sysexit not ambiguous in Intel ass [...] adds f7060b53312 Remove a dead #ifdef. adds d812737d710 [X86] Mark some more InstAliases as 'att' syntax only. adds 0d85819205d [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'. adds 9ca2be762bf [X86] Use a MnemonicAlias instead of an InstAlias. adds 4ed0632f8ff [X86] Remove some instructions from the Intel assembly matc [...] adds b4e8dd07719 [X86] Remove some InstAliases aren't needed because a Mnemo [...] adds 1f7a4c875d5 [X86] Hide another instruction from the assembly matcher ta [...] adds 1fe601794ad [X86] Add a Requires<[In64BitMode]> to FARJMP64 adds 15f591eb7de [AArch64][SVE] Asm: Improve diagnostics for gather loads. adds 223197ab455 [mips] Fix microMIPS loads and stores. adds 7c84ee231be NFC - Typo fixes lib/VMCore -> lib/IR adds 3be77b30e98 [X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD in [...] adds 0110ab1c051 [llvm-mca] Support for in-order CPU for -instruction-tables [...] adds fd5e85b6fed [llvm-mca] Regenerate test Atom/resources-sse3.s. NFC adds 068c967842b [bindings] Fix dibuilder go bindings after r331114. adds 051bfd9f172 [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC). adds a831d3894ff [mips] Fix the predicates of jump and branch and link instructions adds 426e78a6835 Revert "[mips] Fix the predicates of jump and branch and li [...] adds 636aebaef4a NFC, Avoid a warning on pointer casting in PassPlugin.cpp adds 7831bed7001 [SelectionDAG] Improve selection of DBG_VALUE using a PHI n [...] adds b0beac8bcff [BranchFolding] Salvage DBG_VALUE instructions from empty blocks adds 0f38c60baff IWYU for llvm-config.h in llvm, additions. adds 3984543d60b AMDGPU/GlobalISel: Don't try to lower geometry shaders adds dc81591f346 [X86] Fix SkylakeServer typo in WritePSADBW class - it only [...] adds c9cfc15fa0b [X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer. adds 05cdaca17f6 IWYU for llvm-config.h, removals. Also see r331184. adds b6736ee4c14 [SystemZ] Improve handling of Select pseudo-instructions adds b57e446bd82 [SystemZ] Refactor some VT casts in DAG match patterns adds 1cff79735ca [llvm-mca] Correctly handle zero-latency stores that consum [...] adds 5b508199fa8 AMDGPU: Remove some dead code adds 4bc4b1d20be [X86][Atom] Remove unnecessary x87 load/move instrw overrides. adds 44735eb19df [SLPVectorizer] Debug info shouldn't impact spill cost comp [...] adds 8cde9622c0a [DebugInfo] Prevent infinite recursion for malformed DWARF adds 2a793f6500a Fix infinite loop after r331115 adds 488cbd2beb1 [SystemZ] Do not use glue to represent condition code dependencies adds 815278b2cd8 [SystemZ] Handle SADDO et.al. and ADD/SUBCARRY adds 7a3b1c9910a [InstCombine][NFC] Add tests for unfolding masked merge wit [...] adds fa71b55bb99 [InstCombine] Unfold masked merge with constant mask adds 4bb83a6ed95 [X86] Introduce X86SchedWriteWidths schedule wrapper for di [...] adds f95322c9b76 [DAGCombiner] rename function attribute for disabling ftrun [...] adds be8f7c9e0e1 [MIR] Reset unique MBB numbering in MachineFunction::reset() adds ac9b3ef76a0 AMDGPU: Add Vega12 and Vega20 adds d3476a44996 [LoopSimplify] Use BB::instructionsWithoutDebug to skip Dbg [...] adds 4d344626681 [MC] Change AsmParser to leverage Assembler during evaluation adds 7d1c37461e1 [LivePhysRegs] Remove registers clobbered by regmasks from [...] adds 8b887213a74 [WebAssembly] MC: Improve debug output adds 557a92ca576 [SimplifyCFG] Use BB::instructionsWithoutDebug to skip DbgI [...] adds 363c4c6046e [ModRefInfo] Rename local variable IsMustAlias to avoid sha [...] adds 4833be099d2 Stop setting LLVM_ON_WIN32 in config.h and llvm-config.h. adds 4a2bb8514f6 [InstCombine] add tests, update checks; NFC adds b787db4da51 [InstCombine] fix test to restore intent adds d3fc40c71bb Temporarily revert "[DEBUG] Initial adaptation of NVPTX tar [...] adds 52c132f528d [X86] Remove 'opaque ptr' from the intel syntax parser and [...] adds 112030e33ee [PM/LoopUnswitch] Add back a successor set that was removed [...] adds dd0dfea28b2 [PM/LoopUnswitch] Remove the last manual domtree update cod [...] adds 03a7ebed885 [X86] movdiri and movdir64b instructions adds b86d2aaf27d NFC, Avoid a warning in WasmObjectWriter adds 05b1399b378 [X86] Correct spill slot size. adds 863acbcdf35 [X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes i [...] adds fb5fad4f7cf [MC] Add llvm_unreachable to toString to fix compile time warning. adds 35643469442 [X86] Convert all uses of WriteFLogic/WriteVecLogic to X86S [...] adds 86ff4579440 [InstCombine] Adjusting bswap pattern matching to hold for [...] adds 332212679ea [X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes adds 8766b180e3f Reland r331175: "[mips] Fix the predicates of jump and bran [...] adds b810df1e668 [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scal [...] adds 60873f11912 [X86] Convert all uses of WriteFShuffle to X86SchedWriteWidths. adds 186779bae5c [X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classes adds 019918ff9b8 [InstCombine] new testcases for OverflowingBinaryOperators [...] adds deb49e5e4e7 Fix the issue that ComputeValueKnownInPredecessors only han [...] adds 974321bd675 [LV] Preserve inbounds on created GEPs adds 2e4c642274d [DAG] add test to show FMF mismatch between IR and DAG; NFC adds 26b584c6918 Remove \brief commands from doxygen comments. adds f91f75799cd [X86] Convert all uses of WriteFAdd to X86SchedWriteWidths. adds 9acd5ab38bd [SLP] Add additional test for transposable binary operation [...] adds 0b24b74655b Remove @brief commands from doxygen comments, too. adds f7e2c2e351a [X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes adds de3e0c4a2c3 AMDGPU/NFC: Use enum values for first/last machs instead of [...] adds edd76949f48 [WebAssembly] llvm-readobj: display symbols names in relocations adds f86c5df7eb5 Fix the sed command in test which doesn't work well on BSD. adds 31d3d2138ae [LV] Move test/Transforms/LoopVectorize/pr23997.ll adds f558d10cc73 Support: assume `std::is_final` with MSVC adds 579a47854bb [X86] Split WriteFCmp into XMM and YMM/ZMM scheduler classes adds abd10450687 AMDGPU: Add missing gfx904 tests adds 082b4ed62ad Use no-op opt run to eliminate the difference in bb pred co [...] adds 8864a3add44 [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt into XMM and Y [...] adds df69f1ffbe6 llvm-symbolizer: Handle function definitions nested within [...] adds 6cdbf16e556 [X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM schedu [...] adds 7efbee14e3f [X86][AMD][Bulldozer] Fix Bulldozer Model 2 detection. adds 53f34ec97af AMDGPU: Remove remnants of gfx901 (it was deprecated some t [...] adds f3a5c86e781 [DAGCombiner] Set the right SDLoc on a newly-created zextlo [...] adds fec188eac77 [DAGCombiner] Change the SDLoc on split extloads (2/N) adds cad24a07046 [DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N) adds 1ae0aae5523 [DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N) adds 792a593446e [AArch64] Add more tests for 64-bit immediate lowering. adds b5a4cf07e41 Create a MachineBasicBlock for created IR-level BasicBlock adds b68ff828994 [PhaseOrdering] add tests for bittest patterns from bitfields; NFC adds bcc7a8e4138 [AggressiveInstCombine] add more bitfield test patterns; NFC adds 2f7417dcfbd [AggressiveInstCombine] convert a chain of 'or-shift' bits [...] adds 090f8159a44 [CFLGraph][NFC] Simplify/reorder switch in visitConstantExpr adds 20a92cda49e [AMDGPU] Support horizontal vectorization. adds ff933fa1afa [llvm-mca] Lift the logic of the RetireControlUnit from the [...] adds ac135922af3 [WebAssembly] Fix debug printing of symbol types adds 81352e1cb7a Fix release build breakage adds f4f861bbdf9 [XRay][tools] Rename llvm-xray filenames from .cc -> .cpp (NFC) adds dd5fd467498 [SelectionDAG] Selection of DBG_VALUE using a PHI node resu [...] adds a5108a08cea Mark invariant.group.barrier as inaccessiblememonly adds 33b9c81ee37 [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate qu [...] adds 3a58e1f0020 [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with mo [...] adds 112e4a35e62 [mips] Correct the predicates for shifts. adds 6e79b3cdd6f [LoopInterchange] Update some loops to use range base for l [...] adds f05d034950f [AArch64][SVE] Asm: Support for non-temporal, contiguous LD [...] adds b997056fc04 [mips] Correct the predicates of sign extension instructions adds c2f66823b6b [X86] Convert most remaining uses of X86SchedWritePair sche [...] adds d0aace53a9f Revert "[mips] Correct the predicates of sign extension ins [...] adds 0a3e3f4afff [AArch64][SVE] Asm: Support for scatter ST1 store instructions. adds d8fa26e8a2e [TableGen] Don't quote variable name when printing !foreach. adds 2b361d88401 [AArch64][SVE] Asm: Support for LDR/STR fill and spill inst [...] adds 97ed34f9ec1 [X86] Convert most remaining AVX512 uses of X86SchedWritePa [...] adds f17b4d4a4bb [MIPS] Fix DIV/DIVU scheduling classes. adds cf0ce438e23 [X86] Fix scheduling info for VMPSADBWYrmi. adds 4f646b035dc [X86] Fix scheduling info for (V?)SQRTPDm on silvermont. adds 17307b033d7 Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi." adds 4f6742d8772 Fix '32-bit shift implicitly converted to 64 bits' warning [...] adds 05610b58279 [X86] Cleanup WriteFMul scheduler classes with more common [...] adds 202b0b58453 Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi." adds f4450482f65 Fix line-endings. NFCI. adds 432963dc824 [AMDGPU] performAddCombine should run after DAG is legalized. adds 6ad7abcee0f [X86] Convert most remaining XOP uses of X86SchedWritePair [...] adds 301a226e182 Revert "[AMDGPU] performAddCombine should run after DAG is [...] adds f6719aecc70 Add assertion to padding size calculation, NFC adds 598de77414d [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants [...] adds 1bfbf81635d [reassociate] Fix excessive revisits when processing long c [...] adds 7edace1421a [AMDGPU] A trivial fix for a buildbot failure caused by "co [...] adds b5c75dc9ca1 [COFF, ARM64] Hook up a few remaining relocations adds 4d488f3b4bb [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/Write [...] adds 06eed39e54f Move the TestPlugin project into the Tests folder in CMake. adds 4e899cb6321 [X86][SNB] Fix scheduling of MMX integer multiply instructions. adds e99f5b406a0 [llvm-rc] Add rudimentary support for codepages adds 36d15d60b6e [GlobalISel][InstructionSelect] Refactoring out a getMatchT [...] adds 260d84af6d2 [GlobalISel][InstructionSelect] Refactoring buildMatchTable [...] adds b4db044c017 [llvm-objcopy] Add --weaken option adds 21e59fd7ef4 [GlobalISel][InstructionSelect] Making Coverage Info genera [...] adds 80e28a9c4e8 [llvm-objcopy] Add --discard-all (-x) option adds 0f7c92aee76 [llvm-cvtres] Allow parameters preceded by '-' in addition to '/' adds 8f8e40c8e2d [llvm-rc] Default to writing the output next to the input, [...] adds df9a986c159 [GCOV] Emit the writeout function as nested loops of global data. adds 47a8f72fea6 [PowerPC] No CTR loop if the candidate exiting block is in [...] adds 1e2e5ffd567 [MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO [...] adds 1c4e4c492f5 [WebAssembly] MC: Create and use first class section symbols adds 7577f35f341 [PowerPC] Implement isMaskAndCmp0FoldingBeneficial adds ecfd97d59f0 MachineInst support mapping SDNode fast math flags for supp [...] adds dc1628b5e70 [gcov] Switch to an explicit if clunky array to satisfy som [...] adds 034a688e829 Commit r331416 breaks the big-endian PPC bot. On the big en [...] adds b9e51cf03e5 [ObjCARC] Convert an if to an early continue. NFC adds e776b8b57b7 [Support] Support building LLVM for Fuchsia adds cfd866304a2 Re-enable "[SCEV] Make computeExitLimit more simple and mor [...] adds 886c0f8e39c lit: flesh out `SubsituteCaptures` further adds 616f8fbe5e5 [LoopIdiomRecognize] Remove unnecessary cast from BinaryOpe [...] adds 524b220de9d [LoopIdiomRecognize] Add a test case showing that we transf [...] adds b5d9edcf9e1 [LoopIdiomRecognize] When looking for 'x & (x -1)' for popc [...] adds 2d481a978b4 [TableGen][NFC] Make ResourceCycles definitions more explicit. adds 5675d3b6a49 Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI n [...] adds b3f6a6a6162 [WebAssembly] MC: Don't litter test directory. adds aa8d271482a [X86] Update MMX instructions to be tagged with X86SchedWri [...] adds 4c3bf0a0727 [X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSA [...] adds d0aaa150ffc [X86][AVX512] VPAVG instructions should be tagged as SchedW [...] adds 9648b463253 Rename invariant.group.barrier to launder.invariant.group adds 4d0342f0d93 perform DSE through launder.invariant.group adds 4c19071b5b4 ARM: don't try to over-align large vectors as arguments. adds 2cc6ed7b2eb [X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM sch [...] adds e14cfef0896 [CodeGen][X86][NFC] Copy two selectcc tests from AArch64. adds d8f6aa43aa8 use LLVM's standard CMakeLists.txt layout for llvm-xray adds 5c162365ddc Reapply "[SelectionDAG] Selection of DBG_VALUE using a PHI [...] adds ad2b36f02c0 [DebugInfo] Correction for an assert in DIExpression::creat [...] adds 00c1a2374f1 [PowerPC] add tests for FMF propagation; NFC adds c9b68352598 [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM an [...] adds 3e77bbe6778 [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul [...] adds da9cac629ca [PowerPC] add more FMF debug output; NFC adds 3a0c2765857 [ThinLTO] Add support for optimization remarks to thinBackend adds 57342fb583a GlobalISel: Use a callback to compute constrained reg class [...] adds b841e3b9476 [InstCombine] refine select-of-constants to bitwise ops adds bf0b5f5f330 Fix include of config.h that was incorrectly changed in r331184 adds a71b5d3c632 [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes adds bbc6a290c8b [X86] Add WriteDPPD/WriteDPPS dot product scheduler classes adds 220e35cb11c AMDGPU: Make getSubRegFromChannel a static member of AMDGPU [...] adds 013b5ae046d [LoopIdiomRecognize] Add a test case to show incorrect tran [...] adds 41532eec3cf [LoopIdiomRecognize] Turn two uncheck dyn_casts into regula [...] adds 928cd2f4095 [LoopIdiomRecognize] Use a regular array instead of a Small [...] adds eecfb9c5eca [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast. adds 53458b4d8af [MachineCSE] Rewrite a loop checking if a block is in a set [...] adds de00b9f0703 [XRay][compiler-rt+docs] Introduce __xray_log_init_mode(...). adds db587a4f07d [IRCE] Fix misuse of dyn_cast which leads to UB adds cac7859af8d [RegUsageInfoCollector] Bugfix for handling of register aliases. adds 6542d5412c2 [SelectionDAG] Refactor code by adding RegsForValue::getReg [...] adds 23c1e933eb6 Word wrap a test-file comment to 80 columns adds fac3f324f98 [X86] Add test case for PR30290s failing behaviour adds 771e0a55164 [X86] Add SchedWriteFRnd fp rounding scheduler classes adds f501530ff63 [llvm-mca] remove unused argument from method InstrBuilder: [...] adds f6d466f5ba0 [llvm-mca] use colors for warnings and notes generated by I [...] adds 1a966b86697 [Hexagon] Skip reserved physical registers when updating liveness adds e7b4c7bbff6 [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32 adds 3ca5f74c79b [X86] Add WriteVecMOVMSKY scheduler class adds aff0c11ab4f [mips] Correct the predicates of sign extension instructions adds 66648415b9e [Hexagon] Handle non-immediate constants in HexagonSplitDouble adds adb4ffc3118 [Hexagon] Remove leftover debugging code after r331527 adds 3847aa02de2 [bindings/go] Add Go bindings for volatile loads/stores adds 43fbec5ac72 [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWi [...] adds 60248da1b67 [llvm-exegesis] Fix pfm counter names for BDW. adds a244d9e3deb DwarfCompileUnit: Fix another assertion failure on malforme [...] adds c0d9a0b316b obj2yaml: Correctly round-trip default alignment. adds 1f438297062 Object: The default alignment of a section without alignmen [...] adds 5646bfe92b7 [llvm-mca] Add descriptive names for the TimelineView repor [...] adds dbaf52b13f0 [AArch64] Add missing testcase for r331522 adds 671262c2c32 [LoopIdiomRecognize] Don't create an IRBuilder just to call [...] adds 512e46b3c9c [X86] Finish splitting WriteVecShift and WriteVecIMul to re [...] adds 3571b4d5a24 [X86] Add WriteEMMS scheduler class adds eb53cf72757 Fast Math Flag mapping into SDNode adds b90f003d3e7 [ObjCARC] Account for catchswitch in bitcast insertion adds 156f761cf0f [MachineLICM] Debug intrinsics shouldn't affect hoist decisions adds 0511853bbf8 AMDGPU: Add D16 instructions preserve unused bits feature adds 847f729f1cf AMDGPU/NFC: Fix formatting for 900, 902 ISA Version features adds 806dec77cbe [LICM] Compute a must execute property for the prefix of th [...] adds 380bd7f59c1 AMDGPU/NFC: Update D16PreservesUnusedBits description based [...] adds 125f36c4f3c Mapping SDNode flags to MachineInstr flags adds 62b8986cc32 [llvm-mc-assemble-fuzzer] Catch up with API changes. adds 61d9a69a186 [LTO] Allow pass remarks with hotness to be set when emitti [...] adds bb011b6cdd0 LowerTypeTests: Fix non-determinism in code that handles ic [...] adds 412df0bfa1a Fix a bunch of places where operator-> was used directly on [...] adds 874de34d8cf GlobalISel/InstructionSelector: Implement GIR_CopyFConstantAsFPImm adds 44008c54476 Range-ify for loop; NFC adds 3f9d52f4a86 [Option] Remove an unnecessary conversion function. adds 869a79511a3 [MIRParser] Allow register class names in the form of integ [...] adds 5726495e3ab [CaptureTracking] Handle capturing of launder.invariant.group adds bbb655f05f5 [NFC][DagCombiner] unfoldMaskedMerge(): improve readability. adds 24727498547 [llvm-mca] minor tweak to the resource pressure printing fu [...] adds 5a92153e842 [LTO] Handle Task=-1 passed to addSaveTemps adds d6075d034eb [llvm-mca] removes flag -instruction-tables from the "View [...] adds fe26f48c1eb [DAGCombiner] Masked merge: don't touch "not" xor's. adds 9de4e7f7794 Simplify LLVM_ATTRIBUTE_USED call sites. adds b1f8c095b15 [MIRPraser] Improve error checking for typed immediate operands adds 2cc8a8f7a4b [globalisel] Update GlobalISel emitter to match new represe [...] adds c353ad5eeba [MC] Remove unused MCOI::GenericOperandType adds 722cccb8cf0 [globalisel] Remove redundant -global-isel option from test [...] adds 53dc71d2945 Add test cases for large integer legalization of add and sub. NFC adds e49d7b229d4 [X86] Add test cases for reciprocal estimation for v16f32 v [...] adds 98e0a453a76 [X86] Enable reciprocal estimates for v16f32 vectors by usi [...] adds b13221b35cf [NFC][DAGCombine] unfoldMaskedMerge(): rename two variables adds c5823bd8664 [llvm-dwp] Define InitLLVM. adds c35bab7d2b2 [X86] Fix copy/paste mistake in comment. NFC adds af4d5d44bb6 [TargetLowering] Use StringRef::split instead of SplitString. NFC adds ece3eb8cb6b [ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's [...] adds 10f1f0d599b Fix comment. NFC adds 073b5b41a60 [llvm-exegesis] Add a library to cluster benchmark results. adds bfa2014b785 Revert r331622 "[llvm-exegesis] Add a library to cluster be [...] adds 7b8a8728fbd Re-land r331622 "[llvm-exegesis] Add a library to cluster b [...] adds c151f6b7d53 [InstCombine][NFC] Add tests for one more masked merge pattern. adds 8f5a881fd76 [SystemZ] Bugfix for MVCLoop CC clobbering. adds a7b63e74c96 Skip unreachable blocks for CFIInstrInserter verify adds e1b4442d3ff [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classes adds b107abeaf82 [AMDGPU] Don't force WQM for DS op adds 55cedcc499f [NFC] Fix typo in variable name. adds 44b4b3a2582 Add option -verify-cfiinstrs to run verifier in CFIInstrInserter adds ac95aa53619 [AMDGPU][Waitcnt] Remove the old waitcnt pass adds d1ce206367a [X86] Split WriteFDiv schedule classes to support single/do [...] adds 72c0afef177 [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases. adds 3491ea57525 [DAGCombine][NFC] Masked merge unfolding: comment: some tes [...] adds 8fd84d4be29 [Hexagon] Move clamping of extended operands directly to MC [...] adds a3a709fa554 [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteSh [...] adds c9a31109e73 [llvm-mca] Avoid exposing index values in the MCA interfaces. adds 409ea28c474 [tools] Introduce llvm-strip adds b1872a26170 [WebAssembly] Ensure all .debug_XXX section has proper symb [...] adds da8f6959d96 [SelectionDAG] Transfer DbgValues when casts are optimized [...] adds 694780d67ee [llvm-rc] Fix alphabetical order of cases. NFC. adds 526033340b9 [llvm-rc] Exclude padding from sizes in versioninfo resources adds ab499d8976c [llvm-rc] Allow optional commas between the string table in [...] adds 31dc80fca0c [llvm-rc] Implement the BITMAP resource type adds d1d32f238d7 [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classes adds 6441549f058 [llvm-rc] Fix build: missing 'override'. adds 6608b6daee5 [tools] Adjust the lit config for llvm-strip adds 388124a55a0 [llvm-mca][x86] Remove addsubpd from SSE2 tests adds 75acc73db13 Remove explicit setting of the CFI jumptable section name, [...] adds 6dcc5db09e8 [DagCombiner] Not all 'andn''s work with immediates. adds e8d53c5b015 [DAGCombiner] Masked merge: enhance handling of 'andn' with [...] adds f6638d30e82 [tools] Add missing test dependency adds 5a8bc70a2d0 AMDGPU/GlobalISel: Don't try to lower hull shaders adds 481686fbc11 [MachineVerifier][GlobalISel] NFC, Improving MO printing an [...] adds 297777e34fd [MachineVerifier][GlobalISel] Checking that generic instrs [...] adds 07e155ea6ab Follow Up on [MachineVerifier][GlobalISel] NFC, Improving M [...] adds 5d61ed94175 Revert r330742: Let TableGen write output only if it change [...] adds f21558f73af [MC] ELFObjectWriter: Removing unneeded variable and cast adds 0af44d69392 [WebAssembly] MC: Use existing MCSymbol.Index field rather [...] adds e6569f0a341 [NewPM] Emit inliner NoDefinition missed optimization remark adds 106d54d2061 [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>) adds 507450209fc [MachineVerifier][GlobalISel] Verifying generic extends and [...] adds ea4e5922336 [DebugInfo] Accept `S` in augmentation strings in CIE. adds a4f2996da07 [x86] Introduce the pconfig instruction adds e5fae2e7c31 [LCSSA] Do not remove used PHI nodes in formLCSSAForInstructions adds ceb5c6fec6d [x86] Introduce the enclv instruction adds aa4eef7aaba Object: Find terminator correctly when reading long filenam [...] adds 76e573dd134 [llvm-rc] Don't strictly require quotes around external file names adds 30962eca38e [X86][CET] Shadow stack fix for setjmp/longjmp adds 4bd3e6c6db4 [X86] Mark all byval parameters as aliased adds f100a5dc31e [mips] Correct clo/clz predicates adds 3372396f708 [AArch64] Disallow vector operand if FPR128 Q register is r [...] adds 5a886bf8e67 [mips] Mark various memory instructions as being in microMI [...] adds 21150634b02 [X86] Add SchedWriteFTest/SchedWriteVecTest TEST scheduler classes adds 91ba6e73386 [AArch64][SVE] Asm: Support for LD1R load-and-replicate sca [...] adds 155f943ddf7 [X86] Add vector masked load/store scheduler classes (PR32857) adds 9affe20dc07 [llvm-rc] Update a stale comment. NFC. adds 681b39081c3 [llvm-mca][x86] Add div/idiv, mul/imul and inc/dec/neg/nop [...] adds 34a5efcdc51 [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementati [...] adds 04538fb3097 [llvm][x86] SandyBridge/IvyBridge don't support BMI1/BMI2 adds 7b20fe2cfa3 [X86] Split off WriteIMul64 from WriteIMul schedule class ( [...] adds 460bf85fc56 [mips][msa] Pattern match the splat.d instruction adds 6c961de3ad3 [X86] Tag PCONFIG instruction with WriteSystem scheduler class adds 7de8fd2b743 [AMDGPU] Added checks for dpp_ctrl value adds 680a6e84e31 [llvm-objcopy] Fix exit code adds 4ad2dcac818 [PowerPC] Unify handling for conversion of FP_TO_INT feedin [...] adds 14bd1f8c838 [CodeGenPrepare] Move Extension Instructions Through Logica [...] adds 147e51b2047 [Power9]Legalize and emit code for truncate and convert QP to DW adds f05af5da1d4 AMDGPU: Use eraseFromParent to delete am instruction when i [...] adds 80ff171fdc1 [Power9]Legalize and emit code for truncate and convert Qua [...] adds 438411c5078 DAG: Use correct shift width type adds 722943122f9 AMDGPU: Fix broken dynamic vector indexing for packed types adds d60939522ed [docs] Fix a typo in KaleidoscopeJIT tutorial adds 44e89707783 AMDGPU: Don't use undef in a test adds 9454ffe572e AMDGPU: Fix broken check lines in test adds 38dc71ca1e1 [Power9]Legalize and emit code for truncate and convert QP [...] adds 34e0b6a1d63 [AMDGPU] Provide machine -> name mapping adds 3ce25b339f5 [LV] Fix for PR37248, Broadcast codegen incorrectly assumed [...] adds 524159d4bed Changing constants in a test (NFC) adds c97ab8f1e3a [Coverage] Take filenames into account when loading functio [...] adds 793104bc6dc [llvm-rc] Add support for all missing dialog controls adds 0cb4ac08f0b [AsmPrinter] Allow emitting codeview for any windows target adds 483fd529ecc Revert "[X86][CET] Shadow stack fix for setjmp/longjmp" adds d7b3d72efa7 [globalisel] Add a combiner helpers for extending loads and [...] adds 024c2ba46da [GlobalISel][Legalizer] More concise and faster widenScalar, NFC adds add75ccccd9 [globalisel] Correct r331816 to check the opcode before cal [...] adds ec588866c67 MC: Remove dead code. NFCI. adds 33b646c4289 [SimplifyCFG] Fix a crash when folding PHIs. adds 31dcd106587 [CMake] Use CMAKE_OBJCOPY and CMAKE_STRIP to externalize de [...] adds db9d4d0ae2b Inline contents of LLVM_XRAY_TOOLS variable into its only use. adds 5a09fce19db Support a funclet operand bundle in LowerInvoke adds 819f32ff4c4 Make llvm-cfi-verify CMakeLists.txt formatting more consist [...] adds 86a524c901c fix path to llvm-cfi-verify unittests in docs adds e0c7deb8d5f Make CMakeLists.txt formatting more consistent with the res [...] adds 99deb0bcb19 [RuntimeDyld][MachO] Properly handle thumb to thumb calls w [...] adds 3ce5bb7fe7b Revert r331819 [GlobalISel][Legalizer] More concise and fas [...] adds a8a13bc662a [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. adds 085342284ca [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr. adds 24abe71d71a [DebugInfo] Examine all uses of isDebugValue() for debug in [...] adds e08d6cea343 Revert r331816 and r331820 - [globalisel] Add a combiner he [...] adds 17b8afd9d78 [X86] Combine (vXi1 (bitcast (-1)))) and (vXi1 (bitcast (0) [...] adds 06dc7eafe28 [DebugInfo] Fix test failed due to new DISubprogram attributes. adds 8b5d7e60653 [InstCombine] snprintf optimizations adds 778613a69e2 [LLVM-C] Correct types in Go bindings adds 819122349a2 [MergedLoadStoreMotion] Fix a debug invariant bug in mergeStores adds 8d6ead21e63 [DebugInfo] Fix test failed due to debug-label-mi.ll and de [...] adds ca76ce5f8ae Add a test for r331746. adds ad7a1f939cb [COFF] Improve correctness of def parsing for GNU features adds beccc078200 [mips] Move conditional moves out of isCodeGenOnly adds 1c881df6d1d [X86] Cleanup WriteFStore/WriteVecStore schedules adds fa04d8ba31b [DebugInfo] Mark tests using -debug-only as REQUIRES: asserts adds be423e4d7b0 Revert "[InstCombine] snprintf optimizations" adds d80aa1ad9d9 [CostModel][X86] Split off SLM checks adds 1ed49633b37 DWARFVerifier: Check "completeness" of .debug_names section adds 2a79fdd9449 Revert "DWARFVerifier: Check "completeness" of .debug_names [...] adds 1cbc8c01e86 Remove 'abi-breaking-checks' lit feature. adds cae204293af [AArch64] Improve cost of vector division by constant adds 81ac9c63eee [Support/Path] Make handling of paths like "///" consistent adds ac455c2fd04 [LV] Add lit testcase for bitcast problem. NFC adds 4549ddbb684 [Hexagon] Simplify MCCodeEmitter, move data to tables adds 277cedda80e APFloat/x87: Fix string conversion for "unnormal" values (pr35860) adds 6b025ac6855 [LV] Change MaxVectorSize bound to 256 in assertion, NFC otherwise adds fdba35eadd9 [Hexagon] Fix sanitizer error about using -1u in variable o [...] adds 8d032600bea [DAGCombine] Change store merge candidates check cut off to 1024. adds 3b0f8c0f128 [InstCombine] snprintf optimizations adds 60c5c559099 [DAGCombiner] In visitBITCAST when trying to constant fold [...] adds 388f53488a9 llvm-mca: Add missing includes adds f66d8c2e1aa Reapplying r331819 [GlobalISel][Legalizer] More concise [...] adds 1b557b33fa1 [llvm-rc] Allow -1 for control IDs in old style dialogs wit [...] adds 0aa38c8f714 [llvm-rc] Add support for the RCDATA resource type adds d5e933640f8 [llvm-rc] Handle C preprocessor output adds 33cab0605c8 AMDGPU: Stop special casing constant indexes of extract_vector_elt adds 61baf50339f [Hexagon] Check the end of the correct container (fix typo) adds e2f4d3fdb72 AMDGPU: Add combine for trunc of bitcast from build_vector adds 4581920e467 [X86] Merge instregex patterns to reduce InstrRW compile time. adds 35d3d7ee6fe [X86] Fix Broadwell's Shuffle256 schedule classes load late [...] adds c7ccc04824d AMDGPU: Partially shrink 64-bit shifts if reduced to 16-bit adds 5d4101dba49 AMDGPU: Handle partial shift reduction for variable shifts adds 3a2083a2cd8 [Hexagon] Add patterns for vector shift-and-accumulate adds c31fde08240 AMDGPU: Ignore any_extend in mul24 combine adds 030b9437a70 [AMDGPU] Support horizontal vectorization of min/max. adds dd5a608d8b6 [llvm-objcopy] Add --strip-symbol (-N) option adds 051da15b1e7 [GlobalISel][Legalizer] Widening the second src op of shift [...] adds 0f4cc998913 [ARM] Add support for SETCCCARRY instead of SETCCE adds c1c66c07051 [InstCombine] Teach SimplifyDemandedBits that udiv doesn't [...] adds eb0a9668703 [InstCombine] Widen guards with conditions between adds 1e84bc6951c [AggressiveInstCombine] convert a chain of 'and-shift' bits [...] adds 6889537ce7b [PhaseOrdering] remove stale comments; NFC adds 2f825676aaf [NVPTX] Added a feature to use short pointers for const/loc [...] adds 2a434d1ea3e [LIT] Handle xml characters in test names adds 296c5bb5965 [Inscombine] fix a signedness warning which broke -Werror builds adds eeb8057fb5f Refactor test incase results are backwards adds 46f1489f18b [LIT] Add the missing file adds 324b19dcac7 [InstCombine] Use APInt::getBitsSetFrom to shortern a line [...] adds 6cdec699094 [InstCombine] Reorder an if condition to put a cheap check [...] adds 6b81d891992 SCEV] Do not use induction in isKnownPredicate for simplifi [...] adds a02e1ac80b0 [SCEV] Add missed Test for rL331949. adds ac2df64c27b Fix tests added in r331924 so that they work on Windows. adds c31146b1794 [X86] ptwrite intrinsic adds 0f6b0335f94 [mips] Correct the predicates of cvt.fmt.fmt instructions adds b82663119e7 [DWARF] Rework debug line parsing to use llvm::Error and callbacks adds b83e520deee [InstCombine] Only propagate known leading zeros from udiv [...] adds 74080eb9446 [CFLGraph] Fixed Select instruction handling adds 290ef8aa416 Fix signed/unsigned comparison warning and print format adds b50edb96e4a [DWARF] DWARFDebugLineTest: fix a few more signed/unsigned [...] adds 1886be969a5 [DWARF] dwarfgen::LineTable::writeData(): pacify -Wcovered- [...] adds f1d346e4c5d [DWARF] DwarfGenerator.h LineTable: explicitly mark DG as unused adds e72f853489c [DAG] Avoid using deleted node in rebuildSetCC adds 6340f7f814b [DWARF] Remove unused member and fix(?) the unit-tests on b [...] adds e21fc646bed Don't redefine a bunch of defines from llvm-config.h in config.h. adds d948fa6f180 [x86] add tests for maxnum/minnum intrinsics with nnan; NFC adds f9bd414b6dd [x86] fix test names; NFC adds 0ccb7f4a4d9 [PR37339] Fix assertion in FunctionComparator::cmpInlineAsm adds 88b5ce0eea8 [DSE] Teach the pass about partial overwrite of atomic memo [...] adds 2a96212ada6 [x86] fix fmaxnum/fminnum with nnan adds 9d9bed7ba9d [llvm-objcopy] Add tests for help messages adds 316c9702852 [mips] Accept 32-bit offsets for lh and lhu commands adds 34b34574ba1 [mips] Accept 32-bit offsets for ld/sd/lld commands adds ae65e14fbd5 [InstCombine] regenerate full checks; NFC adds a5819b50a23 [X86] Split WriteVecALU/WriteVecLogic/WriteShuffle/WriteVar [...] adds 004b1c902d2 [X86][SNB] Fix typo in PEXTRDmr instregex, was missing VPEXTRDmr. adds d681e1aa7b3 [PM/LoopUnswitch] Avoid pointlessly creating an exit block set. adds 70b76a172d4 [WebAssembly] Create section start symbols automatically fo [...] adds 318896f049c [X86][Znver1] Remove unnecessary SchedWritePMULLD InstRW ov [...] adds 8d1235ff266 [WebAsembly] Update default triple in test files to wasm32- [...] adds 42400512520 [LLVM-C] Move DIBuilder Bindings For Temporary MDNodes adds aaea1bf6a17 [LLVM-C] Add Accessors for Common DIType and DILocation Properties adds 48ccf8506ac [CGP] Split large data structres to sink more GEPs adds 8bd2392fe8e Add regression test for r331976 adds 8b40a2e52b4 [X86] Convert/Merge more instregex patterns to reduce Instr [...] adds 5e8c19b5ff7 [X86] Initialize HasPTWRITE member of X86Subtarget adds 5dc9b6a1fdf [InstCombine] add minnum/maxnum tests (PR37404, PR37405); NFC adds 55a66360d5e [InstCombine] Moving overflow computation logic from InstCo [...] adds 3dc44a9d48d [DWARF] Fixing a bug in DWARF v5 string offsets tables wher [...] adds 87d94cc8a79 [InstCombine] add folds for minnum(-a, -b) --> -maxnum(a, b) adds 70d549800ca AMDGPU/GlobalISel: Enable TableGen'd instruction selector adds 07e5114430d [LLVM-C] Consolidate llgo's DIBuilder Bindings adds ce448553221 AMDGPU/GlobalISel: Implement select() for G_BITCAST s32 <-- [...] adds c86ac9aca98 Revert "[InstCombine] snprintf optimizations" adds fd645d3d089 [X86] Add new patterns for masked scalar load/store to matc [...] adds 04cf0d7c9c3 [WebAssembly] Initial Disassembler. adds ff56eb4dc5c [InstCombine] Replace an 'if' that should always be true wi [...] adds fd0a9c3d8a0 [LIT] Move xunit tests tests into their own location, and a [...] adds 48fd38c5734 [STLExtras] Add distance() for ranges, pred_size(), and suc [...] adds f2885f72974 [SampleFDO] Don't treat warm callsite with inline instance [...] adds 9470bd67fab Refactor xunit test case builder to not use as much str addition adds fcfa4b82779 Support Unsupported Tests in xunit output adds a88573cfc24 [InstCombine] Add tests for cases where we don't recognize [...] adds 3d02bd7c77a Register NetBSD/i386 in AddressSanitizer.cpp adds dcf0b3b7b3e [sanitizer-coverage] don't instrument a function if it's en [...] adds fae67c2efe6 [Support] Add docs for 'openFileFor{Write,Read}' adds dcb2807d870 [Coroutines] PR34897: Fix incorrect elisions adds f3684c59a8a [llvm-objcopy] Update remove-section.test adds e12166f8ad8 [X86] Remove and autoupgrade the avx512.mask.store.ss intrinsic. adds 3e6c331c766 [llvm-strip] Add support for -remove-section adds a915f005cd6 AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI adds 4ced77c3680 [IRTests] Verify PDT instead of DT adds 5b80d9d3cd3 [APFloat] Set losesInfo on no-op convert adds fb6b06bda18 [X86] Added scheduler helper classes to split move/load/sto [...] adds dd5223777fd [InstCombine] Unify handling of atomic memtransfer with non [...] adds 8e53f98c8b6 [X86] Split WriteF/WriteVec Move/Load/Store scheduler class [...] adds e0189536931 [X86][SLM] Vector stores only use the MEC port. adds a884ad2442c [mips] Enable disassembly of fused (negative) multiply add/ [...] adds d40f63039be Remove unused SyncExecutor and make it clearer that the who [...] adds b75b6479e7f [Reassociate] Prevent infinite loops when processing PHIs. adds a345b842f8b Use iteration instead of recursion in CFIInserter adds 74d22cb9f51 [mips] Rename Filler to MipsDelaySlotFiller and initialize [...] adds 14a7c1a0624 [AArch64] Fix performPostLD1Combine to check for constant l [...] adds a1da9452e7e [X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classes adds d2bdcd6f8ae [Analysis] Validate the return type of s(n)printf like libcalls adds 0d102410ca8 [RISCV] Support .option rvc and norvc assembler directives adds 8ab14800c3f [X86][BtVer2] Model ymm move as double pumped instructions adds 5905ca8b1ef [InstCombine] snprintf optimizations adds d92ec5fa040 make add_llvm_fuzzer calls slightly more consisten with oth [...] adds 29909981224 [LIT] replace output escapes wit a cdata block adds f6585e9bd31 [DAGCombiner] Factor out duplicated logic for an extload co [...] adds bdb4eca65ea [DAGCombiner] Set the right SDLoc on a newly-created sextlo [...] adds c230f0300b2 [DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N) adds 4343791f3ea Move standard library inclusions to after internal inclusions. adds e65f74fb3ee [InstCombine] Handle atomic memset in the same way as regul [...] adds c4c7b41b7ca [DAG] reduce code duplication; NFCI adds 3d133176355 [AMDGPU] Fix compilation failure when IR contains comdat adds 9d11c652b08 [Split GEP] handle trunc() in separate-const-offset-from-gep pass. adds c36d516fd6b [X86] Remove and autoupgrade a bunch of FMA instrinsics tha [...] adds 52d265c4ad0 AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast [...] adds b7c28298e2d Overhaul unicode handling in xunit output adds 1dd3afa36a6 [DAG] clean up flag propagation for binops; NFCI adds a09145e6dda [CodeExtractor] Allow extracting blocks with exception handling adds 8e3c0384fdf [MemorySSA] getIncomingValueForBlock should return a MemoryAccess. adds 6269b4f3a65 AMDGPU/GlobalISel: Implement select() for >32-bit G_STORE adds 8d4503a87fc [DAG] add convenience function to propagate FMF; NFC adds 9a50c9b3df7 Add the message attribute to skipped adds 7e911dad6c8 Requirements can have & in them! adds cf1a1cbbf12 [AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler adds 105e762f2a6 [IDF] Enforce the returned blocks to be sorted. adds 0daa661eb92 Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." adds 57cc768ae7a [X86] Remove some unused masked conversion intrinsics that [...] adds d96a720ead4 [mips] Initialize the long branch pass for testing purposes adds 974a7014d8b [X86] Add WriteFCMOV scheduler class for x87 CMOVs adds db69401678c llc: don't call llvm_shutdown twice adds c1d2340df22 [NFC] Remove inaccurate comment adds d9314d95a57 Clear converters map after X86 Domain Reassignment to avoid [...] adds a9453146341 [x86] Remove a comment obviated by r330269. Should have del [...] adds fbe091db86b [X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics t [...] adds 3d518c82963 [X86] Remove an autoupgrade legacy cvtss2sd intrinsics. adds e44514734fd [X86] Remove some unused CHECK lines from tests. adds 44156e3f614 [X86] Add some load folding patterns for cvtsi2ss/sd into i [...] adds d8ca4dd7115 [NFC] MIR-Canon: switching to a stable string sorting of in [...] adds 0ff8dbe4d6c Fixing build bot error: adding const qualifiers to std::sor [...] adds f3c5d2fc2e1 AMDGPU: Make undef legal for v2i16/v2f16 adds 0d44e5b362f AMDGPU: Rename OpenCL lowering pass to be R600 specific. adds 094f39bdd5b Follow-up to rL332176 by adding a test case for PR37264. adds e6d357b0ce9 [X86] Remove and autoupgrade masked vpermd/vpermps intrinsics. adds 03e25daf22f [X86] Add missing test for the InstCombines of pclmulqdq. adds 4105bd514aa [X86] Extend instcombine folds for pclmuldq intrinsics to t [...] adds dc05051a07a [X86] Add fast-isel test cases for _mm_cvtu32_sd, _mm_cvtu6 [...] adds 4aa6763ade3 [X86] Add patterns for combining movss+uint_to_fp into the [...] adds d4541505a59 [X86] Remove and autoupgrade the cvtusi2sd intrinsic. Use u [...] adds 3d2aa2d1309 [X86] Cleanup a multiclass that doesn't need as many parame [...] adds 711dd879a41 [X86] Add fast isel test cases for the clang output for 512 [...] adds 558d7248e08 Correct compatibility with the GNU Assembler's handling of [...] adds 426849be4f6 [llvm-ar] Make PositionalArgs static. adds b5e7dcccf93 [LLVM-C] Add Bindings For Module Flags adds bd7040f0a75 Test commit access. adds 6cf914db39c [llvm-exegesis] Allow lists of BenchmarkResults to be parse [...] adds d91853e2c44 [mips] Correct the predicates of indexed floating point sto [...] adds 431f230ab6c [llvm-exegesis] Add an analysis mode. adds a0b75d92d71 [llvm-exegesis] Fix a warning in r332221 adds 4f14c9bd165 [llvm-exegesis] Revert accidentally commited code. adds e2c1bdb4dd5 [AArch64][SVE] Extend parsing of Prefetch operation for SVE. adds e17809bf50a Re-land r332230 "[llvm-exegesis]Fix a warning in r332221" adds b97a8ca8d61 Fix "not all control paths return a value" MSVC warning. NFCI. adds fc2b453631f Fix Wdocumentation warnings. NFCI. adds 0818e789cb5 Rename DEBUG macro to LLVM_DEBUG. adds 65e6faea890 [mips] Add missing test case from r332227 adds d7960310017 [AggressiveInstCombine] avoid crashing on unsimplified code [...] adds 8d9ab7e57d5 Docs: Fix the title underline too short. adds 3f8354c90ef [CodeGen/AccelTable]: Handle -dwarf-linkage-names=Abstract [...] adds 40a24a84872 [llvm-mca] Improved support for dependency-breaking instructions. adds 29ab6ce3aab [AArch64] Improve single vector lane stores adds 3b3c5030615 [NFC] [Power] Fix instruction format for xsrqpi adds fb6636e6dac [llvm-mca][x86] Add and/not/or/xor instruction tests adds 08ef88f001b [mips] Fix the predicates of round, ceiling, floor and trunc. adds f206c4fa84f [Hexagon] Avoid predicate copies to integer registers from [...] adds 6df0758cb97 [llvm-mca][x86] Add scalar nt-store instruction tests adds edf2f134479 [BranchFolding] Allow hoisting to block with a single condi [...] adds f33e915b87e [X86] Remove GCCBuiltin from the intrinsics that clang stop [...] adds 35ba3b0bbd6 [X86][BtVer2] Fix MMX/YMM integer vector nt store schedules adds 6d6fe22ff78 [llvm-mca][X86] Add missing SSE4A test file adds 28daf68df74 [X86] Remove and autoupgrade avx512.vbroadcast.ss/avx512.vb [...] adds fb89f7ec00d alphabetize list adds 5fdb3b2e0ac [X86] Add NT load/store scheduler classes adds 27ff622b217 Remove a workaround that should be unneeded after r202806. adds 32200805330 Inline a few CMake variables into their only uses. adds 86cf23258e7 Hexagon: Put relocations after instructions not packets. adds 1a0893616d1 [Hexagon] Add a target feature for memop generation adds 989920616f4 [DWARF] Factor out a DWARFUnitHeader class. NFC adds b4e7a421357 [Hexagon] Add a target feature for generating new-value stores adds 415c71be4e6 [Hexagon] Add a target feature to control using small data section adds e6979f263bd [PowerPC] add more tests for FMF propagation; NFC adds 086018dbbeb [CodeView] Improve debugging of virtual base class member v [...] adds 962213d3ac2 [llvm-rc] Add missing inputs for tag-icon-cursor.test. adds 4fc07cda7da [ARM] Back up R4 and LR if calling the stack probe function adds 8fa6fcaf5a3 [Option] Fix PR37006 prefix choice in findNearest adds 26b9bb11663 [AArch64] enhance test to show FMF loss; NFC adds abb2646f5ab [InstCombine] fix crash due to ignored addrspacecast adds 67ebb421ce0 Revert "[Option] Fix PR37006 prefix choice in findNearest" adds b67613ea0a9 [WebAssembly] Move toString helpers to BinaryFormat adds 9897943c6c5 [CommandLine] Error message for incorrect PositionalEatArgs usage adds b12dd1fa59b [Debugify] Add -debugify-each for testing each pass in a pipeline adds 77b93b3504d Fix debug build by adding missing dependencies on libBinaryFormat adds ca3e13c8383 [NFC] Add const to method signature adds 90842deba1c [RISCV] Define FeatureRelax and shouldForceRelocation for R [...] adds b6cd9b4a614 [X86] Revert part of r332267: Remove GCCBuiltin from the in [...] adds 54e2a7e2a56 [NFC] Update comments adds 929e74568e3 [NFC] pull a function into its own lambda adds ac0fd1e0b35 [X86] Add fast isel tests for some of the avx512 truncate i [...] adds ce6387468a3 [llvm-rc] Read the Planes/BitCount fields from BITMAPINFOHE [...] adds 370633f2f2d [llvm-rc] Add support for parsing memory flags adds 4021505db6f [llvm-exegesis] Check perf event validity. adds 6357b5f4058 [llvm-exegesis] InMemoryAssembler: handle return-less targe [...] adds 15038de7ec2 [llvm-mca] Add file header to RetireControlUnit.cpp. adds 3ba603c98b8 [X86] Improve unsigned saturation downconvert detection. adds bc7b3f4d5d7 [llvm-mca] Remove unused include header files. NFC adds e9a999eea8f [mips] Fix predicates of mfc1, mtc1 instructions adds 3319b10cf9b [mips] Add disassembly support for comparison instructions adds 4c447f334e5 [mips] Fix formatting of floating point conversion patterns adds 51c1b4007db [MergeFunctions] Fix merging of small weak functions adds fc0362a3f21 [llvm-exegesis] Add an analysis mode. adds ea4e63b33c1 Fix r332344: only the native target is linked. adds a206567c6b5 Fix compilation under pre-c++14 gccs. adds 482be99a5b8 [llvm-mca][x86] Add F16C instruction tests adds bb3b3c2dfca [llvm-exegesis] Split AsmTemplate.Name into components. adds d3664eaf52d Reapply "DWARFVerifier: Check "completeness" of .debug_name [...] adds 8206b0c26f2 Fix broken asan Support tests adds 5fe8b27775a [llvm-objcopy] Add --keep-symbol (-K) option adds c2faa707779 [X86] Split off F16C WriteCvtPH2PS/WriteCvtPS2PH scheduler classes adds f46201df376 [DAG] propagate FMF for all FPMathOperators adds 3529d77f3f2 [llvm-mca] Strip leading tabs and spaces from instruction s [...] adds 1cc744a2e52 [mips] Mark select instructions correctly adds 711424181c4 [Hexagon] Remove unused flag from subtarget and (non)corres [...] adds 9b2ede65de2 [AArch64] Fix mir test case liveins info. adds 3069e4ead50 Rename three cxx files in unittests to cpp. adds b50d67b7315 [Hexagon] Remove unused function from subtarget adds 1e7a393cc41 [InstCombine] add multi-use shuffle tests and regenerate ch [...] adds faad403e268 [InstCombine] fix binop-of-shuffles to check uses adds 04291304897 [X86] Split WriteCvtF2F into F32->F64 and F64->F32 schedule [...] adds e8cfe2231c5 AMDGPU: Add disasm tests for deep learning instructions + f [...] adds d9158124030 AMDGPU/GlobalISel: Implement select() for G_FCONSTANT adds eebfacb84e6 [llvm-mca] use a formatted_raw_ostream to insert padding an [...] adds 26e0acdad08 [MemorySSA] Don't sort IDF blocks. adds 65de7bd1fee [llvm-rc] Add support for the optional CLASS statement for dialogs adds c9241855711 AMDGPU: Fix v_dot{4, 8}* instruction encoding adds 16952fe9058 Use perfect forwarding to deduplicate code in unit test. NFC. adds d5ae6a3f71c [x86][eflags] Fix PR37431 by teaching the EFLAGS copy lower [...] adds 1b9c9435361 [llvm-mca] Introduce a pipeline Stage class and FetchStage. adds 91518dd4d4f Nios2: Unbreak build. adds 201b4e47c38 [DAGCombine] Move load checks on store of loads into candid [...] adds 63f181a9143 [InstCombine] add more tests for binop-shuffle; NFC adds 8d19d135aff [AArch64] Improve single vector lane unscaled stores adds bcc9a743a62 [llvm-objcopy] Add --only-keep-debug as a noop adds e8d6f344458 [InstCombine] clean up code for binop-shuffle transforms; NFCI adds fd83828e5db Move helper classes into anonymous namespaces. NFCI. adds 0d00bdb5851 [msan] Instrument masked.store, masked.load intrinsics. adds 13ec17eb2e2 StructurizeCFG: fix inverting conditions adds 8037fc4d911 AMDGPU: Add a missing test for the 128-bit local addr space option adds 4883de9d879 [WebAssembly] Provide WasmFunction content offset information. adds 382e5e701dd [InstCombine] fix binop (shuffle X), C --> shuffle (binop X [...] adds 732896dd876 [AMDGPU] Fix handling of void types in isLegalAddressingMode adds 27b0d8a7623 [X86][SSE] Add tests for vector rotates by splat variable. adds b79d2cf9406 [MachineOutliner] Add optsize markings to outlined functions. adds d146023adda [Debugfiy] Print the pass name next to the result adds a76b6de3b8c [Debugify] Fix test failing after r332416 adds 942907df5b5 ARM: Deduplicate code and remove unnecessary declaration. NFCI. adds 3aa3080f8c4 ARM: Remove unnecessary argument. NFCI. adds ba7d439a19c Use not to catch unexpected pass as well as remove old test [...] adds 98ccabbf2a6 remove output xml incase it is leftover from another run adds 9cbab963e67 Fix LSR compile time hang. adds 1187b9b7a72 [DebugInfo] Only handle DBG_VALUE in InlineSpiller. adds b60356726cc Signal handling should be signal-safe adds 0302e7b44f0 Revert "Signal handling should be signal-safe" adds c69e3598576 [ObjCARC] Prevent code motion into a catchswitch adds a899e8e9e49 Remove unused variable introduced in r332336 adds c4ffad9aeb8 [Unix] Indent ChangeStd{in,out}ToBinary. adds 1d6e8c7fc3b [AArch64][SVE] Asm: Support for contiguous PRF prefetch ins [...] adds e36fcd2da13 [X86][SSE] Fix tests for vector rotates by splat variable. adds 13a2d87d4df [llvm-exegesis] Analysis: Display sched class for instructions. adds 19d438a7013 Emit a left-shift instead of a power-of-two multiply for ju [...] adds 9e38e3e26f4 Escape ]]> in xunit xml output adds 5ae14383e94 Fix unused variable warning in r332437. adds 468335283fd [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 [...] adds 13e8f305a95 [llvm-mca] Remove redundant includes in Stage.h. adds b25fd2f921c [AArch64] Support "S" inline assembler constraint adds 3f4a74f3e5d [llvm-exegesis] Add a flag to output analysis csv to a file. adds 54ec36dbf74 [mips] Add support for isBranchOffsetInRange and use it for [...] adds 75ca51beccf [llvm-mca] Regenerate tests after r332381 and r332361. NFC adds b1482594012 [GlobalISel][IRTranslator] Split aggregates during IR translation. adds f733c11f7a9 [LoopUnroll] Split out simplify code after Unroll into a ne [...] adds 4e8768feafb [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F6 [...] adds cb037efeac2 [SimplifyLibcalls] Replace locked IO with unlocked IO adds f8b36841ee3 AMDGPU: Custom lower v4i16/v4f16 vector operations adds f392447b194 [llvm-exegesis] Fix unused variable warning in release mode. adds fb66864554f [llvm-mca] Fix perf regression after r332390. adds 02815c96d34 [mips] Join existing scopes for DecoderNamespace (NFCI) adds a555456abe0 [mips] Simplify some of the predicate scopes for (negative) [...] adds a2173836acd [BasicAA] Fix handling of invariant group launders adds fad0c9b3b04 [llvm-mca] Move definitions in FetchStage.cpp inside namesp [...] adds 2c5ef979724 [AArch64][SVE] Asm: Support for gather PRF prefetch instructions adds db6ccb3ccd8 [ThinLTO] Add const qualifier to a couple of flag getter methods adds f90a5e079ca [ThinLTO] Make llvm-lto module ID numbering consistent with [...] adds 46a30b98c29 [InstCombine] allow more binop (shuffle X), C transforms adds f9deb984807 [AArch64] Gangup loads and stores for pairing. adds c2421e4a708 [AArch64][SVE] Improve diagnostics for vectors with incorre [...] adds 945003c7f91 [x86] add tests for DAG FP undef operands; NFC adds b994738de76 [AMDGPU] Change llvm.debugtrap to be a debug breakpoint tha [...] adds d51b116aa1f [x86] add run with unsafe global param; NFC adds 8e398a45d5e Give shared modules in unittests the platform-native extens [...] adds 92d4ba18bdc [DAG] Defer merge store cycle checking to just before merge. NFCI. adds 2aba6fc24e2 [DAG] Prune cycle check in store merge. adds 9e6d158bde2 [llvm-mca] Move the RegisterFile class into its own transla [...] adds 96936258fd5 Signal handling should be signal-safe adds 1222d6189da [Debugify] Tighten up the test for -debugify-each, NFC adds 846e93cfeec [X86][AVX512DQ] Use packed instructions for scalar FP<->i64 [...] adds cea056a56d5 [x86] preserve test intent by removing undef adds 55e74dfd39c [x86] preserve test intent by removing undef adds 90100323d04 [x86] preserve test intent by removing undef adds bdd960c78ab [Timers] TimerGroup::printJSONValues(): print mem timer wit [...] adds ad5afb18627 [Timers] TimerGroup::printJSONValue(): print doubles with n [...] adds 8e8e5993fe0 [Timers] TimerGroup: make printJSONValues() method public adds b03e023027f [Timers] TimerGroup: add constructor from StringMap<TimeRecord> adds 8c20b5f8296 Fix llvm::sys::path::remove_dots() to return "." instead of [...] adds 37efd329dc3 [X86] Fix typo in instregex for CVTSI642SDrr adds 8458016a404 [MachineOutliner] Don't save/restore LR for tail calls. adds 38b696a7eb3 [WebAssembly] MC: Ensure that FUNCTION_OFFSET relocations a [...] adds 51be45ab231 Fix up a misleading format warning. adds bc809c37df6 Fix small grammar-o. adds 7dc086936fa AMDGPU : Recalculate SGPRs when trap handler is supported adds e66042ff019 [X86][SSE] Reduce instruction/register usages for v4i32 vec [...] adds bbebdb95807 [Hexagon] Mark HVX vector predicate bitwise ops as legal, a [...] adds 5dc60d332df [Hexagon] Fix the order of operands when selecting QCAT adds 020c1e94a61 _WIN32 straggler I missed in r331127; no-op in practice adds 829baac8eae [MachineOutliner] Don't outline instructions that modify SP. adds 62014b88876 [NFC] WebAssembly build fix adds a6425cd4c8b [InstCombine] Fix the signature of fgets_unlocked. adds 398f674fff0 [ARM] preserve test intent by removing undef adds f57d10b7e5d [ARM] preserve test intent by removing undef adds 8aecd6a7a68 [AArch64] preserve test intent by removing undef adds 1cb21c3fcb2 [WebAssembly] Remove unused headers in MCWasmObjectWriter adds 2017c135c0f [X86][SNB] Remove unnecessary CVT InstRW overrides adds 5cb89e921d0 [ARM] preserve test intent by removing undef adds 9b35a3acde2 [ARM] preserve test intent by removing undef adds 9be09777af7 [ARM] preserve test intent by removing undef adds 34b5ae7518d [X86] Update SNB/generic scheduler tests missed from rL332536 adds bb60b65608e [ORC] Rewrite the VSO symbol table yet again. Update relate [...] adds 2a77a185014 [NFC] WebAssembly build break #2 adds 1aa48506b9e [Thumb] preserve test intent by removing undef adds 9658229e848 [Thumb] preserve test intent by removing undef adds fa475c558d9 [PowerPC] preserve test intent by removing undef adds 309c9c43a7a [Hexagon] preserve test intent by removing undef adds ca6a4d968e0 [STLExtras] Add size() for ranges, and remove distance() adds 7b227c4398f Revert 332508 as it caused problems in the clang test suite. adds 3e976e68067 [CodeGen] Use MachineInstr::getOperand(0) instead of gets t [...] adds bf20a75b813 [WebAssembly] Fix the opcode number for i64.load16_u. adds 31b4f49b9f4 [AMDGPU] Move lsr test. NFC. adds 69f1013a11e Mark test with "REQUIRES: shell" since it directly invokes [...] adds 6e244de1d7c [Thumb2] fix typo in test from r332548 adds da555b0e240 [CMake] Support building shared library for Fuchsia adds 06501845178 [X86] Add OptForSize to a couple load folding patterns. Rem [...] adds d2427ff0af6 [RISCV] Add support for .half, .hword, .word, .dword directives adds 7244daec7e4 [SROA] pr37267: fix assertion failure in integer widening adds 9b79c170c15 [SROA] Handle PHI with multiple duplicate predecessors adds 33d415b1595 [llvm-exegesis] Update to cover latency through another opcode. adds 9bb99f85e4a Revert r332579 "[llvm-exegesis] Update to cover latency thr [...] adds a925a3b1249 [Analysis] Only use _unlocked stdio functions on linux adds fadab83bc04 Require DominatorTree when requiring/preserving LoopInfo in [...] adds 1963cc1ac1e [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 [...] adds f4a7407e71b [X86][SNB] Minor scheduler cleanup adds 4f11b743f47 reland r332579: [llvm-exegesis] Update to cover latency thr [...] adds 8603d60d157 Fix r332592 : X86 tests should use the X86 target, not the [...] adds c67506a2fd5 [llvm-mca][X86] Add ADX test files adds 8f090f67c05 [llvm-exegesis][NFC] Remove dead function. adds c42065aa9cf [SystemZ] Commenting (NFC) adds 4cdd921c673 [llvm-exegesis] Disable the tests failing on buildbots whil [...] adds 1e034263107 [llvm-exegesis] Analysis: detect clustering inconsistencies. adds acf3f6ed485 [llvm-mca] add flag -all-views and flag -all-stats. adds 3c529c01cb7 [llvm-exegesis] Disable failing ARM assembler tests. adds 87225e582ec [X86] Split WriteADC/WriteADCRMW scheduler classes adds efebb47c704 [Hexagon] Use addAliasForDirective for data directives adds 0ade31e6a19 [llvm-exegesis] Write out inconsistencies to a file. adds 0fa09b6c22e In thin and full LTO + CFI, direct function calls may go th [...] adds 234ed79cbaf [llvm-exegesis] Remove redudant explicit template instantiations. adds eb1647b75b4 [llvm-mca] Hide unrelated flags from the -help output. adds fdf32950c67 [X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like [...] adds 938d5932072 [RISCV] Set isReMaterializable on ADDI and LUI instructions adds 4acf19a46be [llvm-mca][X86] Add CMOV test files adds 90c9fa065a1 [InstCombine] Propagate the nsw/nuw flags from the add in t [...] adds 6209d969a23 [mips] Add support for Global INValidate ASE adds ce74ac30674 AMDGPU/SI: Handle infinite loop for the structurizer to wor [...] adds 01ff7b72c9e [X86] Split WriteCMOV + WriteCMOV2 scheduler classes adds a1fecd54c57 [llvm-mca] Add an example showing how to get Intel assembly syntax adds cce04b3a5cd [CMake] Make optimizing sanitizer builds optional adds 49f3003c7f8 Fix typo in declaring code-block snippet adds e605bbd4c50 [CMake] Support runtimes in distributions adds 706668176ff [WebAssembly] MC: Fix typo in comment adds 69b60eb28a3 [RISCV] Implement MC layer support for the tail pseudoinstruction adds 19e6e2d1156 [AArch64] preserve test intent by removing undef adds 28e0f25edb0 [ARM] preserve test intent by removing undef adds b231180388e [ARM] preserve test intent by removing undef adds 03da9798c11 [x86] preserve test intent by removing undef adds 6c8d8d769f5 [RISCV] Separate base from offset in lowerGlobalAddress adds ac5db0d5645 [Debugify] Print the output to stderr adds b771c8e3d95 [llvm-pdbutil] Dump struct/class/union sizes in the minimal [...] adds c66bd0a4308 [x86] preserve test intent by removing undef adds c783a5d9374 [llvm-mca] Make Dispatch a subclass of Stage. adds 56649b7234b Add a limit for phi folding instcombine adds 1f4de6bc0a5 [LV][VPlan] Build plain CFG with simple VPInstructions for [...] adds 39bca8321b2 [AA] cfl-anders-aa with field sensitivity adds ceb92ae8110 ARC, Nios2: Silence build warnings. NFCI. adds 0d0bfa9754a [codeview] Include record prefix in global type hashing adds e78f10b99e0 [ORC] Make MaterializationResponsibility's constructor private. adds fe651d1a0e3 [ORC] Consolidate materialization errors, and generate them [...] adds 5b752cf527f [WebAssembly] Add Wasm personality and isScopedEHPersonality() adds d0e6e5a36e3 [pdb] Change /DEBUG:GHASH to emit 8 byte hashes. adds 761b193f297 Revert "[pdb] Change /DEBUG:GHASH to emit 8 byte hashes." adds 54a7d61d8c5 AMDGPU/SI: Don't promote alloca to vector for atomic load/store adds 55033b07cb7 Revert r332657: "[AA] cfl-anders-aa with field sensitivity" adds 18b3754c39c Support: Add a raw_ostream::write_zeros() function. NFCI. adds b26b734118b Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes." adds 4464e8f60fa [X86DomainReassignment] Don't delete IMPLICIT_DEF nodes adds ed72507052d [X86DomainReassignment] Don't compare stack-allocated value [...] adds c7cc20b7d70 [MachineOutliner] Count savings from outlining in bytes. adds 1074714292c Fix unused lambda capture. adds 3de2740e687 Tidy comment up a bit. adds 83650cacf7e Revert "Temporarily revert "[DEBUG] Initial adaptation of N [...] adds 6ff324a4d41 [asan] Add instrumentation support for Myriad adds 2135b33dc52 [llvm-objcopy] Fix formatting adds f5e705e8039 [X86DomainReassignment] Hopefully fix buildbot failure adds 5f0ee1d59d6 [LICM] Extend the MustExecute scope adds e27401501e0 [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeeds [...] adds 710be84a005 [llvm-exegesis] Fix compile error on VS. adds 0ec6e3688b8 [SimplifyCFG] Fix a debug invariant bug in FoldBranchToComm [...] adds 3447c1011df [SystemZ] Fold AHIMux in foldMemoryOperandImpl. adds 1fcee954a4f [X86][CET] Changing -fcf-protection behavior to comply with [...] adds 78c9c765abd [SystemZ] Fix commit message of previous commit. adds a739ddd3fee StackColoring: better handling of statically unreachable code adds 26520533457 [llvm-exegesis] Improve documentation. adds b8f0305c73f use standard llvm cmake formatting for targets defined in p [...] adds 4ccabdd4426 Add Script to match open Phabricator reviews with potential [...] adds e6bf54e91b4 [X86][ZnVer1] Cleanup more single match instregexs adds 5afb869f5f4 [ExynosM3] Fix scheduling info. adds cd0f3471ad8 [X86][SSE] Ensure float load/stores use the WriteFLoad/Writ [...] adds d35d2d4ce6f [X86][AVX] VEXTRACTF128mr store is a WriteFStoreX not WriteFStore adds 2e48b5a57e9 [X86][SSE] Ensure vector partial load/stores use the WriteV [...] adds 96a67f12563 [X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latency adds 7ac661e9474 [InstCombine] regenerate checks; NFC adds 7dcb3bf9877 [InstCombine] add tests for lack of abs/nabs canonicalization; NFC adds efaf55551ee MCSchedModel: Add comments to IssueWidth. adds 145062e42d4 [NFC] update coding standard links to HTTPS adds 5a95f873c19 [docs] Scudo documentation minor update adds 1c0183accbe [X86][BtVer2] Improve simulation of (V)PINSR values adds 849da555d22 Add remarks describing when a pass changes the IR instructi [...] adds 6af49b5c06f [X86] Update fast-isel test cases for _mm256_mask_cvtepi16_ [...] adds cdcd5e1cacc [MC] Relax .fill size requirements adds a39a917dbf9 Revert changes from D46265. adds ad7c2e9c6a1 [X86] Directly legalize v16i16/v8i16 vselect to vXi8 vselec [...] adds 69d22499d3e [X86] Add GPR<->XMM Schedule Tags adds a3fda621398 Reverted r332654 as it has broken some buildbots and left u [...] adds d5b9305f2a3 [Hexagon] Generate post-increment for floating point types adds 17a98146db3 MC: Change the streamer ctors to take an object writer inst [...] adds 9c871324f6d [Support] Avoid normalization in sys::getDefaultTargetTriple adds bb0eb9f136f AMDGPU/NFC: Set symbol's type that is coming from an argume [...] adds a7e652ad1a0 Delete a test that was missed in the revert r332747. adds ff2a8ccbe9d adding baseline fp fold tests for unsafe on and off adds a68d4cc279c Support: Simplify endian stream interface. NFCI. adds c2e06bab45f [NFC] Change cast from r332739 to a static cast adds eab311b6616 [DWARF v5] Improved support for .debug_rnglists (consumer). [...] adds edf5860e510 [msan] Don't check divisor shadow in fdiv. adds a576ca1044e Fixing build error introduced with r332759. adds 02babe8338e Addressing a couple of compiler warnings introduced with r332759. adds d0adb1411d6 [WebAssembly] Object: Add more error checking for object fi [...] adds e24d17420cc [InstCombine] Qualify a select pattern based transform to r [...] adds cdbb0ae52b7 AMDGPU: Add pass to optimize reqd_work_group_size adds c1a566a4939 Fixing buildbot error introduced with r332759. adds 22ecb3d7128 DAG: Fix crash on shift with large shift amounts adds 239df32c7dc [x86] add more FP with FMF simplification tests; NFC adds 2fd56915295 [MemDep] Fixed handling of invariant.group adds da5cef7c189 Constant fold launder of null and undef adds 6ebd054bb61 Dissallow non-empty metadata for invariant.group adds 461e372be69 Propagate nonnull and dereferenceable throught launder adds cae8a1ee2b3 Enable colored diagnostics in ninja builds when building wi [...] adds 9d697869aa8 Fix evaluator for non-zero alloca addr space adds 3fcac5a53b6 Fix build warning compiling TestPlugin on Windows and disab [...] adds 07541493d51 Un-revert "[Option] Fix PR37006 prefix choice in findNearest" adds 907b424daed Fix MSVC unused variable warning. NFCI. adds 9174d3e272d [MergeICmps] Don't crash when memcmp is not available adds 06b38392dd6 [IRCE] Fix miscompile with range checks against negative values adds 12e746778c9 [LLVM-C] Use Length-Providing Value Name Getters and Setters adds 0fbb8daf57c Re-revert "[Option] Fix PR37006 prefix choice in findNearest" adds b5081216738 [GlobalMerge] Exit early if only one global is to be merged adds 56669ed246d [X86] Add test cases to show missed rotate opportunities du [...] adds 04e4adf9682 [cmake] Add a switch to enable/disable bindings. adds 42ebf193bc9 [InstCombine] choose 1 form of abs and nabs as canonical adds e7c11b70931 [mips] Add microMIPSR6 ll/sc instructions. adds f1617020035 Revert 332750, llvm part (see comment on D46910). adds aa228ef4a35 [X86] Remove mask arguments from permvar builtins/intrinsic [...] adds 1181c40e0e2 [LLVM-C] Improve Bindings For Aliases adds 03f0196467b win: try to fix dia tests with newer msvc versions adds eb4186cca79 win: try more to fix dia tests with newer msvc versions adds 071d9bcd625 [X86][SSE] Support v4i32 rotations (PR37426) adds b3845567bd5 [mips] Merge MipsLongBranch and MipsHazardSchedule passes adds 48b86e9c04b Fix up a few grammar issues. adds 519b8ede8d3 [CVP] Require DomTree for new Pass Manager adds edeb7b8e33a [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passes adds 4026a5fa20c revert r332610, it breaks cfi, see D46326 adds b096d31bb68 ARM: be conservative when asked load/store alignment of wei [...] adds dd5fd7ff883 [X86][SSE] Add an assert to ensure that rotation amount is [...] adds 8b03f4d6d27 [DWARF] Refactor callback usage for .debug_line error handling adds 5bfef878299 [X86] - Avoid SFB pass - fix bug in updating the offsets fo [...] adds e9654fe6f7b [LLVM-C] Add DIBuilder Bindings For ObjC Classes adds b6c66c585ca [X86][BtVer2] Add a 'J' prefix to the PRF/RCU defs. NFC adds 8b5d01038b8 [llvm-mca] Removed an empty line generated by the timeline [...] adds 52d10193ef1 [InstCombine] Fix PR37526: MinMax patterns produce an infin [...] adds c2406964f33 AMDGPU/GlobalISel: Address post-commit review comments for r332379 adds a8e9721d8de MC: Change MCAsmBackend::writeNopData() to take a raw_ostre [...] adds 74bda0b7709 MC: Change MCAssembler::writeSectionData and writeFragmentP [...] adds 6152bb94fda [VPlan] Reland r332654 and silence unused func warning adds 8e93a9573ff MC: Change object writers to use endian::Writer. NFCI. adds fe5e50fc87d [AMDGPU] Add divergence analysis as a dependency for ISel adds 0d4292ff61e MC: Have the object writers return the number of bytes writ [...] adds 2e125e8f464 MC: Remove stream and output functions from MCObjectWriter. NFCI. adds 77438c3c98c [EarlyCSE] Improve EarlyCSE of some absolute value cases. adds cce1a88066f Fix ubsan bounds check failure. adds 815bbef5d21 MC: Extract ELFObjectWriter's ELF writing functionality int [...] adds 09ac21d393d MC: Separate creating a generic object writer from creating [...] adds 577615c652f [X86] Add test cases for missed vector rotate matching due [...] adds 4ef1841f206 MC: Extract a derived class from ELFObjectWriter. NFCI. adds f452183fa90 [X86] Add test cases for D47012. adds 74157fc710d [DebugInfo] Use absolute addresses in location lists adds dbe392a333e AMDGPU: Update GCCBuiltin names for DS FP atomic intrinsics adds 60fd99da883 MC: Introduce an ELF dwo object writer and teach llvm-mc about it. adds fe31db84cc7 [DebugInfo] Fix typo "DWARG" in test comment (NFC) adds 3f3ea23d0f7 Remove CMake workaround for LLD PR24476 which is no longer needed adds 9ffe073e982 CodeGen: Add a dwo output file argument to addPassesToEmitF [...] adds 8cf770479a0 [InstCombine] add tests for cast-of-select; NFC adds aadeae8d7a8 LTO: Replace split dwarf implementation that uses objcopy w [...] adds fc055acc89b [InstCombine] remove fptrunc (select) code; NFCI adds 2527cbcd297 Fix a make_unique ambiguity. adds 343a5212998 [X86] Remove masking from vpternlog intrinsics. Use a selec [...] adds ee78629f71a [X86] Remove some unneeded check lines that I copy and past [...] adds eb91413561e [X86] Simplify some X86 address mode folding code, NFCI adds e1d782bb775 [InstCombine] regenerate checks; NFC adds 6ee4a210cc5 [DAGCombiner] Use computeKnownBits to match rotate patterns [...] adds e0b0d5fab77 [ORC] Add IRLayer and ObjectLayer interfaces and related Ma [...] adds 1b804fe0ece [ORC] Remove the optional MaterializationResponsibility arg [...] adds 8b040c41219 [ORC] Lookup now returns an error if any symbols are not found. adds d9367a91972 [ORC] Preserve Materializing symbol flag during resolution. adds 6b03aa25cd5 [X86][AArch64][NFC] Add tests for vector masked merge unfolding adds 9ed66ee093d [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition. adds 6a15b1928a0 [DAGCombiner] isAllOnesConstantOrAllOnesSplatConstant(): lo [...] adds 6e0e0759900 [GlobalISel] Improving InstructionSelect's performance by r [...] adds 8cc89d08e58 Unbreak kaleidoscope example. adds 7625b981c5d Fix warning from r332654 with LLVM_ATTRIBUTE_USED adds 07a4eb640cf Revert r332907 "[GlobalISel] Improving InstructionSelect's [...] adds f7624abeb1f [llvm-objcopy] Add --strip-unneeded option adds 6e21f264951 [X86] Remove 128/256-bit cvtdq2ps, cvtudq2ps, cvtqq2pd, cvt [...] adds 6241099a8c3 Reapply r332907 "[GlobalISel] Improving InstructionSelect's [...] adds 78d8e193c34 [LKH] Add a replacement RTDyldLayer. adds 1948145a6a5 [ORC] Make some more operations on VSO private. These shoul [...] adds 2f6b67546d3 [DAG] fold FP binops with undef operands to NaN adds 6cfc1adc327 [CMake] Pass Clang defaults to runtimes builds adds 7d79fc6afb6 Revert "[llvm-objcopy] Add --strip-unneeded option" adds 714851ee61c MC: Remove dead code. NFCI. adds f02d6fd47c1 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" [...] adds 33b4099feb6 [GlobalISel][InstructionSelect] Removing redundant num oper [...] adds b77633aafe8 [WebAssembly] Fix fast-isel lowering illegal argument and r [...] adds 45250546737 AMDGPU: Make v2i16/v2f16 legal on VI adds 35aa7d25b6f [AMDGPU] Optimze old value of v_mov_b32_dpp adds ecdb8b5a00f [LoopVersioning] Don't modify the list that we iterate over [...] adds 08bf51ee2ac [LowerSwitch] Fixed faulty PHI node update adds 4c5582d7efe [x86] NFC Add some more shuffle-vs-trunc tests adds 1373401fc17 LangRef.rst: the "\01" prefix applies not just to variables adds 91eac1017f1 [TTI] Add uniform/non-uniform constant Pow2 detection to Ta [...] adds 48f3050c47b [mips] Correct the predicates of the cache and pref instructions adds 643e7f6c91a [mips] Merge MipsLongBranch and MipsHazardSchedule passes adds a38d19ff57b [llvm-exegesis] Analysis output uses HTML. adds 1e7d8b35077 [llvm-exegesis] Update doc to mention that the output is in html. adds f690e9b2671 [FastISel] Permit instructions to be skipped for FastISel g [...] adds 096b48f5145 [lit] Don't check output of commands used in `shtest-timeou [...] adds 8cf26099d73 [lit] Don't run `slow.py` in `shtest-timeout.py` test. adds 9f0686b6672 [lit] Try to make `shtest-timeout.py` test more reliable by [...] adds 851bb222e8b [InstCombine] Calloc-ed strings optimizations adds 3216d6ee259 [InstCombine] fix broken test adds 6e22163f52a [ORC] Move symbol-scanning and discard from BasicIRLayerMat [...] adds b296477a11d diff --git a/utils/TableGen/GlobalISelEmitter.cpp b/utils/T [...] adds f3598414d4c Reverting 332999 to get it a proper commit message adds 638915a37f9 [GlobalISel][InstructionSelect] Sorting MatchTable's first [...] adds 04a387aa0f5 [DWARFv5] Put the DWO ID in its place. adds 2c6a6699c3b [DebugInfo] Fix location list check in the verifier adds eda7c167ce4 [DebugInfo] Invert DIE order for range errors. adds eae2e16ab13 [NewGVN] Fix handling of assumes adds 8eff37b3dd1 [llvm-objcopy] Fix the behavior of --strip-* and --keep-symbol adds 831a9e91854 [Hexagon] Add patterns for accumulating HVX compares adds d88e86ef628 [InstCombine] move/add tests for sub with bool op; NFC adds 73026bde126 [MachineOutliner] Add "thunk" outlining for AArch64. adds ccf5904d1cf AMDGPU: Move AMDGPUTargetLowering::isFPExtFoldable() into S [...] adds 792c45b7cd6 [GlobalISel][InstructionSelect] Switching MatchTable over o [...] adds 6853db12178 Delete unused variable from r333015. adds 509312630dd AMDGPU: Fix v2f16 fneg/fabs pattern adds 15b63213e06 [InstCombine] Remove calloc transformations adds 46d48331d63 AMDGPU: Fix missing test coverage for some 16-bit and packed ops adds 0b44b42eaf2 [ORC] Add some comments to Layer.h. adds 5fd7b638b8d [llvm-mca] Move DispatchStage::cycleEvent to preExecute. NFC. adds 79d7eedd8c4 Delete empty test file adds f880cf0ebc6 [Coverage] Update CSS to make HTML reports copy-paste friendly. adds ac1173dabd4 [docs] Clarify usage of "vector" in Programmer's Manual. adds 71b0bb58ebc [InstCombine] move misplaced test file and regenerate checks; NFC adds c5aff608310 [InstCombine] use nsw negation for abs libcalls adds a3ccaa9b882 [WebAssembly] Add functions for EHScopes adds 38031eccca1 [GlobalISel][InstructionSelect] MatchTable second level gro [...] adds 1741de42851 [GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank adds fb0360d185d [InstCombine] [NFC] Added more tests for unlocked IO transf [...] adds 164e4fc900c SafepointIRVerifier is made unreachable block tolerant adds 7a26d28c417 [Sparc] Add mnemonic aliases for flush, stb, stba, sth, and stha adds 2e3226ade60 Fix aliasing of launder.invariant.group adds 17c3197f792 [LoopUnswitch] Fix SCEV invalidation in unswitching adds 0baaa616ba4 [RISCV] Correctly report sizes for builtin fixups adds 1df8a89077a [AArch64] Use addAliasForDirective to support data directives adds 8ee85f1e7af [Sparc] Use addAliasForDirective to support data directives adds e54d539419d [RISCV] Add symbol diff relocation support for RISC-V adds d8c359a4760 Add myself to CREDITS.txt adds 6be4e9f7036 Update my information in the CREDITS file. adds c671da0827f Remove DEBUG macro. adds 4d9795156d0 [X86][MIPS][ARM] New machine instruction property 'isMoveReg' adds 3d525a3f582 [llvm-mca] Print the "Block RThroughput" in the SummaryView. adds 273694c064c [llvm-mca] Fix header comments. NFC. adds e1ddf28f3f6 Silence warnings introduced with r333093 adds c058ba5c3a9 [InstCombine] Negate ABS/NABS patterns by swapping the sele [...] adds ce531b3cc47 [Dominators] Add PDT constructor from Function adds 8a3276d9b51 [InstCombine] Fold unfolded masked merge pattern with varia [...] adds ebceee2165b [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC) adds 310e78bb8fd StructurizeCFG: Adjust the loop depth for a subregion to or [...] adds e99b1c16bb5 [Power9]Legalize and emit code for DW vector extract and co [...] adds 4cb7c3ee0c9 [GlobalISel][InstructionSelect] Moving type checks forward, [...] adds 879a0d87269 [Power9]Legalize and emit code for W vector extract and con [...] adds 49011d2b653 [llvm-strip] Expose --keep-symbol option adds 0390dacdd03 [llvm-strip] Minor fix of the usage of TableGen adds c349f814879 [Tablegen] Tidying up InstRegexOp a little, NFC adds cb64cbca1c4 [GlobalISel] NFCI, Getting GlobalISel ~5% faster adds 38a4af251f3 [LKH] Add a new IRCompileLayer. adds 499fe95f132 [LKH] Add ObjectTransformLayer2. adds 1d560c20ffb [LKH] Add a new IRTransformLayer. adds 60b28ca5a7e [RuntimeDyld][MachO] Add support for MachO::ARM64_RELOC_POI [...] adds 5f477b2b135 [GlobalISel][InstructionSelect] Sorting MatchTable's 2nd le [...] adds 1352bbd3ec2 [RISCV] Set CostPerUse for registers adds 4e24f46cfd2 [DebugInfo] Maintain DI for sunken bitcasts adds 673840e6846 [GlobalISel][Tablegen] Assign small opcodes to pseudos adds 618f11e436b [RISCV] Lower the tail pseudoinstruction adds 3fd1c161ec4 Move a debug info test into the X86 directory adds c1e740501d9 [GlobalISel][InstructionSelect] Maximizing # of Group's com [...] adds 57baf695d85 [GlobalISel][InstructionSelect] Moving Reg Bank Checks forw [...] adds f932fced7c1 [GlobalISel][InstructionSelect] Switching over root LLTs, p [...] adds 41d411071ae [ORC] Add findSymbolIn() wrapper to C bindings. adds b0bd4049744 [PowerPC] Remove the match pattern in the definition of LXS [...] adds 017f7dfd701 Revert r333147 "[ORC] Add findSymbolIn() wrapper to C bindings." adds e8515905960 AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMP adds 3096e9dcfef [NaryReassociate] Detect deleted instr with WeakVH adds 0ec6aadbe3c [RISCV] Support linker relax function call from auipc and j [...] adds 109abe0d9a1 [demangler] Add ItaniumPartialDemangler::isCtorOrDtor adds 8b02838a9b5 [mips] Cleanup the code a bit. NFC adds 5c37d1e9baa [mips] Add precondition asserts to the expandLoadInst/expan [...] adds 6151d6d025c [mips] Remove redundant argument from expandLoadInst/expand [...] adds 3c819aac8ce [mips] Remove duplicated code from the expandLoadInst. NFC adds 4a65e92703d [ScheduleDAGInstrs / buildSchedGraph] Clear subregister en [...] adds 387dd2c562e Added a testcase for PR31593. A patch (r291535) that fixed [...] adds 7273b3f1278 [llvm-exegesis] Show sched class details in analysis. adds 7f8728c26a2 [llvm-exegesis] Analysis: show debug string instead of raw [...] adds 2071b7a8b26 [Support] Add color cl category. adds f7e1e2ecddd [Support] Move header to WithColor header adds df5bf794d61 [llvm-exegesis] Analysis: Show value extents. adds e8e07b9fd6d [x86] add vector load-cmp-select tests; NFC adds 936c00ed941 [NFC][VPlan] Wrap PlainCFGBuilder with an anonymous namespace. adds 1aaff1e1d20 [X86][BtVer2] Added Jaguar cpu cycle counter to permit llvm [...] adds a2d7e85a4ba [X86][SSE] Pull out OR(AND(~MASK,X),AND(MASK,Y)) matching i [...] adds d13570e87b5 FastMathFlags: Make it easier to unset individual ones. adds bc8f9a27992 [InstCombine] Combine XOR and AES instructions on ARM/ARM64. adds 8f9bb802233 Fix unused variable warnings. NFCI. adds 9f6d2386da8 [LICM] Preserve DT and LoopInfo specifically adds 05caaf125a0 Add R_PPC64_IRELATIVE to PPC64 relocations. adds 560976eb573 [X86][SSE] Pull out (AND (XOR X, -1), Y) matching into a he [...] adds add59cbbbbf [UpdateTestChecks] Improved update_mca_test_checks block analysis adds 81a864f66c6 [ORC] Perform name mangling in findSymbolIn(), as done in f [...] adds 8091867dd80 [llvm-mca] Fix a rounding problem in SummaryView.cpp expose [...] adds b3e5dc73875 [ThinLTO/CFI] Minor comment clarification adds cdedb669f2a [AArch64] Take advantage of variable shift/rotate amount im [...] adds 130bebd92f1 [ORC] Add findSymbolIn() wrapper to C bindings, take #2. adds 91b60922094 Add handling for GlobalAliases in ExecutionEngine::getConst [...] adds 3d4c0a0af46 [AArch64] Improve orr+movk sequences for MOVi64imm. adds 5932cd90d72 AMDGPU: Split R600 AsmPrinter code into its own class adds 0bd45c420d0 [InstCombine] Enable more reassociations using FMF 'reassoc [...] adds 16296d72ff7 [ValueTracking] Teach computeKnownBits that the result of a [...] adds 803d39f85cd [ORC] Extend object layer callbacks so JITEventListener can [...] adds 00af3355f1b [ORC] Add ability [un]register JITEventListener on Orc C stack. adds 2373d70fe72 [ORC][C-API] Expose LLVMOrc{Unr,R}egisterJITEventListener(). adds f501bf3e392 [C-API] Add functions to create GDB, Intel, Oprofile event [...] adds f48234e221a [LegacyPM] Use MapVector for OnTheFlyPassManagers. adds fca4ed2fcf5 [DebugInfo] Maintain DI when converting GEP to bitcast adds 951e605c7ba [Debugify] Avoid printing unnecessary square braces, NFC adds 646a736e7b4 [Debugify] Set a DI version module flag for llc compatibility adds 86df7c70f71 [llvm-symbolizer] Simplify. NFC adds 7feb37bec20 Use quoteattr to ensure we make well formed attributes adds 77818507224 Restore the LoopInstSimplify pass, reverting r327329 that r [...] adds 84a74917968 Revert r333226 "[ValueTracking] Teach computeKnownBits that [...] adds 96dd58bd6cd AMDGPU: Remove AMDGPUMCInstLower.h adds 87a4c58e539 [x86] invpcid LLVM intrinsic adds dde13123001 [AMDGPU] Fixed incorrect break from loop adds cc53486e922 [RegUsageInfoCollector] Bugfix for callee saved registers. adds 8c15b1c4737 [SystemZ] Bugfix in combineSTORE(). adds 537da199f42 [AArch64][SVE] Asm: Support for DUP (immediate) instructions. adds 60231abbcc6 Fix ODR violation from r333230 adds fe9deeb4321 [llvm-objcopy] Add --strip-unneeded option adds e6cc3adb12d [IPSCCP] Use PredicateInfo to propagate facts from cmp inst [...] adds 714f05ab4ec Fix ubsan errors introduced by r333263 re. left-shifting ne [...] adds 10826be2a67 [X86][SNB] Fix differences between vex/non-vex XMM vector m [...] adds 8d113114c48 [MustExecute] Fix a debug invariant issue in isGuaranteedTo [...] adds 682d7382c66 [Hexagon] Fix packing source vectors in shufflevector selection adds f1f35aaa798 [NFC] Restructure linkage name printing in AsmWriter adds e68d92b3873 [RFC][Patch 1/3] Add a new class of predicates for variant [...] adds 0d3a4af35c0 [RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve vari [...] adds ca7ed383cb0 [mips] Fix the definitions of lwp, swp adds 277225f5279 [AMDGPU] Add perf hints to functions adds ede786dd187 Fix -Winconsistent-missing-overrides in AMDGPU code adds cf35b20cbe0 [llvm-mca] Add the RetireStage. adds 66f9771e76a [Tablegen][SubtargetEmitter] Add a default case to the auto [...] adds e81b963da49 [llvm-mca] Update DispatchStage header comment. NFC. adds 31858aea84c [llvm-mca] Update the header's guard name. NFC. adds 869684e00bd [AMDGPU] Fixed test failure with AMDGPUPerfHint adds 981880ea8b5 Recommit r333226 "[ValueTracking] Teach computeKnownBits th [...] adds d900d78107a [AMDGPU][Waitcnt] Remove obsolete waitcnt option adds 192d09bc6e6 [CodeGenPrepare] Revert r331783 adds a50c4ffd89e [Support] Avoid normalization in sys::getDefaultTargetTriple adds 3bf8298d82e Replace AA's uses of uint64_t with LocationSize; NFC. adds 2cd65e1d26e Revert r333268: [IPSCCP] Use PredicateInfo to propagate fac [...] adds 758389d0d98 [CFLAA] Reflow comments; NFC adds 31d7817dfe8 [MemorySSA] Reflow comments + clean up control flow; NFC adds 77898103bf4 [llvm-symbolizer] Simplify adds a9a2147997b [ThinLTO] Print module summary index to assembly adds 601e1a7f76c [ThinLTO] Fix bot failures from r333335 adds 1e3026df79a [ThinLTO] Fix another bot failure due to test mismatch adds 2a70cfb61fe [ThinLTO] Fix a few more test match issues adds 5af80c626ea [llvm-objcopy] Add --keep-file-symbols option adds 1c5fb8ed958 Add test case for D46505 . NFC adds f49a7bfac5b Fix comment decribing setcccarry. NFC adds bfcd30f542b [X86] Remove masking from avx512ifma intrinsics. Use a sele [...] adds 98ac2639434 [dwarfdump] Make -c and -p work together adds 4362e9efb4c Tidy some language in the xray documentation. adds 9532fa4749c Cleanups for getKindForGlobal: - Clarify block comment - [...] adds 717390cf59d Remove boolean argument from isSuitableFromBSS. adds 3dde46793ca [UnrollAndJam] Add a new Unroll and Jam pass adds 00d34a85c6a Revert 333358 as it's failing on some builders. adds 15b56a703cf [X86] Don't hardcode scheduler class adds 822fd80cbeb [AMDGPU] Fixed WWM bug in block otherwise entirely in WQM adds 5bedd79076b [Tablegen] Avoid generating empty switch statements. NFC adds 6a0790d2aaf [X86] Stop forcing X86VPermi2X node index operand to match [...] adds f37b1a18727 [Sparc] Add .uahalf and .uaword directives adds 74b03c90995 [PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/stores adds 17534530708 [Power9]Legalize and emit code for HW/Byte vector extract a [...] adds 2457cfc63a4 [LLVM-C] [OCaml] Remove LLVMAddBBVectorizePass adds 9f7f417dbb2 [AMDGPU] Re-enabled 128bit wide-vector generation for local [...] adds 804aa541bed [X86] Fix typo in comment. NFC adds f6f4ca202ef [X86] Converge X86ISD::VPERMV3 and X86ISD::VPERMIV3 to a si [...] adds b943e69b7f9 [X86] Add unmasked vermi2var intrinsics so we can use expli [...] adds a96fa2453bc [X86] Remove masked vpermi2var/vpermt2var intrinsics and au [...] adds 7cdb0e22c2b [LangRef] Fix TBAA example adds 5c9fd60f9fc Use uniform mechanism for OOM errors handling adds 5ab2b7c9d7d Added system header cstdlib to MemAlloc.h adds 6cb2dcb6613 [X86][Sched] Add InstRW for CLC on Intel after SNB. adds 026b4e2a3ed [X86] Disable a DAG combine to allow packed AVX512DQ instru [...] adds 79428ba4694 Added library LLVMSupport to dependencies of LLVMDemangle adds d3b4e817113 Reverted commits 333390, 333391 and 333394 adds ae6d614666b [AMDGPU] Fixed build warning adds 66039bf0974 [mips] Stop parsing a .set assignment if the first argument [...] adds 0b90c62a5f0 [mips] Escape else-after-return. NFC adds f6555fd47fc [mips] Cleanup the code to reduce diff with the upcoming pa [...] adds 1b5b9b61708 [mips] Correct the predicates for a number of instructions. adds 6b4e03b5c30 Test Commit Access - Removed Whitespace adds 30edd11e203 [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations adds 8f9ce25710e [AArch64][SVE] Asm: Support for ADD (immediate) instructions. adds cfb33a0de9f [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS [...] adds 5caca234f99 [AArch64] added FP16 vcvth intrinsic support adds 56b39559999 [AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instr [...] adds babbfe42786 [PowerPC] Fix the incorrect iterator inside peephole adds 6fa6453210f StackColoring: better handling of statically unreachable code adds d5f15150786 [X86] Scalar mask and scalar move optimizations adds 5f28b9c36c1 [CodeView] Add prefix to CodeView registers. adds e4c479fce54 [AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors) adds 980b901b1e7 [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes [...] adds bfc882d9b5c Revert "[AArch64] added FP16 vcvth intrinsic support" adds fc06be5513f [mips] Process numeric register name in the .set assignment [...] adds ff4e68832fd [AArch64] Fix PR32384: bump up the number of stores per mem [...] adds 0828dbea263 [X86][AVX] Regenerate vzeroall/vzeroupper cleanup tests adds f498c48490a [X86][SSE] Regenerate sdiv combine tests adds f5982f47734 [StrictFP] Make getStrictFPOpcodeAction(...) more accessible adds 300f4783657 [TableGen] Fix leaking synthesized registers. adds 5aba3740e40 TableGen: add some more helpful error messages adds e4c36d2f8bd [TableGen] Fix leaking of PhysRegInputs. adds bc78b53387f AMDGPU: Split R600 MCInst lowering into its own class adds fec5a579e7e DAG: Remove redundant version of getRegisterTypeForCallingConv adds 31361406cce AMDGPU: Add nuw to add off of kernarg ptr adds 36d1b4fe6f4 AMDGPU: Pass function directly instead of MachineFunction adds 4ab6b1f52ba IRBuilder: Add overload for intrinsics without args adds 9ef66917200 [ARM] Enable SETCCCARRY lowering for Thumb1. adds 98de50d1f8e [TableGen] Use explicit constructor for InstMemo adds 840f423383f AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to [...] adds e1b970aa149 Update CodeView register names in a test that was missed in [...] adds cbc5616c5e7 [BasicAA] Teach the analysis about atomic memcpy adds 72d605bcbb5 [RISCV] Add peepholes for Global Address lowering patterns adds 1fa5b55214b AMDGPU: Round up kernel argument allocation size adds c40f49e881a AMDGPU: Fix typo in option description adds 7f19a98b4cc AMDGPU: Fix broken check lines adds 50617cfe729 [WebAssembly] Add more error checking to object file parsing adds fb69f8242b9 [X86] Fix a potential crash that occur after r333419. adds 95ab02a5c07 [LoopInstSimplify] Re-implement the core logic of loop-inst [...] adds cb122505e17 Fix build error introduced in rL333459 adds e83159701cf [X86] Rename the operands in the recently introduced MOVSS+ [...] adds fca3b88d171 [X86] Use VR128X instead of VR128 in EVEX instruction patterns. adds c51efb8b0f3 [X86] Remove some of the extractelts from the new MOVSS+FMA [...] adds 7029deaeb5c [VPlan] Replace LLVM_ATTRIBUTE_USED with ifndef NDEBUG adds 8bc9af8efb9 [RISCV] Support resolving fixup_riscv_call and add to MCFix [...] adds 543cda41102 [ORC] Update JITCompileCallbackManager to support multi-thr [...] adds 7264d3b64cb [ORC] Fix an ambiguous make_unique call. adds c96b7cb0029 [PM/LoopUnswitch] When using the new SimpleLoopUnswitch pas [...] adds 1838ee91829 [WebAssembly] MC: Add compile-twice test and fix corresponding bug adds f392a175ab4 Fix use of `echo` command in test script adds 4548453c8b1 MC: Remove redundant substr() call adds 9066b8af331 [PowerPC] fix broken JIT-compiled code with tail call optimization adds 70fe1686ce8 Use uniform mechanism for OOM errors handling adds 17fb18e7072 [X86] Add unmasked AVX512VNNI instrinsics. Use a select in [...] adds a9caa65fed7 [Sparc] Select correct register class for FP register constraints adds d8472b591c1 Revert commit 333506 adds a049b2d5f46 Set underlying type for enum with GNU_PROPERTY_X86_FEATURE_ [...] adds fc1eef35a4a [Sparc] Treat %fxx registers with value type Other as singl [...] adds 5d783b348f8 [AArch64][AsmParser] Fix segfault on illegal fpimm. adds adcf643e718 AArch64: print correct annotation for ADRP addresses. adds cab5faf1e22 [YAML] Quote multiline string scalars adds 056c0666f5e [mips] Correct the predicates of arithmetic and logic instr [...] adds e4b4ace58e6 [mips] Sink PredicateControl further down the class hierarchy. adds a9aee862f07 [mips] Correct the predicates of microMIPS compact branch i [...] adds f5a87e6cf44 [mips] Correct the definition of CTC2/CFC2 adds 93c2d96597b [Hexagon] Use vector align-left when shift amount fits in 3 bits adds a0bb0ca79d1 [ARM] Remove code handling ADDC/ADDE/SUBC/SUBE adds f6643943be2 [X86][SSE] Replace -cpu with equivalent -mattr for vec_cast tests adds bf13d093f13 [X86][SSE] Remove unnecessary -cpu from sttni tests adds 8f367c48d76 [X86][AVX512] Replace -cpu=knl with -mattr=+avx512f for avx [...] adds 896749ca406 [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector adds 136d97ecc48 [AliasSet] Teach the alias set how to handle atomic memcpy/ [...] adds eaf5e5d8b4c [X86] Lowering FMA intrinsics to native IR (LLVM part) adds b81ef9cebe1 [AMDGPU][Waitcnt] Fix handling of loops with many bottom blocks adds a85653ea251 [ValueTracking] Fix endless recursion in isKnownNonZero() adds 664e38cb138 AMDGPU: Use better alignment for kernarg lowering adds b7ba560cf93 [AMDGPU][Waitcnt] Fix build error: unused variable 'SWaitInst' adds efc5ddaded1 [X86][AVX512BW] Fixed check prefix copy+paste typo in avx51 [...] adds 21cf02e0607 [GlobalISel][Legalizer] NFC mostly reducing LegalizeRuleSet [...] adds e22dca52860 [dsymutil] Escape HTML special characters in plist. adds 947f8c23105 [X86] Update the fast-isel tests for _mm_rcp_ss, _mm_rsqrt_ [...] adds fd6d60ff755 [GlobalISel][Legalizer] LegalizerInfo verifier: check rules [...] adds 80f62ff390c Reverted r333424 as it broke multiple build bots and left u [...] adds 7432746a8b0 [X86][SSE] Pulled out splat detection helper from LowerScal [...] adds 44e7cf45f6b llvm-objcopy: Set sh_link to 0 on unrecognized symtab-linke [...] adds 6450da6b0c8 [CalledValuePropagation] Just use a sorted vector instead o [...] adds e7c7bc039fa [lit] Report line number for failed RUN command adds 9c6a07cc6f5 Fix Wdocumentation warning. NFCI. adds e33ce2953b9 [IRBuilder] Add APIs for creating calls to atomic memmove a [...] adds 70d25790ff4 [ADT] Add unit test for PrintHTMLEscaped adds 0b596f0cd28 [TableGen] Avoid leaking TreePatternNodes by using shared_ptr. adds 22634021a15 Revert r333584: [lit] Report line number for failed RUN command adds fe061018e75 [GlobalISel][AArch64] LegalizerInfo verifier: Adding Legali [...] adds 0123bcf4a96 [NewGVN] Fix set comparison; reflow comment adds 97d2b2af9ec [LowerTypeTests] Discard extern_weak linkage for definitions adds e0c801c31a1 AMDGPU: Split AMDGPUTTI into GCNTTI and R600TTI adds db0f0aca363 [llvm-cov] Use the new PrintHTMLEscaped utility adds a855adc9a08 [InstCombine] don't negate constant expression with fsub (PR37605) adds a1f89c23d36 [InstCombine] don't change the size of a select if it would [...] adds 1d95844557f [lit] Report line number for failed RUN command adds 7074b82591e [GlobalISel][AArch64] LegalizerInfo verifier: Fixing bugs e [...] adds 12dc03238a5 [GlobalISel][Legalizer] LegalizerInfo verifier: Making Lega [...] adds 1d4f2158ac9 [lit] Terminate ": RUN at line N" with ";" not "&&" adds 655741c8078 AMDGPU/R600: Make sure functions are cacheline aligned adds 10bf29495fa [AMDGPU] Track occupancy in MFI adds deabcc51dc5 [lit] Fix windows cmd.exe test config for r333620 adds 81e2b6bb011 Revert rL333106 / D46814: [InstCombine] Fold unfolded maske [...] adds 0ff5fd6ca90 [llvm-exegesis][NFCI] Counter::Counter(): more useful msg o [...] adds 46d43c43ddc [NFC] Factor out a method for further extension adds 8b391bff9c1 [AArch64] Reverted rL333427 fixing Clang UnitTest Failure adds 2299c2e836a DWARFAcceleratorTable: fix equal_range iterators adds 179d3b6ebbd [X86][SSE] Add support for detecting SUB(SPLAT_BV, SPLAT) c [...] adds 7f6275200a2 [X86] Extract latency of fldz/fld1 in separate classes. adds cbc8a87b848 [InstCombine, ARM] Convert vld1 to llvm load adds a2207057d9c [mips] Guard all short instructions correctly. adds f4eac50c9d1 Extend the GlobalObject metadata interface adds ae5fb65acec [MCSchedule] Add the ability to compute the latency and thr [...] adds f13df0323ac Use -Wextra spelling instead of -W adds 38dac027e19 [X86] Introduce WriteFLDC for x87 constant loads. adds 51a3d890840 [DA] Fix direction vectors for weakZeroSrcSIV adds af4ce71b169 make GlobalValueSummary::getOriginalName() a const function adds 3465265c398 [X86][AVX] Add peekThroughEXTRACT_SUBVECTORs helper (NFCI) adds 4531d3dfa97 [X86][SSE] Recognise splat rotations and expand back to shift ops. adds d46273ac4fa [GlobalISel][X86] LegalizerInfo verifier: Adding LegalizerI [...] adds 0c1c48cee69 [GlobalISel][ARM] LegalizerInfo verifier: Adding Legalizer [...] adds 99f1f92235f [GlobalISel][AMDGPU] LegalizerInfo verifier: Adding Legaliz [...] adds f911f7d95af [GlobalISel][Mips] LegalizerInfo verifier: Adding Legalizer [...] adds e027ed4b629 [MC] Fallback on DWARF when generating compact unwind on AArch64 adds 3b8808fda4c [SimplifyLibcalls] [NFC] Cleanup, improvements adds 7eeba255a65 [ADT] Make escaping fn conform to coding guidelines adds 543ae96995f [ADT] Annotate immutable list/set/map update methods with L [...] adds 714d12718f5 [JumpThreading] Fix some strange formatting of code inside [...] adds 51eddbabdf6 Relax GOTPCREL relocations for tail jmp instructions. adds d24e9c32fc1 IRGen: Write .dwo files when -split-dwarf-file is used toge [...] adds 4129c41f40b [InstCombine] regenerate checks; NFC adds 5da314cda88 [ORC] Rename IRMaterializationUnit's Discardable member to [...] adds e9015c77605 [ORC] Add a getRequestedSymbols method to MaterializationRe [...] adds 9f5837ba985 [GISel]: Pattern matchers for GFSUB, GFNEG adds 93b037daa0a [AMDGPU] Fixed incorrect -mcpu=gfx800 in xnor.ll test. NFC. adds 4495104b59a [InstCombine] narrow select to match condition operands' size adds e5240df77ae [AMDGPU] Construct memory clauses before RA adds 5f7a952b278 [llvm-mca] Fixed a problem caused by an invalid use of a pr [...] adds 9eb93071627 [llvm-strip] Add -o option to llvm-strip adds 5a3ab98eb8b [LoopVectorize, x86] regenerate checks; NFC adds a6e37da488e [WebAssembly] Add Wasm exception handling prepare pass adds f1fb72e56bf [LoopIdiomRecognize] Only convert loops to ctlz if we can p [...] adds 60c0443a114 [WebAssembly] Support instruction selection for catching ex [...] adds fa719da681b [WebAssembly] Fix the signatures for the __mulo* libcalls. adds 6da40ce2e20 [LoopVectorize, x86] add tests to show missing SVML transfo [...] adds 238f816f4c4 [WebAssembly] Update to the new names for the memory intrinsics. adds 2522e34cd59 Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC. adds f431a94a97d [X86] Add test cases showing the disassembler producing an [...] adds d0d3e796b7c [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' [...] adds 9f563c4301f [X86] Make sure the check for VEX.vvvv being all ones on in [...] adds c54b4ce0c3d AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.td adds baf24940e74 [X86][Disassembler] Use a local variable instead of using a [...] adds 6b95374465f [X86][Disassembler] Make sure EVEX.X is not used to extend [...] adds 3ff438cbeb5 [X86] Add a test case showing a bad disassembling of an EVE [...] adds d62e7ad8825 [X86][Disassembler] Clamp index to 4-bits when decoding GPR [...] adds 86986e7ed4b Implemented sane default for llvm-objdump's relocation Valu [...] adds 983b09a88b4 [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to [...] adds af54ec44f00 [X86][Disassembler] Make it an error to set EVEX.R' to 0 wh [...] adds 0176ae243c3 AMDGPU: Switch some half using-tests to use amdhsa adds 1aba3493997 [AArch64][SVE] Asm: Support for DUPM (masked immediate) ins [...] adds 48c1879dced NFC Avoid a warning in WasmEHPrepare.cpp adds 55b76bc78d7 [mips] Select the correct instruction for computing frameindexes adds 787adc70066 DWARFAcceleratorTable: Add an iterator-based api for access [...] adds aa33e079d26 [mips] Guard 'nop' properly and add mips16's nop instruction adds 39b491d6bb5 Recommit r333268: [IPSCCP] Use PredicateInfo to propagate f [...] adds 1b58c0fb246 [mips] Guard more aliases correctly. adds 3646784d6dc [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) [...] adds b062161990a Revert r333740: IPSCCP] Use PredicateInfo to propagate fact [...] adds 82441a3e012 [AArch64][GlobalISel] Zero-extend s1 values when returning. adds 876db10e96e Set ADDE/ADDC/SUBE/SUBC to expand by default adds d0ebabd8a8a [Utils][X86] Help update_llc_test_checks.py to recognise re [...] adds 275c590ab30 [x86] NFC. Reautogenerate test/CodeGen/X86/vector-half-conv [...] adds 925c3a82e23 [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if lega [...] adds 1d12ed52734 [llvm-exegesis] Analysis: Display idealized sched class por [...] adds db87b1cd645 [NFC] Zero initialize local variables adds 4acd0f7b388 [llvm-mca] Move the logic that computes the block throughpu [...] adds 0028bf52e14 [InstCombine] add baseline test for bug with div+select tra [...] adds 1a0db446251 [llvm-exegesis] Fix off-by-one in llvm-exegesis documentation. adds e5ce9ac1bde [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ adds 3ef57a09b91 [DAG] Prune store merge legal store check to stop invalid s [...] adds 5c84d3b038a [DAG] Remove untriggerable check. NFCI. adds 08410ea64b7 [DAG] Simplify Expression. NFC. adds 75446f106ab [DAG] Avoid checking for consecutive stores in store merge. NFCI. adds e213c7a036a [ConstantFold] Add lit testcase for bitcast problem. NFC adds 54c0192722b [ThinLTOBitcodeWriter] Emit summaries for regular LTO modules adds 3d9d207bb28 [LangRef] fix typo; NFC adds 2985b38bbea [Hexagon] Avoid UB when shifting unsigned integer left by 32 adds 64284524f09 [llvm-objcopy] Fix null symbol handling adds 50fd0f624a7 [mips] Extend list of relocations supported by the `.reloc` [...] adds d525a1e0b67 [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions adds 1c19a372980 [InstCombine] add tests for broken shuffle transform (PR37648) adds e5a153eafdc [InstCombine] fix vector shuffle transform to replace undef [...] adds ad388af4147 [ConstantFold] Disallow folding vector geps into bitcasts adds 4a03a2af4d9 [X86] Add fast-isel tests for avx512vbmi2 instructions. adds 2c205448993 [X86] Expand the testing of expand and compress intrinsics adds ca723b633fc [MachO] Fixing ub in MachO BinaryFormat adds afee80613fc Move some function declarations out of WindowsSupport.h adds 612077896b6 Revert "[MachO] Fixing ub in MachO BinaryFormat" adds cc46647abe2 [X86] Add isel patterns to use vexpand with zero masking wh [...] adds eacd22487e0 Add a debug dump for DbgValueHistoryMap adds a380a4e5ba2 Re-land: [MachO] Fixing ub in MachO BinaryFormat adds fe687157a73 [X86] Do something sensible when an expand load intrinsic i [...] adds 893c5df3e31 Revert "Re-land: [MachO] Fixing ub in MachO BinaryFormat" adds a82bdae0593 [DebugInfo] Refactoring DIType::setFlags to DIType::cloneWi [...] adds 71a53486661 Remove the test from r333801 adds 2aaad362036 [PM/LoopUnswitch] Fix how the cloned loops are handled when [...] adds cd5a806c0f2 [X86] Add encoding information for the AVX5124FMAPS and AVX [...] adds b6ec37aaaa7 [Support] Remove unused raw_ostream::handle whose anchor ro [...] adds 5d9c754b875 [InstCombine] add more tests for shuffle-binop; NFC adds c5b2db16de1 [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part) adds b155a7cf565 [InstCombine] call simplify before trying vector folds adds 6c4969c5033 [X86] Fix warning message for AVX5124FMAPS and AVX5124VNNIW [...] adds d1bfb4c41d3 [X86] Add tied source operand to AVX5124FMAPS and AVX5124VN [...] adds 56500c79d33 [MC] Add assembler support for .cg_profile. adds f646a586eb7 Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 [...] adds a13992d918e [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) adds f1434b74d01 [X86][BMI1] Remove test for non-existent andn i16 instruction adds 793826588a8 [X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off [...] adds c7f940736d6 [X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests adds 9ade710da54 [X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover S [...] adds e2962ff8f58 [X86][SSE] Cleanup SSE3/SSSE3 intrinsics tests adds 3ae762d9b22 [X86][SSE] Cleanup SSE2 intrinsics tests adds fc0f56727e2 [X86][SSE] Cleanup SSE1 intrinsics tests adds 86446182372 [X86][SSE] Cleanup AVX1 intrinsics tests adds cff463369b4 [ORC] Use JITEvaluatedSymbol for IndirectStubsManager findS [...] adds 3e8866efa22 Remove SETCCE use from Lanai's backend adds f0126ab1c0c [X86][TBM] Branch off i32 intrinsics and test on 32/64 bits adds 90556455861 [X86][BMI] Remove CTTZ tests - this is fully covered in clz.ll adds c94fa24c2bc [X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off [...] adds ddd630b12cb [X86][AVX512BW] Regenerate arithmetic tests using update_ll [...] adds d640970907a [X86][AVX512] Cleanup intrinsics tests adds 9a5dadc5b18 [InstCombine] improve sub with bool folds adds bae60caa7aa [X86][TBM] Use realistic BEXTR control bits adds 33c00a3db2c [ORC] Add a constructor to create an IRMaterializationUnit [...] adds 89c9fe49ef5 Re-land: [MachO] Fixing ub in MachO BinaryFormat adds 2373850ed00 [Debugify] Skip dbg.value placement for EH pads, musttail adds 93d997435d7 [X86] Remove and autoupgrade masked avx512vnni intrinsics u [...] adds 63a0fe28349 Reformat overflowing lines, NFC adds 701cfb8f829 [opt] Add a -strip-module-flags option adds f66cfed61f1 [Debugify] Don't apply DI before the bitcode writer pass adds f88b709c4a5 [InstCombine] Fix div handling adds 4f55de6f813 [Debugify] Add debug intrinsics before terminating musttail calls adds a22c0bf8365 [AArch64][SVE] Asm: Support for CPY immediate instructions adds dafed019d67 [AArch64][SVE] Asm: Support for FCPY immediate instructions. adds 7ea5568b5e2 [AArch64][SVE] Asm: Support for indexed DUP instructions. adds 586cc3f79b0 [AArch64][SVE] Asm: Print indexed element 0 as FPR. adds 40c66c3d403 [AArch64][SVE] Fix range for DUP immediates (16bit elts) adds 16cc55db244 [AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns adds f5872fd35f6 [llvm-exegesis] Analysis: Show inconsistencies between chec [...] adds 2d87e5abe5e [llvm-exegesis][NFC] Use an enum instead of a string for be [...] adds c8a936b18ef [llvm-mca] Make sure not to end the test files with an empty line. adds b29b4919ea3 [llvm-mca] Track cycles contributed by resources that are i [...] adds feb319a84ab [llvm-mca] Regenerate a test to remove a double newline adds 14d1a66e677 [llvm-mca][UpdateTestChecks] Prevent an IndexError being ra [...] adds 49eaa4d1e03 [mips] Restore the availablity of trap for microMIPS adds fa47ca77771 [ReleaseNotes] Add release note for the new LLVM_DEBUG macro. adds 26db53e38e1 TableGen: Streamline the semantics of NAME adds 6b71fcbf269 TableGen: some LangRef doc fixes adds d74cc3fc39a [ReleaseNotes] Formatting fixes. adds 6f256bce8f3 TableGen/DAGPatterns: Allow bit constants in addition to in [...] adds c5e20053214 AMDGPU: Make various NamedOperands upper case adds f181103bd30 [SelectionDAG] Add missing closing parentheses in comments, NFC adds 2db6f82ea72 [llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes [...] adds 47acfadfe75 [RFC][patch 3/3] Add support for variant scheduling classes [...] adds 38eba07f5f0 [NVPTX] Delete dead code from the AsmPrinter. adds 9d0b6a4e21f [X86] Only accept const SelectionDAG to resolveTargetShuffl [...] adds 8177aafa749 [AMDGPU][Waitcnt] Fix handling of flat instrs adds 9495e9e09de [ValueTracking] Match select abs pattern when there's an se [...] adds 65da601c2dd [WebAssembly] Fix .td files after rL333900 adds 8844a1781e3 [MachO] Add out-of-bounds check to MachOObjectFile.cpp adds 222c71a39d2 [AMDGPU] Factored out common part of GCNRPTracker::reset() adds 9136eac9794 [AMDGPU] Small refactoring in the scheduler adds d63b4b67fbd [X86] Don't pass ParitySrc array into isAddSubOrSubAddMask. [...] adds 03c2c8140e8 In thin and full LTO + CFI, direct function calls may go th [...] adds 7436bb683e6 Get rid of SETCCE adds 711621feb77 [llvm-strip] Add missing aliases for --strip-debug adds 06b75979913 Fix for llvm-dis/llvm-bcanalyzer overflows adds 5f67380d0ea [DAGcombine] Teach the combiner about -a = ~a + 1 adds ea3c8cfdcef [Support] Add functions that operate on native file handles [...] adds b9cccf44aae [CodeGen] Always update divergence in SelectionDAG::UpdateN [...] adds cf25dfc503c Regenerate expected test results for test/CodeGen/X86/pr231 [...] adds f0e85c194ae Remove various use of undef in the X86 test suite as patern [...] adds fbccfa39294 [X86][ELF][CET] Adding the .note.gnu.property ELF section in X86 adds 65c5ddb6f86 [MachineOutliner] NFC - Move intermediate data structures t [...] adds 71e6616a7c6 Revert "Remove various use of undef in the X86 test suite a [...] adds 8325fb20d4d Move Analysis/Utils/Local.h back to Transforms adds 1fb574d534f Add missing header adds 8c3bbfcc15b [Debugify] Preserve analyses in -check-debugify adds 9b4ac07fadc Revert "Regenerate expected test results for test/CodeGen/X [...] adds 9c45f896fa2 Remove various use of undef in the X86 test suite as patern [...] adds 3479c8049bd [InstCombine] refine UB-handling in shuffle-binop transform adds 3bc04090d38 Simplified WebAssemblyAsmBackend by removing explicit ELF variant. adds 475e5301215 Move Compiler.h from Demangle back to Support adds 9d75364cfaa Fix -Wcovered-switch-default warning and clang-format it adds b86b9032fde [MIRParser] Add parser support for 'true' and 'false' i1s. adds e70aaf7304c [ShrinkWrap] Add optimization remarks to the shrink-wrapping pass adds c29988523b8 Use MF instead of Fn for MachineFunction references. NFC adds 61b411cd372 Apply clang-format on a file, NFC adds 0e9833dbfa7 [Debugify] Don't insert debug values after terminating deopts adds 9e729a33eff [opt] Introduce -strip-named-metadata adds 4c53b27f1f9 [RegAllocGreedy] Use simpler map class for EvicteeInfo. NFCI. adds 912ef7aa018 [X86] Make all instructions that operate on MMX types, but [...] adds 3c5de91faa1 [X86][CET] Shadow stack fix for setjmp/longjmp adds 7fd3761e18c [MC][ARM] Correct Thumb BL instruction range adds c08e3f7298d [X86][SSE] Add basic PACKUS support to X86TargetLowering::c [...] adds 13e7624a748 [MC][ARM] Add range checking for Thumb2 resolved fixups. adds b00bb39e238 [X86] NFC Refactor some code in InstPrinters adds 3f2a06592b3 [X86][SSE] Add target shuffle support to X86TargetLowering: [...] adds bed775073b8 [llvm-exegesis] Add instructions to BenchmarkResult Key. adds a518a5e97ec [X86][SSE] Fix line endings for shuffle-vs-trunc tests. NFCI. adds 8b13d9fafa1 [PowerPC] reduce rotate in BitPermutationSelector adds 19eacef7de1 [Hexagon] Minor cleanups in isel lowering adds d117450d6ab [X86] NFC Fix typo introduced in r328016 HSI->HDI adds ebe751f9808 [InstCombine] Correct the cmp operand type used when canoni [...] adds e5fc6740900 DAG: Stop dropping invariant/dereferencable adds 956861e56a4 [MC][X86] Allow assembler variable assignment to register name. adds f68ced99b15 [X86][SSE] Use multiplication scale factors for v8i16 SHL o [...] adds 61da58d5fe8 Remove a self-referencing #include adds 04b507e1042 [llvm-mca] Correctly update the CyclesLeft of a register re [...] adds 8ca27f22af8 [UpdateTestChecks] Error if --llvm-mca-binary gets an empty string adds 8499c1a3970 [mips] Fix the predicates for arithmetic operations adds 39e47efe752 NFC: adding baseline fneg case for fmf adds e23e5cc5b11 guard fneg with fmf sub flags adds 7488dbc1218 [Hexagon] Add more patterns for generating abs/absp instructions adds 9e7803cfe05 [Hexagon] Add pattern to generate 64-bit neg instruction adds 0c5ab47e3bd AMDGPU: Use more custom insert/extract_vector_elt lowering adds 19dfb4b388a AMDGPU: Preserve metadata when widening loads adds ceb8b5d24a7 [FileSystem] Remove OpenFlags param from several functions. adds 30557dd78b5 [CodeGenPrepare] Move Extension Instructions Through Logica [...] adds e667d971171 [Mips] Remove uneeded variants of ADDC/ADDE lowering adds 863443f97f7 [CodeGen] assume max/default throughput for unspecified ins [...] adds 26b7b194d71 [Analyzer] Fix the Z3 lit test config adds ac290fc00ee [Support] Use zx_cache_flush on Fuchsia to flush instruction cache adds e2b017e8ff8 [MIPS GlobalISel] Add lowerCall adds ed92eef9768 Added documentation for Masked Vector Expanding Load and Co [...] adds e2b2a91087a [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixup adds f37d1934609 [llvm-exegesis] move Mode from Key to BenchmarResult. adds d2c6383f3cd [cmake] fix a typo in llvm_config macro adds 54845e4bd7a [X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR con [...] adds f22b386635e [mips] Partially revert r334031 adds 16b3cbe7f09 Fix compilation of WebAssembly and RISCV after r334078 adds e038e0568ac Fix MSVC '*/' found outside of comment warning. NFCI. adds f2cc2b9e5f0 Update the project name in README.txt adds 603a19fd853 InstCombine: ignore debug instructions during fence combine adds 7c9e5c3975a [mips] Add testcase for i64, i128 addition for the DSP ASE adds 216b290618b Avoid UnicodeEncodeError on non-ascii reviewer names adds b439319a25c [GlobalMerge] Set the alignment on merged global structs adds c4f3d9f40df Relax shtest-run-at-line.py adds a0a79b99270 [X86][BtVer2] Add tests for all vector instructions that sh [...] adds adb3fd7c767 Change TII isCopyInstr way of returning arguments(NFC) adds 9c2b3778924 [ConstProp] move tests for fp <--> int; NFC adds 5d3e5a3332b [Hexagon] Split CTPOP of vector pairs adds feaa0dca1ce [llvm-mca][x86] Fix all resources-x86_64.s tests to use dif [...] adds a3a327f0ff6 [ThinLTO] Make ValueInfo operator!= consistent with operato [...] adds 1de1655ed5a guard fsqrt with fmf sub flags adds d84132e4554 Fix the test case that places intermediate in source directory. adds df07044b5f0 [AArch64, ARM] Add support for Samsung Exynos M4 adds f0c081c4cc5 [Debugify] Add a quiet mode to suppress warnings adds a959524611a [Debugify] Move debug value intrinsics closer to their oper [...] adds 04c4197451a [X86][BtVer2] Add support for all vector instructions that [...] adds 1e296472a53 [X86] Rename vy512mem->vy512xmem and vz256xmem->vz256mem. adds 7cdce818bde [X86] Properly disassemble gather/scatter instructions wher [...] adds ddfcacb69b4 [Hexagon] Implement vector-pair zero as V6_vsubw_dv adds 300d3c16026 [NFC][X86][AArch64] Reorganize/cleanup BZHI test patterns adds 33766d28542 [X86] Emit BZHI when mask is ~(-1 << nbits)) adds 5c1cd1ae0e3 [InstCombine][NFC] PR37603: low bit mask canonicalization tests adds 85b7bc9e526 [InstCombine] PR37603: low bit mask canonicalization adds ad593b0363b [llvm-strip] Expose --discard-all option adds 2d78ae2ab11 AMDGPU: Custom lower v2f16 fneg/fabs with illegal f16 adds 4063baba8d7 [InstCombine] add tests for another abs() pattern (PR36036); NFC adds 957e46dfb8c [CMake] Pass additional CMake tools to external projects adds 6a08b7888b6 [InstCombine] fold another shifty abs pattern to cmp+sel (PR36036) adds e07c2606ba3 [ThinLTO] Rename index IsAnalysis flag to HaveGVs (NFC) adds ded60aa7f8b [AMDGPU] Improve reciprocal handling adds 032b3051e3a llvm-readobj: fix printing number of relocations in Android [...] adds a42c01a4b3c Add definition for ELF dynamic tag DT_SYMTAB_SHNDX. adds d13f6289f77 SpeculativeExecution Pass: Set PreserveCFG to avoid unneces [...] adds 5c3e6410f47 [SystemZ] Build Load And Test from scratch in convertToLoa [...] adds 1c7fca97fb9 [BranchFolding] Fix live-in's when hoisting code adds 680aba746e9 [X86][NFC] Fix harmless typos in BDW/ZnVer1 sched models. adds a1c8d87b414 [llvm-exegesis] Serializes instruction's operand in Benchma [...] adds 184b9569f93 [llvm-exegesis] Improve error reporting. adds d9ded5e7ff0 [llvm-exegesis] Add a Configuration object for Benchmark. adds 52d9f458492 Test commit access. adds 66a7e9beda1 [NFC] Use variable instead of accessing pair many times adds 99763c22820 [X86] Block UndefRegUpdate adds f546e73aa0e [X86][NFC] Fix harmless typo in BtVer2 model. adds 75c4f68f538 AMDGPU: Try a lot harder to emit scalar loads adds f36d22b0035 [llvm-strip] Expose --strip-unneeded option adds ed2e7364524 [X86] Regenerate rotate tests adds 86e569e7c67 AMDGPU: Use scalar operations for f16 fabs/fneg patterns adds 2cd9451d45d [Mem2Reg] Avoid replacing load with itself in promoteSingle [...] adds 2ab43f753f8 [X86][SSE] Add extra trunc(shl) test cases adds 4dea9c28110 AMDGPU: Fix not including v2f64 in SReg_128 adds efeb67ca07f [PowerPC] fix trivial typos in comment, NFC adds 7a1c547b189 [X86][SSE] Simplify combineVectorTruncationWithPACKSS to re [...] adds a1a3a0ed7a6 [Mips] Silencing warnings in instruction info (NFC) adds 61db82a706c [PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector adds 3fc706588c4 [llvm-objdump] Add -R option adds 9c8bd216eb3 [llvm-exegesis] Make BenchmarkRunner handle multiple config [...] adds c9843e63a7e [x86] add tests for backwards propagate mask bug (PR37060, [...] adds 837cf88a094 [NFC][InstSimplify] Add tests for shl nuw C, %x -> C fold. adds c51e39b7f5f [X86][SSE] Simplify combineVectorTruncationWithPACKUS. NFCI. adds 5cadb75706e [AVR] Fix build after r334078 adds 8c71680c989 [RISCV] AsmParser support for the li pseudo instruction adds 53673e8b7ba [X86][SSE] Updated comment - combineVectorSignBitsTruncatio [...] adds afa7b32d8f8 [NFC][InstSimplify] Add more tests for shl nuw C, %x -> C fold. adds a8e3af51926 [docs] add various sanitisers support for FreeBSD/OpenBSD adds 9378ab2ca41 [LSR] Check yet more intrinsic pointer operands adds bd9be7a1ed5 [TargetLibraryInfo] add mappings from LLVM sin/cos intrinsi [...] adds 89be48cd836 [llvm-objcopy] Remove unused field from Object adds b6ab0f18f85 DAG: Avoid bitcast/ext/build_vector combine adds 03bcb2143b5 [FileSystem] Split up the OpenFlags enumeration. adds fa1dbcce5b8 [InstSimplify] shl nuw C, %x -> C iff signbit is set on C. adds 11cede3a06f Fix unused private variable. adds b99ddeab540 Try to fix build. adds d22fc60ce59 [Support] Link libzircon.so when building LLVM for Fuchsia adds 04cb3cb2397 [NFC][InstSimplify] One more negative test for shl nuw C, % [...] adds 6dc64e29f8d [NFC][InstSimplify] Add tests for add nuw %x, -1 -> -1 fold. adds 1310a7556e1 [AMDGPU] Simplify memory legalizer adds 71bbcb1f4af propagate fast math flags via IR on fma and sub expressions adds e6e585b6dcc Expose a single global file open function. adds 5ecc80bd50f NFC Fix a comment in ValueTypes.td adds 1306190f317 Revert r334209 "[LSR] Check yet more intrinsic pointer operands" adds 469bc504d00 [AMDGPU] Simplify memory legalizer (add missing virtual des [...] adds 5109f3dedd8 [X86] Improve some shuffle decoding code to remove a condit [...] adds 693db957d29 [NFC] fix formatting adds 3006b374d6f [DAGCombine] Fix for PR37667 adds 0aedafefd12 AMDGPU: Error on LDS global address in functions adds 42f7ad099aa [LV] Fix PR36983. For a given recurrence, fix all phis in e [...] adds 3a14e8ce77b [TableGen] Make DAGInstruction own Pattern to avoid leaking it. adds 696a18d3c4f [X86][SSE] Consistently prefer lowering to PACKUS over PACKSS adds 055d3aae75c [RISCV] Implement MC layer support for the fence.tso instruction adds 7eabd93fbb0 [mips] Correct the predicates for a number of codegen only [...] adds bff55302937 [ADT] Add `StringRef::rsplit(StringRef Separator)`. adds 1ec02551591 [VPlan] Move recipe based VPlan generation to separate function. adds 3ff0fb06516 [BPI] Apply invoke heuristic before loop branch heuristic adds f61fd4636ff [x86] restore test comment; NFC adds 3416a07cb97 [X86][SSE] Simplify combineVectorTruncationWithPACKUS to re [...] adds a7bdfb88d1d [X86][SSE] Add SSE2/AVX2 vector rotate tests adds ae9d394d991 Fix Wdocumentation warning for unknown param. NFCI. adds 9d5c29c2259 [X86][BtVer2] Limit zero idiom tests to a single iteration. adds bc083d568e6 Add a file open flag that disables O_CLOEXEC. adds 370ce5a7b00 Clean up some code in Program. adds a3869c0c219 commandLineFitsWithinSystemLimits Overestimates System Limits adds 0197608901a [X86][BtVer2] Add tests for scalar SUB/XOR instructions tha [...] adds 21448274b7f [X86][BtVer2] Remove SBB tests that were accidentally added [...] adds b76b2440ec7 [InstSimplify] add nuw %x, -1 -> -1 fold. adds 65cbabed5f8 [NFC][InstSimplify] SimplifyAddInst(): coding style: variab [...] adds a3fe40f2b02 reapply r334209 with fixes for harfbuzz in Chromium adds 8fbd41bc439 [AMDGPU] Inline asm - added i16, half and i128 types support adds 2251f252bef [X86] Fix schedule-x86_64.s tests to use different register [...] adds 63f4875014e [X86][BtVer2] Add support for all SUB/XOR 32/64 scalar inst [...] adds da19974802b [VPlan] Move recipe construction to VPRecipeBuilder. adds 27c4e626a1a Utilize new SDNode flag functionality to expand current sup [...] adds 4a49826736f [x86] regenerate test checks; NFC adds 1503b9f6fe8 [x86] add tests for node-level FMF; NFC adds a735ba5b795 [X86][SSE] Support v8i16/v16i16 rotations adds 6ad988b5998 [DAGCombiner] clean up comments; NFC adds 98c78e82f54 [asan] Instrument comdat globals on COFF targets adds 34d605cb168 [InstCombine] add llvm.assume + debuginfo test (PR37726); NFC adds 50f05d394ac [InstCombine] Skip dbg.value(s) when looking at stack{save, [...] adds 4b6d3f98cdf [SCEV] Look through zero-extends in howFarToZero adds c2adc2d4299 [SmallSet] Add some simple unit tests. adds 09c10d86a80 [ARM] Allow CMPZ transforms even if the input has multiple uses. adds 50a5ae6d027 Test commit: remove a blank line adds 0d3cb776ccf [LangRef] insertelement/extractelement return poison for ou [...] adds c035816d764 [LangRef] fptosi and fptoui return poison on overflow. adds 3f7dfd74cf8 [X86] Remove GCCBuiltin from some intrinsics so we can do c [...] adds f5137255b64 [tablegen] Improve performance on *GenRegisterInfo.inc by r [...] adds 74eba10280c Use SmallPtrSet instead of SmallSet in places where we iter [...] adds c71a2123c71 Use uniform mechanism for OOM errors handling adds 77c9bf3a4fe [X86] NFC Use member initialization in X86Subtarget adds 7e8494f5c2b [NFC][InstCombine] Tests for (x << y) >> y -> x & (-1 >> [...] adds 60e082b13fc [NFC][InstCombine] Tests for (x >> y) << y -> x & (-1 << [...] adds 1afb7bca161 [NFC][InstCombine] More tests for (x >> y) << y -> x & ( [...] adds 0c500a83b4f [CostModel][X86] Add 'select' style shuffle costs tests (PR33744) adds 861985beca4 [Support] Expose flattenWindowsCommandLine. adds eda86f5c644 Revert "[Support] Expose flattenWindowsCommandLine." adds 432c8507735 Resubmit "[Support] Expose flattenWindowsCommandLine." adds edd16bdf674 Revert "Resubmit "[Support] Expose flattenWindowsCommandLine."" adds 72d68d3473a Cleanup. NFC adds edd46a8e797 [X86] Remove masking from the 512-bit masked floating point [...] adds c5b8bcad3b7 [X86] Fix forward declaration in a test case that was messe [...] adds c7f180e8c4d [NEON] Support VST1xN intrinsics in AArch32 mode (LLVM part) adds 7d5aadaa891 [X86] Remove GCCBuiltin from some intrinsics so we can cust [...] adds 45f382c290f [x86] add tests for potentially miscompiling cvttp2si (PR37 [...] adds 62f18f97c72 [X86] Add expandload and compresstore fast-isel tests for a [...] adds 963769c2862 [NFC][InstCombine] Revisit tests for D47980 / D47981 once more. adds 69d7a864076 [InstCombine] Fold (x << y) >> y -> x & (-1 >> y) adds 67d1bbfc434 [InstCombine] Fold (x >> y) << y -> x & (-1 << y) adds bd27672ab40 Revert rL334371 / D47980: "[InstCombine] Fold (x << y) >> y [...] adds e956ae9dc32 [TableGen] Move some shared_ptrs to avoid unnecessary copie [...] adds 07d33bf7d7d Attempt 3: Resubmit "[Support] Expose flattenWindowsCommandLine." adds db3fe986cb3 Revert r334374 [TableGen] Move some shared_ptrs to avoid un [...] adds 0b9640b156c [X86] Miscellaneous fixes to get the load folding table gen [...] adds 331074fceb5 [DAGCombiner] match vector compare and select sizes with ex [...] adds 84fc2f53bf6 [TableGen] Combine two constructors by taking vectors by va [...] adds 7b57400c9da [TableGen] Make better use of std::map::emplace and emplace [...] adds 1eda80d0b06 [X86] Remove and autoupgrade the expandload and compresssto [...] adds 62178e9f4e7 [CodeView] Omit forward references for unnamed structs and unions adds 82194ab97de [Sparc] Add support for 13-bit PIC adds e5d2855ab47 [X86] Remove masking from dbpsadbw intrinsics, use select i [...] adds 713ff626ae3 [X86] Add test files for upgrade of vbmi2 expand load and c [...] adds b9583480e25 [X86] Add encoding tests for avx5124fmaps and avx5124vnni i [...] adds 76fc17f48fb [X86] Explicitly mark unsupported classes in scheduling models. adds c6d32738675 [ExynosM1][Sched] Fix resource usage in scheduling model. adds 8e5dad51ca3 [Unittests] Change linker flags of dynamic library tests adds e0003ef72cb [llvm-exegesis] Program should succeed if benchmark returns [...] adds c71ad5de2cc [Utils] update_llc_test_checks.py: support AMDGPU backend: [...] adds 8a8a7292421 [NFC][AMDGPU] Add tests for all the various IR patterns equ [...] adds 802e2f30e4a Move VersionTuple from clang/Basic to llvm/Support adds 09f0f7ccc5e Fix build errors on some configurations adds 2210d8ab6c9 [x86] add scalar cvtt intrinsic tests; NFC adds 582e5dd5553 [llvm-exegesis] Fix unhandled error. adds ca4e5225083 [X86] Fix skylake server scheduling info. adds b6377293f22 [AVR] Set trackLivenessAfterRegAlloc adds 85edf48b76e [mips] Fix spill slot for mips3, n64 abi adds 7a3f751cbc0 [AMDGPU] Do not consider indirect acces through phi for wav [...] adds 5fffef3f190 [X86][AVX512] Tag AVX5124FMAPS/AVX5124VNNIW with missing sc [...] adds 9299628cf44 [SCEV] Canonicalize "A /u C1 /u C2" to "A /u (C1*C2)". adds a6348bee3e6 [Hexagon] Late predicate producers cannot be used as dot-ne [...] adds f17b95446ce Fix indentation in ScalarEvolution.cpp. adds 109b3a6dbde [SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags where safe. adds e2401ceceba [SCEV] Add transform zext((A * B * ...)<nuw>) --> (zext(A) [...] adds 0d387f77252 [X86] Reorder some type constraints to force things to be v [...] adds 5be29b2568f Fix incorrect CHECK-LABEL adds 4128fd181f5 [SLP] Add testcases of min/max reduction pattern for AMDGPU. adds a1aabffae01 [X86] Push some variable declarations down into the individ [...] adds 696326c395a DAG: Fix extract_subvector combine for a single element adds db963fc642f AMDGPU: Add 64-bit relative variant kind adds 7f3c26cfc1a TableGen: Change some pointer parameters to references sinc [...] adds 93bc7468246 [SampleFDO] Add a new compact binary format for sample profile. adds 86ba66c945d Fix a warning reported by clang but not by gcc. adds 23bfaae29f0 Simplify; NFC adds e5839ea3a47 [CMake] Fix dropped dependency in install-llvm-headers adds baba854f8f8 Fix a warning issued by clang. adds b54c4f871a3 Fix a buildbot error reported by sanitizer-x86_64-linux-fas [...] adds 8f93b43810b [AMDGPU] prevent hitting Assertion `isReg() && "Wrong Machi [...] adds 91c6e9af6ed [X86] Add isel patterns for folding loads when creating ROU [...] adds 0f51ad9a113 NFC, some additional tests added and some renaming for plan [...] adds f7bc6cbf14d [X86] Enforce agreement of AdSize field when autogenerating [...] adds bd4977bdae9 [X86] Add NotMemoryFoldable to a bunch of instructions to s [...] adds ddabdc0f8c4 Fix a typo in rL334447. adds 7253cd85800 [NFC] Change sample profile format enum name SPF_Raw_Binary [...] adds a742c525627 [X86] Update folding table generator to properly detect RMW [...] adds 99f784907aa [X86] Add NotMemoryFoldable to more instructions. adds 36aef6e2cac [X86] Don't add stores to the autogenerated load folding ta [...] adds 2572fc691c2 [X86] Add NotMemoryFoldable to the VPCOMPRESS instructions. adds 57002750564 [CostModel][X86] Add extra Identity shuffle mask cost tests [...] adds f808d850c7c [AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns adds e0a17956246 [mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter adds a1847c760ce [mips] Guard some floating point instructions correctly adds b2621b34b75 Use SmallPtrSet explicitly for SmallSets with pointer types (NFC). adds 77ce0e565d7 [SelectionDAG] Provide default expansion for rotates adds 331580afbfe [llvm-exegesis] Move libpfm linking to LLVMExegesis. adds 4fcee8af8bc [llvm-exegesis] Sum counter values when several counters ar [...] adds 5d7877c83af [x86] move shrunkblend transform to helper function; NFCI adds 861e3f325fd [CostModel] Treat Identity shuffle masks as zero cost adds 32c8f741220 [Hexagon] Make floating point operations expensive for vect [...] adds 2ccbb4c82e7 Fix signed/unsigned warning. NFCI. adds 97c09621904 [X86] Remove TB_ALIGN_16 from VEXTRACTF128/VEXTRACTI128 in [...] adds e369b9d3709 [DWARFv5] llvm-mc -dwarf-version does not imply -g. adds 21582f2af69 [CostModel] Replace ShuffleKind::SK_Alternate with ShuffleK [...] adds b6d28af2a58 Utilize new SDNode flag functionality to expand current sup [...] adds 2307d55eeea [MC] [X86] Teach leaq _GLOBAL_OFFSET_TABLE(%rip), %r15 to u [...] adds 0dcc1159b40 Refactor ExecuteAndWait to take StringRefs. adds 299cf5ff6a8 AMDHSA: Code object v3 updates adds b1c42dee782 [MIR][MachineCSE] Implementing proper MachineInstr::getNumE [...] adds 0397fe58633 AMDHSA/NFC: Code object v3 updates (additional): adds ff373df1792 [MS][ARM64] Hoist __ImageBase handling into TargetLoweringO [...] adds 54dd30f23b3 [X86] Remove mayLoad flag from AVX512 truncating store inst [...] adds 0932f64556b [X86] Remove unnecessary include from one of the tblgen emitters. adds 0bf3db8810b [AArch64] Support reserving x20 register adds e6b73b045ef [MCJIT] Call materializeAll on modules before compiling the [...] adds 5ce15834278 [RuntimeDyld] Add an assert to catch misbehaving symbol resolvers. adds cdaeb5b41eb [ORC] Refactor blocking lookup logic into the blockingLooku [...] adds fd5548df547 [ORC] Add a fallback definition generator for VSOs. adds 68f6da04912 Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build adds 908b1550afb Add null check to Intel JIT event listener adds f38bd3d4b7f Remove malloc.h include from Intel JIT events code adds c048795fb5a [X86] add avx512 tests for potentially miscompiling cvttp2s [...] adds f173f1f1513 [DAGCombiner] Recognize more patterns for ABS adds 882a223e8aa Added missing include to AMDHSAKernelDescriptor.h adds dc0e0763cc3 [AArch64] add tests for fadd with more than one use; NFC adds 6c5eb4370b5 [AMDGPU] DAG combine to produce V_PERM_B32 adds 04bd25fad13 [X86] Remove VPCOMPRESSB/W from the autogenerated load fold [...] adds dae4c99b4e4 [X86] Mark all instructions that have masked store semantic [...] adds d4958cbf6c9 Revert "Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build" adds a1759fc9c05 [SimplifyIndVars] Ignore dead users adds d789989d532 utils/release: Add merge-git.sh adds 6c008761fa3 Set the code model when specified. adds c2287211daa [X86] Remove masking from avx512vbmi2 concat and shift by i [...] adds c271b02f295 [DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entries adds 32dae0daed5 [PowerPC] avoid verification failure due to PowerPC VSX Swa [...] adds de997703757 Fix "Optional" is ambiguous error on some bots adds a86334c256f Fix -DLLVM_ENABLE_THREADS=OFF build after r334537 adds 0ec92f80b19 [PowerPC] fix trivial typos in comment, NFC adds 83f6dc20df0 GettingStarted.rst: Fix 'If you you' typo (PR37787) adds fa81124fba4 [TableGen] Emit a fatal error on inconsistencies in resourc [...] adds 74cd05c4a4f [SLPVectorizer] getSameOpcode - remove unusued alternate co [...] adds bdc0cb64352 [SLPVectorizer] getSameOpcode - remove useless cast [NFC] adds 238154cfea3 [RISCV] Codegen support for atomic operations on RV32I adds d4b322beffb [RISCV] Add codegen support for atomic load/stores with RV32A adds 81eac77ab10 [x86] eliminate even more sign-bit tests with vector select adds eee75ac7313 Improve handling of COPY instructions with identical value numbers adds 76b46df975a [mips][microMIPS] Extending size reduction pass with LWP an [...] adds 7f976eb2808 [llvm-exegesis] Cleaner design without mutable data. adds be100d0a8dd Revert "Improve handling of COPY instructions with identica [...] adds c855277f2ae [llvm-exegesis] Fix failing assert when creating Snippet for LAHF. adds f246e3e960c [llvm-exegesis] Fix buildbot - power was using native targe [...] adds 7c4ee81607a Do not enforce absolute path argv0 in windows adds d2e44d5932d [FPEnv] Expand constrained FP operations adds 1b7a9ecfa8d [x86] add test for fadd with more than one use; NFC adds 98e05fe5290 AMDGPU: Move isSDNodeSourceOfDivergence() implementation to [...] adds 7177c61dc99 [DAGCombiner] remove hasOneUse() check from fadd constants [...] adds d77bb599aa7 [AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_ [...] adds bc8a784b07a [llvm-mca] Flush the output stream before we start the anal [...] adds 4252f6639c1 [CostModel][X86] Test showing failure to recognise BROADCAS [...] adds 10183d6bcdd Revert: [llvm-mca] Flush the output stream before we start [...] adds 31dfcf10a6f [CostModel] Recognise BROADCAST shuffle mask if the element [...] adds 3ab6afc6d27 [AMDGPU][MC] Enabled parsing of relocations on VALU instructions adds b083fc6f496 [CostModel][X86] Test showing failure to recognise REVERSE [...] adds 350359838b4 [AMDGPU] Change enqueue kernel handle type adds 941e741e9e7 IR: fix documentation markup adds 74928bc090c [X86] Add one more intrinsic and test cases to avx512-cvttp2i.ll. adds 6965c8b7610 LTO: Keep file handles open for memory mapped files. adds a71e59ebf7f [CMake] Handle 'libtool' being at a path with spaces in it. adds 2a8508d8ca6 [llvm-mca] Fixed a bug in the logic that checks if a memory [...] adds ba86f98ba71 Change checked arithmetic functions API to return Optional adds b97b3021fc7 Add checkMulAdd helper function to CheckedArithmetic adds 822ea1bfe89 [AMDGPU] Corrected computeKnownBits for V_PERM_B32 adds 4090b47b77e Enable ThreadPool to support tasks that return values. adds c2bd08fe6e9 Add missing #include. adds eadd795fa31 [X86] Move RCPSSr_Int, RSQRTSSr_Int, SQRTSDr_Int, SQRTSSr_I [...] adds a9ac180f032 [Timers] Use the pass argument name for JSON keys in time-passes adds 529fb8b5cd3 Revert r334649 "[Timers] Use the pass argument name for JSO [...] adds 0bcb48f4feb [WinASan] Don't instrument globals in sections containing '$' adds b7135866e31 Update comments of CheckedArithmetic API based on Philip Re [...] adds 77fc0e91191 [TableGen] Make getOnlyTree return a const ref (NFC) adds 68d5d59240f Reland: [Timers] Use the pass argument name for JSON keys i [...] adds 7c17201f14c Revert "Enable ThreadPool to queue tasks that return values." adds 2cf1b47d895 AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL adds fce447566ae [llvm-mca] Introduce the ExecuteStage (was originally the S [...] adds 3a81c6c6976 [x86] fix mappings of cvttp2si/cvttp2ui x86 intrinsics to x [...] adds 26570985ef8 [NFC] fix trivial typos in comments adds 49fb4d413fc [llvm-exegesis] Use BenchmarkResult::Instructions instead o [...] adds d9dafe02fb7 [CostModel] Recognise REVERSE shuffle mask if the elements [...] adds 419887cd06b [CostModel] Cleanup isSingleSourceVectorMask to match other [...] adds d5f3b742c05 [SLPVectorizer] Remove RawInstructionsData/getMainOpcode an [...] adds 45a02a4f847 [DebugInfo] Check size of variable in ConvertDebugDeclareTo [...] adds 5cd96b7a00b [TableGen] Move some shared_ptrs to avoid unnecessary copie [...] adds 5cadc32f5f8 [EarlyCSE] Propagate conditions of AND and OR instructions adds 9a849b0187f [mips] Correct predicates for MSA pseudo instructions adds d796da8a357 [DWARFv5] Tolerate files not all having an MD5 checksum. adds 28809c071a5 [MC] Move MCAssembler::dump into the correct cpp file. NFC adds 8859b11a893 [CostModel][AArch64] Add cost tests for ALTERNATE/SELECT st [...] adds ad70f357e8c [EarlyCSE] Fix MSVC build. NFCI. adds 385d0da89cd [docs] Update CompilerWriterInfo.rst for MIPS adds 103c75a7dba [ORC] Strip the Materializing flag off finalized symbols in VSOs. adds 26907984ce2 [ORC] Add a WaitUntilReady argument to blockingLookup. adds 6ba3aa8738c [ORC] Assert that the query argument to VSO::lookup must be [...] adds c6679d1e091 [ORC] Filter out self-dependencies in VSO::addDependencies. adds 474c12cb486 [X86] Remove NotMemoryFoldable from some AVX/AVX512 scalar [...] adds 8a9fc632eb3 [X86] Disable load unfolding for a bunch of instruction whe [...] adds a56239d6e3b [X86] Remove '128' from the internal name of some scalar FP [...] adds b179f7438dc [X86] Add more vector instructions to the memory folding ta [...] adds f5c585b6fde [DAG] Avoid needing to walk out legalization tables. NFCI. adds c8cb969dd34 [llvm-mca] Add another test for partial register stalls. adds 8f682e9960c Avoid unused variable in non-assert builds. adds 2522f2ba38c Revert rL334704: "[DebugInfo] Check size of variable in Con [...] adds 978dec7518f [AMDGPU] Document the AMDGPU LLVM attributes adds 80e4916fc94 Revert "[MC] Factor MCObjectStreamer::addFragmentAtoms out [...] adds bcaa1096524 [SCEV] Fix indentation and combine two if statements in get [...] adds 4090ce2a163 [SCEV] Simplify trunc-of-add/mul to add/mul-of-trunc under [...] adds 3edd5bf9082 [SCEV] Simplify zext/trunc idiom that appears when handling [...] adds ad5cfb94bc2 [SCEV] Fix a variable name, NFC. adds 64bb270506e [X86] Lowering Mask Scalar intrinsics to native IR (LLVM part) adds 8fc6007820f [llvm-mca] Add tests for instructions that implicitly clear [...] adds d1d28702c60 [x86] add tests for AVX1 FP logic op abuse (PR37749); NFC adds 7d3355e4023 [CMAKE] Honor CMAKE_OSX_SYSROOT to compute include dir for libxml2 adds a1b4efd4bd8 [VirtRegRewriter] Avoid clobbering registers when expanding [...] adds 10cde000da8 [WebAssembly] Ignore explicit section names for functions adds 4bfcd6ff018 updating isNegatibleForFree and GetNegatedExpression with f [...] adds a9f3f668fce Revert "[VirtRegRewriter] Avoid clobbering registers when e [...] adds 3d2940410bd Re-apply "[VirtRegRewriter] Avoid clobbering registers when [...] adds b4220f48edb AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz adds b261e10390f [X86] Fix stale comment in folding tables. adds a641736633a [x86] be more selective about converting 'and' to shuffle ( [...] adds 1967f637b47 [MSSA] Print more optimization information adds cf7e990880a [TableGen] Make TreePatternNode::getChild return a reference (NFC) adds 74dff3bf019 Revert r334764, as it breaks some bots adds 11f1b27ce76 easing the constraint for isNegatibleForFree and GetNegated [...] adds c14f322145d [llvm-mca] Clean up the header comment. NFC. adds a94df7d526c [ORC] Strip weak flags from a symbol once it is selected fo [...] adds caa16eabb4f Make uitofp and sitofp defined on overflow. adds 4ec881844ea [cmake] Add linker detection for Apple platforms adds 3f58912081a [cmake] Change ON/OFF to YES/NO. NFC adds 156c4a865a2 Add debug info for OProfile profiling support adds 61c89e393d2 [X86] Add 'Z' to the internal names of various EVEX instruc [...] adds 99f3bc505ac [X86] Fix some checks to use X86 instead of X32. adds 96dcb6683ea [NFC] fix trivial typos in documents adds 055e27a2ce1 [X86] Add more instructions to the memory folding tables us [...] adds f26b24c4879 [X86] Prevent folding stack reloads with instructions that [...] adds f045c54f1a4 Revert r334802 "[X86] Prevent folding stack reloads with in [...] adds 480c306fdd4 [llvm-exegesis] Print the whole snippet in analysis. adds 0f100d9444c NFC: Regenerating x86-sse41.ll test for InstCombine adds 86935c1b432 add myself to the CREDITS.TXT adds 089aa0bc9b7 [llvm-exegesis][NFC] Add more comments. adds 34ed662e9f0 [llvm-exegesis][NFC] Remove dead variable. adds 565bf54c1cd [MC] Move bundling and MCSubtargetInfo to MCEncodedFragment [NFC] adds 1d9a02a498e [AMDGPU] Recognize x & (-1 >> (32 - y)) pattern. adds fc84800456f [AMDGPU] Recognize x & ((1 << y) - 1) pattern. adds f2c20b5ace4 [AMDGPU] Recognize x & ~(-1 << y) pattern. adds ae2a6132b3b [InstCombine] Recommit: Fold (x << y) >> y -> x & (-1 >> y) adds b753b187857 [SLP][X86] Regenerate POW2 SDIV Tests adds afe3129d8f1 [SLP][X86] Add AVX2 run to POW2 SDIV Tests adds bd512dd0f9d DAG: Fix creating concat_vectors with illegal type adds f58bfff04c8 [NFC] chmod +x utils/update_analyze_test_checks.py adds dde50dc1333 [AArch64][SVE] Asm: Add parsing/printing support for exact [...] adds 16d63b172e6 [mips] Add licensing information of the microMIPS tablegen [...] adds 0ac3f0a4d93 Re-apply "[DebugInfo] Check size of variable in ConvertDebu [...] adds 4ba09bb3877 [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immedia [...] adds cedc64e7712 [MCA][x86][NFC] Add tests for -register-file-stats, -schedu [...] adds 6fe55f4897b [MCA] Add -summary-view option adds 064db4306cf [llvm-readobj] Add -string-dump (-p) option adds 9e41f5314eb AMDGPU: Make v4i16/v4f16 legal adds bd0b6b0e98c AMDGPU: Add combine for short vector extract_vector_elts adds df60d71070b [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions. adds ff160b6333c [LV] Prevent LV to run cost model twice for VF=2 adds 187c713c759 Avoid copying PrettyStackTrace messages an extra time on Apple OSs adds 4b7915e49a5 [AArch64][SVE] Asm: Support for CPY SIMD/FP and GPR instructions. adds 52d8fd61eab [InstCombine] Avoid iteration/mutation conflict adds 69ccb71234d Remove <undef> from rematerialized full register adds 26658355771 [X86] Prevent folding stack reloads into instructions in ha [...] adds a36133dda76 [X86] Lowering sqrt intrinsics to native IR adds a292a774936 [llvm-mca][x86] Add Generic cpu resource tests adds 3a32fa4e62f Move redundant-vf2-cost.ll test to X86 directory adds 80cb547d115 [PPC64] Support "symbol@high" and "symbol@higha" symbol modifers. adds a24485376e7 [PowerPC] Add support for high and higha symbol modifiers o [...] adds f1d55911bf1 Update my information in the CREDITS file. adds 9fcdc897848 [SanitizerCoverage] Add associated metadata to pc-tables. adds 97de3c8816c Utilize new SDNode flag functionality to expand current sup [...] adds b7012eca07e [FPEnv] Expand constrained FP POWI adds 3874a4ab05e [BPI] Remove unnecessary std::list adds 9dda3f52a16 [X86] Add more instructions to the hasUndefRegUpdate list. adds b3fd12d9135 Revert r334731 "Avoid unused variable in non-assert builds." adds c8f69e3a9e1 Revert r334729 "[DAG] Avoid needing to walk out legalizatio [...] adds a2824b68e64 [globalisel][tablegen] Add support for C++ predicates on Pa [...] adds 5802a4a49f0 [SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV. adds dc96bffe352 [SCEV] Simplify some flags expressions. adds f4fa78a051e Utilize new SDNode flag functionality to expand current sup [...] adds e743a53c301 Revert "[SCEV] Simplify some flags expressions." -- depende [...] adds cfc2fa9b55f Revert "[SCEV] Use LLVM_MARK_AS_BITMASK_ENUM in SCEV." -- b [...] adds 885e8cb3716 Avoid needing to walk out legalization tables. NFCI. adds ec4b3c5670b [AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | cc adds 348096519ed [SmallSet] Add SmallSetIterator. adds e15abbe6b09 [SmallSet] Avoid using is_trivially_XXX<>::value which is C++17 adds 6b5cc847798 Revert r334887, as GCC 4.8 does not have is_trivially_copy_ [...] adds c011f6948e8 Fix namespaces. No functionality change. adds 5e8f334dfad [Dominators] Change getNode parameter type to const NodeT * (NFC). adds 273aba7517d CorrelatedValuePropagation: Preserve DT. adds ea330bd0863 [X86] Fix an inconsistency between AVX512 and AVX/SSE versi [...] adds 86126e4b16f [X86] Hide POP16/32/64rmr and PUSH16/32/64rmr instructions [...] adds 73b1acb59c8 [X86] More additions to the load folding tables based on th [...] adds 011c97ec87d [WebAssembly] Simple comment fix. NFC. adds 572d25bd9ae [NVPTX] Ignore target-cpu and -features for inlining adds cac4c4a7c45 [AArch64][SVE] Asm: Support for SEL (vector/predicate) inst [...] adds 59cb663e728 [AArch64][SVE] Asm: Support for bitwise operations on predi [...] adds a9e397149a0 [llvm-mca][X86] Add some avx512f/avx512vl resource test pla [...] adds 07beb491a5a [X86] Pass the parent SDNode to X86DAGToDAGISel::selectScal [...] adds e1646eb2429 [ORC] In MaterializationResponsibility, only maintain the M [...] adds 05afd8a0292 [ORC] Erase empty dependence sets when adding new symbol de [...] adds 501141aa483 [ORC] Suppress an unused variable warning for a debug-mode [...] adds 77b50e463e2 [X86] Add all the FMA instructions direclty to the load fol [...] adds 00bb1a1722b [ORC] Only notify queries that they are resolved/ready when [...] adds 174673f81e9 [ORC] Remove redundant condition adds 50ea5bbb2de [TableGen] Prevent double flattening of InstAlias asm strin [...] adds 3ac0bd33037 [X86] Move the 'vmovq.s' and similar assembly strings for E [...] adds 3f833442570 [X86] Add '.s' aliases to the assembler for the various red [...] adds c6145b53bbc [X86] Create X86InstrFMA3Group objects fully in a static ta [...] adds 637504b2179 [X86] Fix NOOP sched overrides on BDW/HSW/SKL. adds 001626f17f7 [AArch64][SVE] Asm: Support for vector element compares. adds 288479f35ce [llvm-exegesis] Optionally ignore instructions without a sc [...] adds c74d4477808 [VPlanRecipeBase] Add insertBefore helper. adds 640b8b82cca [SLPVectorizer] Avoid calling const VL.size() repeatedly in [...] adds 74a06eaa778 Update copyright year to 2018. adds b0c87384295 [TableGen][AsmMatcherEmitter] Allow tied operands of differ [...] adds 6e8480a8e50 [VPlan] Fix sanitizer problem with insertBefore. adds 0f51d6d4e97 [llvm-mca] Add tests for XOP and AVX512 instructions that i [...] adds a5ac3f909cd [X86][BtVer2] Flag AVX2+ scheduler classes as unsupported adds 3e3bddcaee1 [AArch64][SVE] Asm: Support for saturating INC/DEC (64bit s [...] adds 11952d0f055 [VPlanRecipeBase] Add eraseFromParent(). adds 61d5cb52aa2 [TableGen] Remove unused member variable. adds 46cd4ae5856 [TableGen] Make TiedAsmOperandTable in the AsmMatcher 'stat [...] adds e375af8c1df [SLPVectorizer] Tidyup isShuffle helper adds 85385783058 Fix typoed cast to avoid assertion in MCFragment::dump. adds c75619bff71 [llvm-mca] Use an ordered map to collect hardware statistics. NFC. adds db53e01a534 Shrink interval after moving copy in removePartialRedundancy adds dcd570fed75 [ORC] Keep weak flag on VSO symbol tables during materializ [...] adds 69791607398 [ORC] Add an initial implementation of a replacement Compil [...] adds b838c5c3d3a [VPlan] Add VPInstruction to VPRecipe transformation. adds 6f176b72c14 [NFC] make MIFlag accessor functions consistant with usage model adds 2bcbecf8527 [X86] Encode the EVEX2VEX exception list information in .td [...] adds 6cc4ab33f06 [docs] Fix indentation of llvm-exegesis command line arguments adds d388cdf1acf [x86] regenerate checks and adjust tests adds 2fff458e8e0 [WebAssembly] Cleaned up register accessors in WebAssemblyM [...] adds 38d82ac61bb [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit s [...] adds 49b7c4d0fb2 [AArch64][SVE] Asm: Fix predicate pattern diagnostics. adds 98cc0668579 refactor of visitFADD for AllowNewConst cases adds 17406f3a2a4 [WebAssembly] Modified tablegen defs to have 2 parallel ins [...] adds f9dc097e14c [llvm-mca] Cleanup the header syntax line. Fix a comment. NFC. adds 2a6f354a56e Tests for dag combine select (binop) -> select. NFC. adds ba9ac3034cc Add return statements to make it clear that all of these ar [...] adds 2bb865e0098 Pull non-lazy stub table emission into a separate function [...] adds 6368868d2eb Tidy comment language and explanation. adds f976cf4cca0 Simplify blockaddress usage before giving up in MergeBlockI [...] adds 849db7fa025 Revert "Simplify blockaddress usage before giving up in Mer [...] adds 8187a5bc6df [X86] Remove ReadAfterLd from avx512_shift_rmbi multiclass. adds 56057ccc175 Utilize new SDNode flag functionality to expand current sup [...] adds a800b896797 [VPlan] Add Analysis and Core to LLVM_LINK_COMPONENTS adds f1fc1ae9b77 [WebAssembly] Make rethrow instruction take a target BB argument adds f135420eabe [WebAssembly] Fixed disassembler unit test failure. adds 7d6421e0edc [ARM] Testcase for missed optimization with i16 compare. adds f5b3e111649 [ARM] Testcase for missed optimization for masking. adds 959e5f81645 [ARM] Add Thumb1 coverage for cmn testcases. adds 9ba2448193a [ARM] Testcase for Thumb1 cmp with constants. adds f6172a9f68f [ARM] Thumb2 constant cmp testcases. adds c430c830299 [WebAssembly] Add WasmEHFuncInfo for unwind destination inf [...] adds dba082adc8c [WebAssembly] Add more utility functions adds ce641730174 [WebAssembly] Remove an extra ';' at the end of a namespace adds fe7e53ea94c [X86] Simplify the TSFlags checking code in EvexToVexInstPa [...] adds 1a6eaebd1c3 Revert "[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags" adds 023b407c112 [X86] Add a new VEX_WPrefix encoding to tag EVEX instructio [...] adds e5b799ba09a [X86] Add the ability to force an EVEX2VEX mapping table en [...] adds 634dad18405 [SimplifyIndVars] Eliminate redundant truncs adds ef2db721dbe [RISCV] Add tests for overflow intrinsics adds 21cf43199f6 If the arch is P9, we will select the DFLOADf32/DFLOADf64 p [...] adds f356e3e089a Test commit. adds 6517111aa98 [LoopInterchange] Move PHI handling to adjustLoopBranches. adds 96f21df4487 Add a factory method to ConstantDataArray that allows to pa [...] adds 339ffa44503 Remove valueCoversEntireFragment asserts in ConvertDebugDec [...] adds eb242d5190d [SLPVectorizer] Pull out AltOpcode determination from reord [...] adds 857083aa705 [MCA][NFC] Add generic TBM resource tests adds 00258393d41 [MCA][NFC] Add generic XOP resource tests adds d6cd67b722e [LoopSimplifyCFG] Invalidate SCEV in LoopSimplifyCFG adds be59eb33a04 [X86] VRNDSCALE* folding from masked and scalar ffloor and [...] adds fdc767cc014 [llvm-exegesis] A mechanism to add target-specific functionality. adds 53ba989b547 [InstCombine] Replacing X86-specific rounding intrinsics wi [...] adds 0dae1a0252b Revert r335038 "[llvm-exegesis] A mechanism to add target-s [...] adds 41d0646d59b Re-land r335038 "[llvm-exegesis] A mechanism to add target- [...] adds ba6893f3827 llvm-exegesis: mark ~ExegesisTarget() as virtual. Fixes build. adds 96f8f2ad399 [PowerPC] Fix label address calculation for ppc32 adds 4c0259dd2ec [SLPVectorizer] Remove default OperandValueKind arguments f [...] adds 58b1f43714c [mips] Fix the predicates of some aliases adds 9331b2fae1f [mips] Mark microMIPS64 as being unsupported. adds b07f54afdc8 docs: document CodeView directives adds 3e9f1c2ce41 [Hexagon] Enforce restrictions on packetizing cache instructions adds 54edf4671d5 [X86] Don't fold unaligned loads into SSE ROUNDPS/ROUNDPD f [...] adds fbe156db3c2 [X86] Initialize FMA3Info directly in its constructor inste [...] adds c0ac3859b1c [Hexagon] Fix the value of HexagonII::TypeCVI_FIRST adds dfd20c40909 [MIRParser] Update a diagnostic message to use the correct [...] adds 42f462a3924 [IR] move shuffle mask queries from TTI to ShuffleVectorInst adds 6cf6b0aaa21 [X86] Add fast-isel tests for clang's AVX512F vector reduct [...] adds c57aba1e3b6 [X86] Update fast-isel tests for clang's avx512f reduction [...] adds a587557962e [WebAssembly] Fix liveness tracking info after drop insertion adds 19d4a02944e [MachineOutliner] NFC: Remove insertOutlinerPrologue, renam [...] adds 19036ee759d [InlineSpiller] Fix a crash due to lack of forward progress [...] adds 9808fe2d204 [llvm] Document "%T" as deprecated in TestingGuide.rst adds 83a6451ad7a [IR] Introduce helpers to skip debug instructions (NFC) adds ab9dc9af98b Revert r334980 and 334983 adds abee837d01a Add more test cases for deopt-operands via regalloc adds 05f7051a703 [X86] Use binary search of the EVEX->VEX static tables inst [...] adds 9ba4465e430 [SelectionDAG] Don't crash on inline assembly errors when t [...] adds 7d845da765e [X86] Remove a fptosi from the test_mm512_mask_reduce_max_p [...] adds 09d5b89fff4 [DAGCombiner] Add some comments to some true/false argument [...] adds 73d058aa97f [NFC] fix trivial typos in comments adds c04abfa0f05 [X86] Add sched class WriteLAHFSAHF and fix values. adds 0a7982e9622 [X86] Fix r335097 adds dbef69f000e [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity. adds 6bfac2f4039 [PatternMatch] Add m_Store pattern match helper adds 7e9ed1d023d [NFC][SCEV] Add tests related to bit masking (PR37793) adds b1497a74adb [llvm-exegesis] Use a Prototype to defer picking a value fo [...] adds 92bc62dc3d8 [Support] Add missing includes of <system_error> for std::e [...] adds 42ed299d09e [llvm-exegesis] Fix missing move in r335105. adds 4234b30a977 [llvm-exegesis] Remove noexcept in r335105. adds 315f4d08af2 [SLPVectorizer] Split Tree/Reduction cost calls to simplify [...] adds 9fc96b89c9e [llvm-mca][X86] Teach how to identify register writes that [...] adds 793551740ba [llvm-exegesis] Fix failing test. adds 859d0672979 [llvm-exegesis] Add mechanism to add target-specific passes. adds da491f7dbfe [AArch64] Implement FLT_ROUNDS macro. adds 4d3b2120989 ARM: convert ORR instructions to ADD where possible on Thumb. adds 1fcac9fd7e3 [RISCV] Add InstAlias definitions for sgt and sgtu adds a5181ab9143 [InstCombine] ignore debuginfo when removing redundant assu [...] adds bad6cbc0b30 [mips] Fix the predicates of some DSP instructions from Add [...] adds 1979d71cfcb [Hexagon] Remove 'T' from HasVNN predicates, NFC adds 60b40e954b2 [ADT] Allow llvm::hash_code as DenseMap key. adds 52d71b29980 [X86] Adding a test for PR37879 adds 9a06968c69a [RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d} adds f4f8a442ba9 [InstSimplify] Add tests for missed optimizations in simpli [...] adds 0da71804c34 [InstSimplify] Fix missed optimization in simplifyUnsignedR [...] adds 2970a295669 [SLPVectorizer] Relax "alternate" opcode vectorisation to w [...] adds 27bb5a7b489 [llvm-mca] use APint::operator[] to obtain the bit value. NFC adds cac51ca1a67 [SLPVectorizer] Use InstructionsState to record AltOpcode adds 9d9298bf57f [WebAssembly] Update know failures for the wasm waterfall adds 737553be0c9 [LIT] Enable testing of LLVM gold plugin on Mac OS X adds c578b9b40a0 [DAG] Fix and-mask folding when narrowing loads. adds 105d2e890f9 [DAG] Don't map a TableId to itself in the ReplacedValues map adds cb219d00892 [SLPVectorizer] Move isOneOf after InstructionsState type. NFCI. adds 19357eaea4f Remove a redundant initialization. NFC adds 1d36450d245 [Local] Add a utility to insert replacement dbg.values, NFC adds 444617b4b37 IRMover: Account for matching types present across modules adds 92dc883a08b [DWARF] Don't keep a ref to possibly stack allocated data. adds a65852c5d74 [PredicateInfo] Order instructions in different BBs by DFSNumIn. adds d8be43c3da2 [InstCombine] add vector select of binops tests (PR37806) adds a8d65426c85 [Local] Generalize insertReplacementDbgValues, NFC adds e9f7c281fcd [MachineOutliner] Add debug info test for the outliner adds c409a140899 [RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for [...] adds 224eb0a7853 [PM/LoopUnswitch] Support partial trivial unswitching. adds 882235cf443 [IR] add/use isIntDivRem convenience function adds 40afa1876fd [Hexagon] Replace .ll test for expanding post-ra pesudos with .mir adds f5aaf7216c2 AMDGPU: Fix missing C++ mode comment adds eb6f9a11dbd AMDGPU: Fix scalar_to_vector for v4i16/v4f16 adds 2bdc7ff150b [mips] Correct predicates for loads, bit manipulation instr [...] adds 55348758ce1 [InstCombine] fix typo in test comment; NFC adds 3e703da2578 Allow binop C1, (select cc, CF, CT) -> select folding adds 346e379f2f6 [SLPVectorizer] Provide InstructionsState down the BoUpSLP [...] adds a1276218c0e [X86] Use setcc ISD opcode for AVX512 integer comparisons a [...] adds af6c3e6dec7 [MemorySSA] Verify Phi incoming blocks are block predecessors. adds b8b321ac76b [Dominators] Simplify child lists and make them deterministic adds af5dcf12477 Remove myself from the release testers list. (NFC) adds 673b97ff71a [MemorySSA] Add convenience APIs in updater to avoid needing MSSA. adds 6de04e40d0b Fix WasmEHFuncInfo.h to include what it uses adds 8d9ac7ff948 Generalize MergeBlockIntoPredecessor. Replace uses of Merge [...] adds a5a4f60b044 [mips] Add microMIPS specific addressing patterns. adds 5a4174c5401 [DWARF] Improved error reporting for range lists. Errors fo [...] adds c7b8c8c6a7e [SCEV] Improve zext(A /u B) and zext(A % B) adds 956efeeb271 Revert "[SCEV] Improve zext(A /u B) and zext(A % B)" adds cb5e58dbd93 [X86] Remove masking from 512-bit floating max/min intrinsi [...] adds f7c66a1b63d ProvenanceAnalysis: Store WeakTrackingVH instead of Value* [...] adds 5acb50cf5a8 [RISC-V] Fix a test case to not include label names as thos [...] adds b92fd73274f [PM/LoopUnswitch] Add partial non-trivial unswitching for i [...] adds c076ce0306b [X86] Go through some tests that still reference old intrin [...] adds 57db0178ea6 [DebugInfo] Keep DBG_VALUE undef in LiveDebugVariables adds cb4031ebdb9 Recommit r333268: [IPSCCP] Use PredicateInfo to propagate f [...] adds 54da16e23ff Add some explanatory text to the associated symbol support. adds 242cb920fb8 Remove FIXME comment about WIP. This is the only line other [...] adds 2e8cb93a84a [DAGCombine] Fix alignment for offset loads/stores adds b631bebeea3 CODE_OWNERS: Take ownership of the MIPS backend adds b16b4ba59a7 [DebugInfo] Make sure all DBG_VALUEs' reguse operands have [...] adds c660be2252a [SLPVectorizer][X86] Add horizontal add/sub tests adds 400b266d8fd [X86][AVX] Reduce v4f64/v4i64 shuffle costs (PR37882) adds 6f9eeb289a7 [DA] Enable -da-delinearize by default adds b36f9319d34 [llvm-mca] Updates comment in code, and remove some stale c [...] adds 9f2ffce7cdc TableGen: Allow foreach in multiclass to depend on template args adds 3bd8feb970a AMDGPU: Turn D16 for MIMG instructions into a regular operand adds 6694c8fd847 AMDGPU: Add implicit def of SCC to kill and indirect pseudos adds f474189510d AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM) adds 2b1cd517a0e TableGen/SearchableTables: Support more generic enums and tables adds db5003ee85e AMDGPU: Use generic tables instead of SearchableTable adds f6113ec066b AMDGPU: Refactor MIMG instruction TableGen using generic tables adds d42a61b0d4f AMDGPU: Select MIMG instructions manually in SITargetLowering adds 330c65751e0 AMDGPU: Convert test cases to the dimension-aware intrinsics adds 7f7cea53068 InstCombine/AMDGPU: Add dimension-aware image intrinsics to [...] adds 4c3fa871b5a AMDGPU: Remove old-style image intrinsics adds ec3300aa1eb AMDGPU: Remove redundant MIMG instruction variants adds 21650449492 [CodeGen] Avoid handling DBG_VALUE in LiveRegUnits::stepBackward adds 11ef9aa12e6 [llvm-exegesis][NFC] Simplify LLVMState. adds 660c8bd9ccd [x86] Lower some trunc + shuffle patterns to vpmov[q|d][b|w] adds 016054315fd [RISCV] Tail calls don't need to save return address adds 34d9682fc55 [llvm-exegesis][NFC] Simplify BenchmarkRunner. adds a3ff01d1016 [NFC][ARM] ldrd/strd negative tests adds e43452878c7 [InstCombine] make div/rem vector constant utility function; NFCI adds 3cd5aad15cf [ARM] Enable useAA() for the in-order Cortex-R52 adds 8f072ac5b47 DAG combine "and|or (select c, -1, 0), x" -> "select c, x, 0|-1" adds 3080dcbe49e Revert "[AArch64] Coalesce Copy Zero during instruction selection" adds 22a1ef14bd6 [DWARF] Warn on and ignore ".file 0" for DWARF v4 and earlier. adds 2c7b1285044 [X86] Update fast-isel tests for clang r335253. adds baa9ccee642 [LoopVectorize] regenerate full checks; NFC adds 1a4304a1326 [InstCombine] simplify binops before trying other folds adds 7cf22ab2fa6 [InstCombine] add vector icmp tests with undefs; NFC adds 83601e52b86 [InstCombine] use constant pattern matchers with icmp+sext adds 50feec5fc15 [DebugInfo] Ignore DBG_VALUE instructions in PostRA Machine Sink adds e9f0bb45ca2 [InstCombine] add tests for shuffled cmps; NFC adds 3316883bba1 AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z and everythin [...] adds cbeaa8b0e2b [AMDGPU] Fix bug with tracking processed blocks in SIInsert [...] adds 8070954cd26 [mips] Modify comment to test new email address (NFC). adds 5119d140c56 Revert r335206 "Recommit r333268: [IPSCCP] Use PredicateInf [...] adds 43cbf8d92e1 [AMDGPU] Update assembler for HSA Code Object v3 adds d7f1ecfded0 [InstCombine] fold vector select of binops with constant op [...] adds 845b439bb4d [mingw] Fix GCC ABI compatibility for comdat things adds 13b063fc366 AMDGPU: Remove ability to reserve VGPRs for debugger adds 2c2fae3d83a [SCEV] Re-apply r335197 (with Polly fixes). adds 01b1faf66c2 [dsymutil] Force mmap'ing of binaries adds f257d99f7ac [GVN] Avoid casting a vector of size less than 8 bits to i8 adds 85adb3cc4d3 [X86] Implement more of x86-64 large and medium PIC code models adds 4f887057969 [X86] Commit some comments that weren't in the medium code [...] adds b3881872a5b Revert r335297 "[X86] Implement more of x86-64 large and me [...] adds e204dd61053 [IR] fix typo in comment; NFC adds 7bbbb631136 [AMDGPU] Fix lit failures introduced in r335281 adds ebb24b101d3 [gdb] Update llvm::Optional adds b9c0a17b9f2 [X86] Fix 32-bit mingw comdat names, only add one underscore adds 3499852bee2 [Instrumentation] Add Call Graph Profile pass adds 0225aa982fb AMDGPU/GlobalISel: Implement select() for G_IMPLICIT_DEF adds d8c64fc2479 [InstCombine] add test for shuffle-of-binops; NFC adds 7fe9364c8bd [InstCombine] fix shuffle-of-binops bug adds 56a5b2a5021 Fix test failures after r335306 due to the pipeline changing. adds b93460fa625 AMDGPU/GlobalISel: Implement select() for COPY adds 20f413f83a2 AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP adds 762b38dd8c7 [LegacyPM] Fix PR37888 by teaching the legacy loop pass man [...] adds 3e9055c7ee0 AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR adds fc57ceaf39a AMDGPU/GlobalISel: Default to using TableGen'd instruction [...] adds 8e0778c059f Revert r335306 (and r335314) - the Call Graph Profile pass. adds 516c1f140bf [X86] Changing the check for valid inputs in combineScalarToVector adds 71f8b0dc815 [Evaluator] Improve evaluation of call instruction adds ae175dfe4a8 AMDGPU: Add patterns for i32/i64 local atomic load/store adds 2ee51272b7b [ARM] ARMv6m and v8m.baseline strict align adds 5af2b9cbf51 Revert r335324 due to a builtbot failure adds 5f1676b4d69 Reverting r335326 while I look at the test failure adds 444b60212b3 [CostModel][AArch64] Add some initial costs for SK_Select a [...] adds 9104c92c0b2 Recommit of r335326, with the test fixed that I missed. adds 08d6b0d9f09 [MC] - Add .stack_size sections into groups and link them w [...] adds 51ddc3757af Revert r335332 "[MC] - Add .stack_size sections into groups [...] adds 0b0278f11bc [IR] Use Instruction::isBinaryOp helper instead of raw enum [...] adds af362952328 Recommit r335333 "[MC] - Add .stack_size sections into grou [...] adds 4578386457e [X86] Add notes to a few intrinsics adds dce4487f88e [X86] Regenerate tests to include fma comments adds bbfb91da0db [InstCombine] rearrange shuffle-of-binops logic; NFC adds a054f92cdc4 [InstCombine] add tests for shuffle-with-different-binops; NFC adds bcfb546743a [InstCombine] add shuffle+binops test from PR37806; NFC adds 1c5cdb19a65 [SLPVectorizer][X86] Add alternate opcode tests for simple [...] adds ae9a1a8ee73 [SLPVectorizer] Relax alternate opcodes to accept any Binar [...] adds fe16001dba2 [DWARFv5] Allow ".loc 0" to refer to the root file. adds ee3b840397f Fix test, nop is not always 1 byte adds 2b353500d1f Fix test again, try to keep all targets happy adds 6c358ea8178 [SLPVectorizer] reorderAltShuffleOperands should just take [...] adds 6299c235bdb [llvm-mca] Introduce a sequential container of Stages adds e0f992ea7d9 [llvm-mca] Set the operand ID for implicit register reads/w [...] adds 5a40cf86395 [SLPVectorizer] Support alternate opcodes in tryToVectorizeList adds d407e550d93 Initialize LiveRegs once in BranchFolder::mergeCommonTails adds 2191fc0b67c [X86] Add a test to show missed opportunity to generate vfnmadd adds 18c02e94e56 [llvm-mca] Remove redundant call. NFC adds 53f3ded93d2 [LoopUnswitch]Fix comparison for DomTree updates. adds 8a152c54c40 [X86] Don't allow ESP/RSP to be used as an index register i [...] adds b6b723f1bfa [X86][AsmParser] Check for invalid 16-bit base register in [...] adds be92ae330e4 [X86][SSE] Add sdiv by (nonuniform) minus one tests (PR37119) adds d6794f0ba70 AMDHSA: Put old assembler docs back adds 122aad957dc [X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encode [...] adds 528e0780e70 [X86] Don't accept (%si,%bp) 16-bit address expressions. adds aa1b399a8ef Re-land "[LTO] Enable module summary emission by default fo [...] adds c22e38d4bb9 [gdb] Use Latin-1 to decode StringRef adds d327d4b2a87 [GISel]: Add G_ADDRSPACE_CAST Opcode adds 3d48ff1d0ac [X86] Add test cases showing missed select simplifcation fo [...] adds 5fd79cfd40a [PowerPC] add tests for bit hacking opportunities with setcc; NFC adds 3a06bb23c20 [x86] add tests for bit hacking opportunities with setcc; NFC adds 5db13ccfe97 [llvm-mca] Remove unnecessary include and forward decl in R [...] adds 7259aa5c9bc [X86][AsmParser] In Intel syntax make sure we support ESP/R [...] adds 31d9a1568ae [PowerPC] add more tests for bit hacking opportunities with [...] adds 3d59bc03425 [x86] add more tests for bit hacking opportunities with setcc; NFC adds a64c3aa1f5d [llvm-size] Make global variables static adds 61a101317c7 [X86][AsmParser] Keep track of whether an explicit scale wa [...] adds 78cd292954d [MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFC adds ea67fb768b2 [LoopReroll] Rewrite induction variable rewriting. adds 10fa02975bc [RuntimeDyld] Implement the ELF PIC large code model relocations adds ba5eea78819 [X86][AsmParser] Rework that allows (%dx) to be used in pla [...] adds 98ae3708b44 [ELF] Change isSectionData to exclude SHF_EXECINSTR adds dc14c20b63e Avoid including intrin.h from MathExtras.h adds af7c445dfa1 [IR] Split Intrinsics.inc into enums and implementations adds adc5f0ab257 [ORC] Fix formatting and list pending queries in VSO::dump. adds 00f00bab006 [AMDGPU] Update includes for intrinsic changes :( adds 17957ec5e50 Fix invariant fdiv hoisting in LICM adds af8308f06ae [X86][AsmParser] Improve base/index register checks. adds 4fc14da1fc9 [X86] Teach disassembler to use %eip instead of %rip when 0 [...] adds b457430300d [X86] Make %eiz usage in 64-bit mode, force a 0x67 address [...] adds 9fa78621e77 [TableGen] Use WithColor for printing errors/warnings adds fb0b759b0a2 [llvm-mt] Use WithColor for printing errors. adds fc6fcece238 [llvm-config] Use WithColor for printing errors. adds 304292110d0 [llc] Use WithColor for printing errors/warnings adds d417685a32a ADT: Use EBO to shrink SmallVector size 1 adds 7cde7d986ff [llc] Fix sanitizer failure. adds 4a7b6910075 [CMake] Support building shared library for OpenBSD adds bd075060f18 [CMake] Do not use --gc-sections on OpenBSD adds e57f6fb05fc Add OpenBSD support to the Threading code adds 009107f3d68 Also forward declare BitScanReverse. adds d153721e94b [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction [...] adds 8fe400a66e7 [X86] Regroup some isel patterns. NFC adds af1e6f153f0 [DAGCombiner] eliminate setcc bool math when input is low-b [...] adds ad8f413c533 [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mip [...] adds 37b9e499fc4 [X86] Reduce the number of patterns needed for masked scala [...] adds 7b76b3ec917 [X86] Remove the changes to combineScalarToVector made in r335037. adds fb9ef323663 [X86] Simplify some code by using isOneConstant. NFC adds 6aa7ab2443d [WebAssembly] Add WebAssemblyLateEHPrepare pass adds ad04e25e240 [WebAssembly] Add WebAssemblyException information analysis adds 19eaf65da0f Add a TaskQueue that can serialize work on a ThreadPool. adds aec098b9245 Fix CRLF line endings. adds 1d3a8f2bbbc Try to fix build error on non MSVC compilers. adds 761de657153 One more build fix for non MSVC compilers. adds 5804675605b [MSSA] Add domination number verifier; NFC adds 9625701b0d4 [X86] Block commuting operand 1 of FMA*_Int instructions in [...] adds 47c8e1d5eb0 [llvm-exegesis][NFC] Fix `Operand` class comments. adds c846c8b55ed Fix -Wparentheses gcc warning. NFCI. adds 534c5d4317e [llvm-exegesis][NFC] clang-format adds 4e7cfd69f5c Use APInt[] bit access to avoid "32-bit shift implicitly co [...] adds 512d410a6b9 [llvm-exegesis][NFC] Simplify BenchmarkRunner ctor. adds a2181998a78 Use APInt[] bit access to avoid "32-bit shift implicitly co [...] adds a8f90c09916 Revert change 335091. adds 647fa5f2e68 Revert change 335077 "[InlineSpiller] Fix a crash due to la [...] adds 15fac97085c [llvm-exegesis] Generate snippet setup code. adds 4025e96cad4 [llvm-exegesis] Fix warning in r22752: Initialize IsSnippet [...] adds 0c43400bbd5 [IR] avoid -Wdocumentation spew about HTML tags adds 14a520d8321 [llvm-exegesis][NFC] Remove unnecessary member variables. adds ce1c8d90ff4 Improve handling of COPY instructions with identical value numbers adds c39bf69d806 SafepointIRVerifier should ignore dead blocks and dead edges adds d3d2228f8c6 AMDGPU: Respect align argument parameter adds 084d7ce7aa7 [DA] Delinearise AddRecs if we can prove they don't wrap adds ba791754878 [SampleFDO] Add an option to turn on/off warning about samp [...] adds c4c340a047c AMDGPU/GlobalISel: Fix G_IMPLICIT_DEF for pointers adds b34fc164bd8 AMDGPU: Remove commented out code adds a26c784064a StackSlotColoring: Decide colors per stack ID adds 529b26551c9 AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr adds e8508360bc0 Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFC adds d8c387b1dd3 [llvm-mca] Rename Backend to Pipeline. NFC. adds f1fc2a32d73 [SelectionDAG] Remove debug locations from ConstantSD(FP)Nodes adds 5ae690aaab8 [X86] Allow base and index for gather instructions to appea [...] adds 3dbf0c9ce7f [X86] Sort the static memory folding tables by reg opcode. [...] adds 6ff63714d1c [GISel]: Update the end of GISel Opcode namespace. adds 88313d288df [InstCombine] add tests for add-of-sext-bool; NFC adds 2d21bce8d98 Re-land r335297 "[X86] Implement more of x86-64 large and m [...] adds e51396c3aeb [InstSimplify] add tests for div/rem with bool divisor; NFC adds 993ef0ca960 Handle NetBSD specific path in findDebugBinary() adds df0d594dd00 [InstSimplify] fold div/rem of zexted bool adds c1803abd1bb [SCEVExp] Advance found insertion point until we find a non [...] adds d8832d436ca [PowerPC] Fix incorrectly encoded wait instruction adds 5223dab9bee [docs] Update doc after split of -gen-intrinsic in r335407 adds 8a3f60e9851 [X86] Add comment about the sorting of the memory folding t [...] adds c5dd80a9d0e [X86] Simplify intrinsic table binary search to not require [...] adds a972a2e1ff7 Force vector width for scev-expander-debug.ll test adds 92a88d2ee38 [LoopIdiomRecognize] Fix a couple places where it appears w [...] adds 26ac94ddde4 Revert r335513: [SCEVExp] Advance found insertion point adds fad81756be0 UBSan blacklist workaround for bot timeouts adds b191d76053e [InstCombine] add tests for sdiv with sext bool divisor; NFC adds 9aa6823d820 [InstCombine] fold sdiv with sext bool divisor adds 5c3069979f1 [Instrumentation] Remove unused include adds aff0591efb5 [InstCombine] add/move tests for udiv; NFC adds d3b9487abb7 [InstCombine] cleanup udiv folds; NFCI adds 6eef3c63b25 Fix unsigned/signed comparison failure in unittest. adds cde39cece92 [OrcMCJIT] Fix test after r335508 causing it to fail on gre [...] adds 560c9c479f7 [X86] Update fpclass intrinsic tests to chain their calls t [...] adds 224904bf2c5 [PM/LoopUnswitch] Teach the new unswitch to handle nontrivi [...] adds 649e247b1c5 [gdb] Add pretty printer for Expected adds 5e785b9abda [APInt] Add helpers for rounding u/sdivs. adds 39add80ac56 Add a warning if someone attempts to add extra section flag [...] adds 4c45b898f09 [ThinLTO] Compute GUID directly from GV when building per-m [...] adds d411816d5c3 [gdb] Escape unprintable bytes in SmallString and StringRef adds 60f122c15f7 foo adds 0b6ddca1f37 [X86] Redefine avx512 packed fpclass intrinsics to return a [...] adds 7ca1126ca83 [ORC] Add a symbolAliases function to the Core APIs. adds 00cc8d0f099 Revert r335562 and 335563 "[X86] Redefine avx512 packed fpc [...] adds 633b851c9ab [ThinLTO] Add per-module indexes to combined index consistently adds d1d8627cf4c [X86] Redefine avx512 packed fpclass intrinsics to return a [...] adds 1cc13e5ad13 [ThinLTO] Add string saver onto index for value names adds 0135f2ae728 [WebAssembly] Fix a typo in a comment. adds 682da16f995 [X86] Use XOR for SUB (C, X) during isel if will help fold [...] adds 2da9f1a84d0 [WebAssembly] Fix lowering of varargs functions with non-le [...] adds 02ed557da0c [X86] Don't use getScalarShiftAmountTy to get the immediate [...] adds d7d68723b85 [InstCombine] (A + 1) + (B ^ -1) --> A - B adds 2079dc34cb0 Improve ConvertDebugDeclareToDebugValue adds 32a7d0f17dd [NFC] Prefer (void) to LLVM_ATTRIBUTE_UNUSED for unused var [...] adds d6bc0c7274d [llvm-exegesis] Get the BenchmarkRunner from the ExegesisTarget. adds 713ebb15587 Fix MSVC "not all control paths return a value" warnings. NFCI. adds 94a670b38e5 [AArch64] Clean up LSE directive tests adds 179cff63927 [AArch64] Tighten up directives tests adds be2419a2acf Fix MSVC "signed/unsigned mismatch" warning. NFCI. adds 1766212247a [IPSCCP] Change dead blocks to unreachable after visiting a [...] adds 2f2d460c914 [llvm-mca] Remove unused header files and correctly guard s [...] adds 823657d43f9 [X86] Just use ArrayRef instead of SmallVectorImpl in a few [...] adds a34afb03345 [llvm-exegesis][NFC] Fix windows warning in rL335465. adds cf4a1ccdffc [llvm-mca] Removed wrong NDEBUG guards introduced by my las [...] adds 43f589a4df3 ARM: diagnose unpredictable IT instructions adds a32cfd263d6 ARM: correctly decode VFP instructions following unpredicta [...] adds 67ad29ab383 ARM: add binary file git swallowed. adds 86366d2a15d [InstCombine] fold udiv with sext bool divisor adds c6dda905a6c [ThinLTO] Parse module summary index from assembly adds 799df9565bf Fix spelling mistakes in comments. NFCI. adds 61f67f4637f [X86,ARM] Retain split-stack prolog check for sibling calls adds f2d90857daf [TargetLowering] isVectorClearMaskLegal - use ArrayRef<int> [...] adds 2c45bcb3993 Account for undef values from predecessors in extendSegmentsToUses adds 7b36ec6b5e1 Fix LLVM_ENABLE_THREADS=0 builds after r335440. adds a301ecd20b0 [InstSimplify] add tests for srem with sext bool divisor; NFC adds e873939bd3e Silence "unused variable" warning in LiveIntervals.cpp afte [...] adds 583ccd4384c [FileCheck] Add CHECK-EMPTY directive for checking for blank lines adds 3e90a9b8c8a Fix doc title underlining. adds 7706083ace4 [InstSimplify] fold srem with sext bool divisor adds 007404388ee [DAGCombiner] Pull out VT bitwidth in visitSDIV. NFCI. adds 0c1dedd8edc [InstCombine] add tests for urem with sext bool divisor; NFC adds 40be0055aea [SLPVectorizer] Recognise non uniform power of 2 constants adds e9e5731866d [InstCombine] fold urem with sext bool divisor adds 41f2034b16d [InstCombine] simplify code for urem fold; NFCI adds 5399eba9f5d [X86][SSE] Add another sdiv by (nonuniform) minus one test [...] adds 84f6f2281a5 [InstSimplify] add tests for shifts by sext bool; NFC adds 5f8dac19296 [InstSimplify] fold shifts by sext bool adds 0fde67787aa Move `REQUIRES:` line to the top adds 67cc73d7b24 [DAGCombiner] Don't accept -1 sdiv divisors in sdiv-by-pow2 [...] adds 6b3e4d2fb7a [Hexagon] Add a "generic" cpu adds 6a78ba2a8c2 [Local] Sink salvageDI's early exit into helper functions, NFC adds 99917384c89 [Local] Add a convenient insertReplacementDbgValues overload, NFC adds 93ae5a35afc LoopUnroll: Allow analyzing intrinsic call costs adds e64a8288ae1 [ConstantRange] Add support of mul in makeGuaranteedNoWrapRegion. adds 9253369f66e [Debugify] Don't treat missing dbg.values as an error (PR37942) adds 8d224a36c1c Use a variable to appease a no-asserts bot, NFC adds 737191dd296 ConstantFold: Don't fold global address vs. null for addrsp [...] adds a2ba13d7317 AMDGPU: Add pass to lower kernel arguments to loads adds 95b187a7ddf [DAGCombiner] use isBitwiseNot to simplify code; NFC adds aac117a9ba2 [AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic adds 34ffe04f30e [X86][AsmParser] Emit an error when RIP-relative instructio [...] adds daa6db3e25b Revert "[X86][AsmParser] Emit an error when RIP-relative in [...] adds fdc08234d7e [ORC] Fix a FIXME by moving MangleAndInterner to Core.h. adds 2338ba3e110 [ORC] Add a FIXME. adds 6ccd1b1e5be [ORC] Move the VSOList typedef out of VSO. adds b525a3a6390 [ORC] Reset AsynchronousSymbolQuery's NotifySymbolsResolved [...] adds 89e0af6b105 [ORC] Allow IRTransformLayer2's transform to be modified af [...] adds ab0a33b6a77 Rename skipDebugInfo -> skipDebugIntrinsics, NFC adds 9e1483fe741 [X86][AsmParser] Recommit r335658 adds 784d2a84999 AMDGPU: Silence unused warnings in waitcnt insertion pass i [...] adds 9f1c2395ce1 [ORC] Add LLJIT and LLLazyJIT, and replace OrcLazyJIT in LL [...] adds 0e00ed71fae [X86] Add test for SDIV by sign bit (minsigned) value adds ab8689e932e [ORC] Add a dependence on MC to LLVMBuild.txt adds d3c8f20a14b [JumpThreading] Don't try to rewrite a use if it's already valid. adds 1d0cbe2918c [ORC] Fix a missing return value. adds 1b30e51a073 [ORC] Don't call isa<> on a null value. adds 0ed99e80c71 Revert "[asan] Instrument comdat globals on COFF targets" adds acc979319bb [Debugify] Diagnose mis-sized dbg.values adds 06f46b29d52 [X86] Don't store register and memory FMA3 opcodes in the s [...] adds 3dbfeaffe7a [Debugify] Handle failure to get fragment size when checkin [...] adds bde65c4dd97 [InstCombine] Avoid creating mis-sized dbg.values in common [...] adds 0f220def93e [llvm-mca] Add a comment to Stage::execute and fix a spelli [...] adds 2051d2558e7 [ADT] Pass DerivedT from pointe{e,r}_iterator to iterator_a [...] adds c2fa8e709e9 [CMake] Use variables rather than ":" delimiters adds 70b7a2fd32c [CMake] Provide direct support for building sanitized runtimes adds 78d083b50fd AMDHSA/NFC: Address missed review feedback from https://rev [...] adds 80681820212 AMDHSA: Rename RESERVED -> RESERVED0, mark gfx9-specific field adds fe1e7736763 AMDGPU/NFC: Fix typo in comment adds 4187c135cfd [AArch64] Remove Duplicate FP16 Patterns with same encoding [...] adds 3a09592b608 Removing empty CodeGen dir in root adds 1f74921dd71 [DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by [...] adds 988e5b9752d [DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN [...] adds 8a57afce61d [DAGCombiner] visitSDIV - simplify pow2 handling. NFCI. adds a62a0a38355 [X86][SSE] Include MIN_SIGNED element in non-uniform SDIV p [...] adds 0093dbb5fc2 [llvm-mca] Avoid calling method update() on instructions th [...] adds 823c169bec7 Build TaskQueueTest in threads=on builds, fixes regression [...] adds 16742ac8e4b [DAGCombiner] visitSDIV - add special case handling for (sd [...] adds a0883e04578 [ValueLattice] Return false if value range did not change i [...] adds 212054e1a97 [NEON] Support vldNq intrinsics in AArch32 (LLVM part) adds 751c17bfa03 [AArch64] Add custom lowering for v4i8 trunc store adds b5a170b9c2e [AArch64] Reverting FP16 vcvth_n_s64_f16 to fix adds bc547571e75 [AMDGPU] Convert rcp to rcp_iflag adds 480d03dbeb9 [X86] Rename the autoupgraded of packed fp compare and fpcl [...] adds 966cfbb5c29 [X86][SSE] Add missing AVX512 rotation tests adds 90b999fed8f [llvm-mca] Register listeners with stages; remove Pipeline [...] adds 928fea20d30 [dsymutil] Move abstractions into separate files (NFC) adds bdacec9c4a9 [AliasSet] Fix UnknownInstructions printing adds aa5b675322e [X86] Add test cases for D48606. adds 52753df4e21 [X86] Use bts/btr/btc for single bit set/clear/complement o [...] adds c86651469ca [InstCombine] add more tests for shuffle with different bin [...] adds 43d4585d619 [MachineOutliner] Don't outline sequences where x16/x17/nzc [...] adds f602599e6b3 [Object] Allow iterating over an IRObjectFile's modules adds 752939e86ab [ThinLTO] Print names in function import debug messages whe [...] adds 3d6697fe50b [DAGCombiner] restrict (float)((int) f) --> ftrunc with no- [...] adds 4b6501ab453 [ThinLTO] Modify test to help diagnose bot failures adds a75001c8dbd [ThinLTO] Fix test adds 576283c1191 [globalisel][legalizer] Add AtomicOrdering to LegalityQuery [...] adds 65fb103bddb [X86] Teach the disassembler to use %eiz/%riz instead of No [...] adds df04b22195f [X86] Fix unmatched parenthesis in r335768 adds d7295192d1a [WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll adds 857aa39725c [ADT] drop_begin: use adl_begin/adl_end. NFC. adds f162464ba81 [DAGCombine] Disable TokenFactor simplifications when optnone. adds 4fc1c001a75 Document the git config for Windows to do line-endings correctly. adds 45f68e6a2eb [InstCombine] add tests for vector-select-of-binops with 2 [...] adds 84e5dbffd78 [llvm-objdump] Add -x --all-headers options adds 78e3c70281b [RISCV] Add machine function pass to merge base + offset adds 9f60a34c354 [X86] In X86DAGToDAGISel::PreprocessISelDAG, make sure we d [...] adds 4b0e4cbeb2f [X86] Make folding table checking threadsafe adds 6a89efb6b2d Move some code from PDBFileBuilder to MSFBuilder. adds 71b21d8fccb Add support for generating a call graph profile from Branch [...] adds 09b856ac453 [CGProfile] Fix unused variable warning. adds 5dc174cf3bf [cmake][xcode-toolchain] add support for major Xcode version >= 10 adds 7e0591f5b86 [X86] Change how we prefer shift by immediate over folding [...] adds f5d15403005 [X86] Use PatFrag with hardcoded numbers for FROUND_NO_EXC/ [...] adds d9df72a18eb Support for multiarch runtimes layout adds e1714df0ef0 [DwarfDebug] Remove unused argument (NFC) adds ff524783991 [llvm-exegesis] Add partial X87 support. adds 3eb8221ad97 [IndVarSimplify] Ignore unreachable users of truncs adds 5016671ee05 [DAGCombiner] Remove unused variable. NFCI. adds e6a8acefb8f [SCCP] Mark CFG as preserved. adds 5796a8d8718 [DAGCombiner] Ensure we use the correct CC result type in v [...] adds d241bc3accb Unify sorted asserts to use the existing atomic pattern adds 5f4316253c2 AMDGPU: Fix assert on aggregate type kernel arguments adds 2f8e5b3099f AMDGPU: Fix AMDGPUCodeGenPrepare using uninitialized AMDGPU [...] adds fe32d1437e3 AMDGPU: Error on calls from graphics shaders adds 90f8cc80db5 AMDGPU: Remove MFI::ABIArgOffset adds 8f542571d7b s/TablesChecked/TableChecked/ after r335823 adds 9d41c557cbe Comment change to verify commit rights. NFC. adds 5652271db1a [llvm-mca] Refactor method RegisterFile::collectWrites(). NFCI adds d5b753a85d9 ADT: Move ArrayRef comparison operators into the class adds 3d172cd8f95 Revert "ADT: Move ArrayRef comparison operators into the class" adds ee2becd7045 [ARM] Parallel DSP Pass adds 1bbef2cc89f Revert "Add support for generating a call graph profile fro [...] adds 106ffb91691 Add a PhiValuesAnalysis pass to calculate the underlying va [...] adds ea63d873c8a [dsymutil] Use UnitListTy consistently (NFC) adds 6859f8aaa97 [DEBUG_INFO, NVPTX] Add test for .debug_loc section, NFC. adds 97e3954d2a0 [PhiValues] Adjust unit test to invalidate instructions bef [...] adds 8746f255cda [AMDGPU] Overload llvm.amdgcn.fmad.ftz to support f16 adds a2237ff0e5a [llvm-mca] Use a WriteRef to describe register writes in cl [...] adds 0e7f42b6394 [AMDGPU] Early expansion of 32 bit udiv/urem adds 4f08eb3e6db [llvm-mca][x86] Add 3dnow! resource tests adds 8e2dac622af [llvm-mca][x86] Add FMA4 resource tests adds 5ed53954fb6 Revert "[DAGCombiner] Ensure we use the correct CC result t [...] adds bd0a2a58e5b [MachineOutliner] Add always and never options to -enable-m [...] adds 294ff667fed SelectionDAGBuilder, mach-o: Skip trap after noreturn call [...] adds 9c7c10e4073 [MachineOutliner] Never add the outliner in -O0 adds be2cdf90a35 Revert "[MachineOutliner] Never add the outliner in -O0" adds 9bc4099b799 Revert "[MachineOutliner] Add always and never options to - [...] adds abd5dd61fc9 [WebAssembly] Add getSetCCResultType placeholder override t [...] adds 39d2c2868cb [llvm-mca] Delete Pipeline's copy ctor and assignement operator. adds 93aa3932e77 [DAGCombiner] Ensure we use the correct CC result type in v [...] adds d6b8d8c07b4 [MachineOutliner] Define MachineOutliner support in TargetOptions adds 25be6bdd6fc [InstCombine] allow shl+mul combos with shuffle (select) fo [...] adds e7de33fcf27 Set line ending style of llvm.natvis to CRLF. adds a924a78e8a4 2 VS natvis improvements. adds 3e2aa5b2f64 Revert "[OrcMCJIT] Fix test after r335508 causing it to fai [...] adds 3695b5379bf Revert "Re-land r335297 "[X86] Implement more of x86-64 lar [...] adds b2408daddbd [X86] Suppress load folding into and/or/xor if it will prev [...] adds 3d7cc9ef304 [Debugify] Do not report line 0 locations as errors adds a71c03687f3 [CMake] Respect CMAKE_STRIP and CMAKE_DSYMUTIL on apple platforms adds be8c3633e05 Remove unnecessary semicolon. NFCI. adds 822461008d3 Add a flag to FileOutputBuffer that allows modification. adds 3605e121fbd Handle absolute symbols as branch targets in disassembly. adds fbc17042e9c [SROA] Preserve DebugLoc when rewriting alloca partitions adds 7540b28963a Some targets don't have lld built, so just use a binary cop [...] adds 8f59c35cfad [ARM] Add missing Thumb2 assembler diagnostics. adds f104e589ce8 [NVPTX] Delete dead code adds 1dc0b96afda [ThinLTO] Port InlinerFunctionImportStats handling to new PM adds c8bdc2e0339 Fix padding with custom character in formatv. adds d628d72dc94 [COFF] Fix constant sharing regression for MinGW adds 83bc27f0aaa [InstCombine] fix opcode check in shuffle fold adds 540a311718e [SupportTests] Silence -Wsign-compare warnings adds eefdbb43aab [llvm-readobj] Add experimental support for SHT_RELR sections adds 87b704f790d [InstCombine] adjust shuffle tests; NFC adds 519acca3343 [MachineOutliner] Never add the outliner in -O0 adds 5ff4fbf6b8b [ARM] Assert that ARMDAGToDAGISel creates valid UBFX/SBFX nodes. adds c1d6c4ab99f Require x86 for this test. adds cba2181e776 AMDGPU: Separate R600 and GCN TableGen files adds a233e5b07ac [X86] Remove masking from the avx512 packed sqrt intrinsics [...] adds 4d942d9e7ec Make email options of find_interesting_reviews more flexible. adds 998f8604339 SCEVExpander::expandAddRecExprLiterally(): check before cas [...] adds 663484452ec [ARM][AArch64] Armv8.4-A Enablement adds ab4b844b3e6 [X86][SSE] Support v16i8/v32i8 vector rotations adds 886c551da5c [cmake] Change WIN32 test to CMAKE_HOST_WIN32 adds 548039bed15 [AArch64] Armv8.4-A: Virtualization system registers adds ecdc1aafd0c Fix overconfident assert in ScalarEvolution::isImpliedViaMe [...] adds ce6e09c7405 [InstCombine] enhance shuffle-of-binops to allow different [...] adds 3b81d99e576 [Hexagon] Remove unused instruction itineraties, NFC adds 6882f03fec6 [DEBUG_INFO, NVPTX] Do not emit .debug_loc section. adds 4e9529bf924 [llvm-mca] Remove field HasReadAdvanceEntries from class Re [...] adds 6e44255b70d [InstCombine] add more tests for shuffle-binop folds; NFC adds d1bf1e83362 [MachineOutliner] Add always and never options to -enable-m [...] adds 0e1a98e2552 [AMDGPU] Enable LICM in the BE pipeline adds ada03192b6d [mips] Support shrink-wrapping adds 4d3e6c13b68 [dsymutil] Introduce a new CachedBinaryHolder adds 9f33bbfea84 [dsymutil] Make the CachedBinaryHolder the default adds 03cec5cbaf0 [X86] Use a std::vector for the memory unfolding table. adds d36457d104a [dsymutil] Rename conflicting declaration adds 8b6f52ae8e8 Extend CFGPrinter and CallPrinter with Heat Colors adds bb9abb7e0d9 [X86] Limit the number of target specific nodes emitted in [...] adds eac8acfa949 AMDGPU: Don't use struct type for argument layout adds 551913f7e3a Revert "Extend CFGPrinter and CallPrinter with Heat Colors" adds 459351c7056 Pass DWARFUnit to verifier by reference not by value. I am [...] adds c55ef4741ac [LLVMContext] Detecting leaked instructions with metadata adds 1c3bbb46642 [HWASan] Do not retag allocas before return from the function. adds d1ed9d650dd [MemorySSA] Add APIs to MemoryPhis to delete incoming block [...] adds d2312611412 [WebAssembly] Comment out a switch block in ISelDAGToDAG adds a70dcefd9a5 [WebAssembly] Update comments for non-splat pow2 vector test case adds 7ce035b5346 [CodeView] Correctly compute the name of S_PROCREF symbols. adds b2b950d7b11 [instsimplify] Move the instsimplify pass to use more obvio [...] adds 8c0bb2f0365 [X86] Remove masking from avx512 rotate intrinsics. Use sel [...] adds c549767db5a [MachineOutliner] Add support for target-default outlining. adds 8eb696d509e AMDGPU/GlobalISel: Make IMPLICIT_DEF of all sizes < 512 legal. adds 1242dda03b7 [X86] Remove test cases from avx512vl-intrinsics-fast-isel. [...] adds 81f95d68a1f [X86] Change some chec-prefixes from X32 to X86 to match th [...] adds 6451a6d6f65 [X86] Update some avx512 fast-isel tests to match their rea [...] adds 985808d7ef5 [DAGCombiner] Handle correctly non-splat power of 2 -1 divi [...] adds 59222a5ca60 Fix Wdocumentation compiler warning. NFCI. adds 4d00d7aadb6 [InstCombine] add tests for negate vector with undef elts; NFC adds 04292f96693 [X86] When combining load to BZHI, make sure we create the [...] adds bfb044eaa54 [X86] Use MVT::i8 for scalar shift amounts since that is wh [...] adds 8dc6c5c5dae [X86] Remove the AsmName from the HAX,HDX,HCX,HBX,HSI,HDI,H [...] adds 16815e99bba [X86] Move the X86InstrFMA3Info class into the cpp file. Ex [...] adds ed5068fcf14 [X86] Move the memory unfolding table creation into its own [...] adds bae31892274 [X86] Remove unnecessary include. NFC adds 0de2000b2d0 [llvm-readobj] Fix printing format adds eaabebdbe00 [Evaluator] Improve evaluation of call instruction adds 243c2fa15c2 [SLPVectorizer][X86] Add some alternate tests for cast operators adds 2d07720488b Revert "[llvm-readobj] Fix printing format" adds e101271f213 [UnrollAndJam] New Unroll and Jam pass adds 4c7a6ba2a43 [SLPVectorizer] Use InstructionsState Op/Alt opcodes direct [...] adds 6fed3d80700 [PatternMatch] allow undef elements in vectors with m_Neg adds 77442a72e04 [InstCombine] add abs tests with undef elts; NFC adds 23d1e8ab600 [X86][Disassembler] Remove TYPE_BNDR from translateImmediate. adds b1dbeaa9ce7 [SLPVectorizer] Replace sameOpcodeOrAlt with InstructionsSt [...] adds a634a07771b [SLPVectorizer] Call InstructionsState.isOpcodeOrAlt with I [...] adds a7fba40f43e [X86] Remove the places that return nullptr from X86InstrIn [...] adds 260d013aef7 [X86] Fix a few test names in avx512-intrinsics-fast-isel.l [...] adds 49451db6ac0 Add an entry for rodata constant merge sections to the defa [...] adds c2f24d9ea87 Implement strip.invariant.group adds 38051ae89ad [PowerPC] Don't make it as pre-inc candidate if displacemen [...] adds ef235be85a9 [X86] Remove FMA3Info DenseMap. Break into sorted tables th [...] adds 33274bcdebb [llvm-exegesis][NFC] Cleanup useless braces. adds 25c9ed7633b [X86] Put some cases in switch statements back on one line [...] adds e52381764a9 [NFC] Test that shows unprofitability of instcombine with b [...] adds 529d7338b8c Reapply r334980 and r334983. adds 16f18201f6c [AArch64][SVE] Asm: Support for vector element compares (im [...] adds 783ea2aeedd [Mips][FastISel] Do not duplicate condition while lowering [...] adds f71bd1f42bb [X86][BtVer2] Added Jaguar FPU Pipe0/1 uop counters to perm [...] adds fe476f5b59e [AArch64][SVE] Asm: Support for (saturating) vector INC/DEC [...] adds 868f51c186b [AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) adds a43dcd4394d [SLPVectorizer] Only Alternate opcodes use ShuffleVector ca [...] adds 386f15c93a2 [SLPVectorizer] Fix alternate opcode + shuffle cost functio [...] adds d9fdb860571 [InstCombine] add tests for shuffle-binop; NFC adds 2a87571b088 Recommit r328307: [IPSCCP] Use constant range information f [...] adds 3fc11a82d18 [llvm-exegesis] Delegate the decision of cycle counter name [...] adds 18de41c4564 [X86] Use addAliasForDirective to support the .word directive adds 736ca3f1beb [InstCombine] adjust shuffle tests with IR flags; NFC adds a40b37f909c [SLPVectorizer] Remove nullptr early-outs from Instruction: [...] adds f1f3f984f72 Revert r336100 adds eca25385a80 [X86] Use addAliasForDirective to support the .word directi [...] adds 752e14ccebb [llvm-exegesis] Change how the native architecture is determined adds bf14300d4c6 [X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104 adds f123cb818a1 [CodeGen] Make block removal order deterministic in CodeGenPrepare adds 6b77c4bc5ff Disable failing test on x86_64-pc-windows-gnu, see PR38006. adds cdbffdd9b54 [ValueTracking] allow undef elements when matching vector abs adds 3e5a75b28df [X86][SSE] Add v8i16 shift test for 2 shift values that doe [...] adds 273949e71bf [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values adds bf4ec2b466c [Dominators] Add the DomTreeUpdater class adds f56a57c59e9 Follow up of r335953 - [ARM][AArch64] Armv8.4-A Enablement adds 20c17e173fa [WebAssembly] Convert remaining tests from elf to wasm outp [...] adds 6e76b4eeb53 Revert "[Dominators] Add the DomTreeUpdater class" adds 636e853b421 [AArch64][GlobalISel] Any-extend vararg parameters to stack [...] adds e5e07035165 [X86] Don't use aligned load/store instructions for fp128 i [...] adds 15962f647bd [CostModel][X86] Add cost tests for fp rounding intrinsics adds eb37a3e6fa5 Tighten up a test for -check-debugify, NFC adds 198bcb65d99 [SLPVectorizer][X86] Begin adding alternate tests for call [...] adds 629c9d30eb3 nm: Add -no-weak flag for hiding weak symbols adds a5d70d8749b [MC] Error on a .zerofill directive in a non-virtual section adds c9a157f7fd5 [InstCombine] reverse canonicalization of add --> or to all [...] adds 13f7859c206 [SLP] Recognize min/max pattern using instructions producin [...] adds 4cc22bda677 Replace unused output filenames with /dev/null in tests adds 89e8753d7bf Replace "Replacable" with "Replaceable". [NFC] adds 1c305da5144 [X86] Add phony registers for high halves of regs with low halves adds df015f19fc7 [WebAssembly] Fix fast-isel optimization of branch conditions. adds 7276550b78a [SCEV] Strengthen StrengthenNoWrapFlags (reapply r334428). adds 8636bd77426 [llvm-mca] Clear the content of map VariantDescriptors in I [...] adds 2546414701c [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m. adds bb8c53976bc [WebAssembly] Support for atomic stores adds 807ab9588cf [ThinLTO] Fix printing of module paths for distributed back [...] adds d7b828144f2 [ORC] Verify modules when running LLLazyJIT in LLI, and dea [...] adds 1a01e8944b7 Remove absolute path in test adds d0f9eaced9b [ADT] Add llvm::unique_function which is like std::function [...] adds 22e1f605703 [demangler] Fix a MSVC alignment warning. adds 3369ac0dd8c Some buildbots were choking on std::max_align_t, try using [...] adds 3aca69ca829 [ThinLTO] Fix printing of aliases for distributed backend indexes adds 52b38c4e9f9 [Support] Fix llvm::unique_function when building with GCC [...] adds 7b549ea6b60 Revert r336159, r336157. Some bots failed on qualified std: [...] adds 57fa5c9397b Reappl "[Dominators] Add the DomTreeUpdater class" adds 4bf5c9984c2 [ADT] Switch another place to `llvm::is_trivially_move_cons [...] adds 2ef7a1ca8c0 [X86] Add avx512vl command line to break-false-dep.ll adds aabbcb39787 [ADT] Try to work around a crash in MSVC. adds c978388e74b [llvm-exegesis] ExegisX86Target::setRegToConstant() should [...] adds 6ac04e25a3a [InstCombine] Delay foldICmpUsingKnownBits until simple tra [...] adds 344a827483e [Support] This sanity check in the test only works with cer [...] adds a9de7e5e9c7 [DebugInfo] Fix PR37395. adds 939e4c5a9cf [ADT] Disable the single callback optimization on Windows. adds 099ee454a70 [AArch64][SVE] Asm: Support for vector element FP compare. adds ba89ffcade7 [PM/LoopUnswitch] Fix PR37651 by correctly invalidating SCE [...] adds c95c8c872bc [MIPS GlobalISel] Lower arguments using stack adds 3095ea4ec7e [AArch64][SVE] Asm: Support for saturing ADD/SUB instructions. adds a5c6980ab7a [llvm-exegesis] Add an AArch64 target adds ed0d4dabbee [llvm-exegesis] Adjust AArch64 unit test adds d5d94ca3a7f Revert "[X86][SSE] Blend any v8i16/v4i32 shift with 2 shift [...] adds 13e9d31258a [DebugInfo] Corrections for salvageDebugInfo adds cfc7aea7ef8 build_llvm_package.bat: Re-try the build steps adds 5af2ac74a54 [AArch64] Armv8.4-A: system registers adds a1ff84e2e4e [IR] Strip trailing whitespace. NFC adds 26122d06c8b [ARM][NFC] Refactor sequential access for DSP adds c810b4e17d7 [InstCombine] fold shuffle-with-binop and common value adds 6a79620306e [DAGCombiner] visitSDIV - Permit MIN_SIGNED_VALUE in pow2 v [...] adds 4962aeccc93 [AArch64][SVE] Asm: Support for predicated unary operations. adds c0606b67ed2 [AArch64][SVE] Asm: Support for FMUL (indexed) adds a9961f34ed2 Rename lazy initialization functions to reflect behavior (NFC) adds 85678535ba7 [Reassociate] add test for missing FP constant analysis; NFC adds ebcc0927e37 [AArch64][GlobalISel] Fix fallbacks introduced in r336120 d [...] adds a06d966cffd [AArch64][SVE] Asm: Support for FP Complex ADD/MLA. adds ed7df98414e [Reassociate] regenerate checks; NFC adds ef3144ea385 [Reassociate] add tests for binop with identity constant; NFC adds d841b7b37d2 [Constants] add identity constants for fadd/fmul adds f438ac9e92f Fix typo in lib/Support/Path.cpp to test commit access adds 773b6e54313 [X86][AsmParser] Don't consider %eip as a valid register ou [...] adds f4212f0917f [X86][AsmParser] Rework the in/out (%dx) hack one more time. adds a5edfbd7f9a [InstCombine] add tests for shuffle+binop with constant op1; NFC adds 92dfb6e3244 [AArch64] Make function parameter names in declarations mat [...] adds e1d12229c21 [ARM] Fix inconsistent declaration parameter name in r336195 adds cfa89ea7f98 [X86] Add tests for low/high bit clearing with different at [...] adds dee3b3b081b [X86] Remove repeated 'the' from multiple comments that hav [...] adds 4bbb8b7d1f4 [NVPTX] Expand v2f16 INSERT_VECTOR_ELT adds 7ead4232dac [X86][AsmParser] Fix inconsistent declaration parameter nam [...] adds bdd6a09688e [lanai] Handle atomic load of i8 like regular load. adds 1eef495cdcc [Support] Remove SaveOr which is no longer used adds 2dfeba53c3d [ImplicitNullChecks] Check for rewrite of register used in [...] adds 71ab3ef1d76 [AArch64][SVE] Asm: Support for SVE condition code aliases adds 19a6aea02d4 [X86][SSE] Add reduced crash test case for r336113 - [X86][ [...] adds c8da7b28b97 [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique [...] adds baf68707d00 [DebugInfo][InstCombine] Preserve DI after combining zext adds fb31c6481f7 [DebugInfo][LoopVectorize] Preserve DL in generated phi ins [...] adds c7d6f7ca768 [NFC] Add test that shows that InstCombine can do better adds 3b4c054b7b9 [AArch64][SVE] Asm: Support for FP conversion instructions. adds d657fe7634b [llvm-exegesis] Remove dead comment. adds c8d61cbaa4c [AArch64][SVE] Asm: Support for instructions to set/read FFR. adds 0aae9148178 NFC - Various typo fixes in tests adds 6c03d59fdb6 [X86][SSE] Add SSE2 target to some shift tests adds 5a15e424fb4 [AArch64][SVE] Asm: Support for reversed subtract (SUBR) in [...] adds 645f3d0f000 [ThinLTO] Update ThinLTO cache file atimes when on Windows adds 4b43817e2b4 [X86][SSE] Add v16i16 shl x,c -> pmullw test adds d069a21e54f [llvm-objdump] Add --file-headers (-f) option adds 195a60c5f5f [MachineOutliner] Fix typo in getOutliningCandidateInfo fun [...] adds 851b4035374 [ARM] [Assembler] Support negative immediates: cover few mi [...] adds 6e5842a1e11 [InstCombine] add value names to test; NFC adds 79d7b5cd915 Fix some irregular whitespace/indentation. NFCI. adds 23aed9c64ab [X86][BtVer2][MCA][NFC] Add CMPEQ dependency-breaking one-i [...] adds b8f75399383 [InstCombine] allow narrowing of min/max/abs adds 96a3f3e4cdb [Dominators] Add DomTreeUpdater constructor from DT* and PDT* adds 1631efd1b8c [PowerPC] Replace the Post RA List Scheduler with the Machi [...] adds d04690c89ba [mips] Warn when crc, ginv, virt flags are used with too ol [...] adds 2dc5cd2beb8 Silence an MSVC C4189 warning about a local variable being [...] adds 4fcda06d85c [Power9]Legalize and emit code for round & convert quad-pre [...] adds 3d92cb5cddb [X86] Remove some of the packed FMA3 intrinsics since we no [...] adds 585ca3a7f51 [X86] Add support for combining FMSUB/FNMADD/FNMSUB ISD nod [...] adds 12fed3cda6e [X86] Remove some isel patterns for X86ISD::SELECTS that sp [...] adds b42f206bec4 [Power9] Implement float128 parameter passing and return values adds 1ae65deb249 [Power9]Legalize and emit code for quad-precision convert f [...] adds ddc48fa71f7 [Power9] Ensure float128 in non-homogenous aggregates are p [...] adds c7bc4c373ce [demangler] Avoid alignment warning adds d50e092736e [Power9] Add tests for passing float128 in VSX reg for non- [...] adds e5da5ca56a2 [Power9][NFC] add back-end tests for passing homogeneous fp [...] adds 5f1cfe90f3e [X86] Remove X86 specific scalar FMA intrinsics and upgrade [...] adds bd76e146be4 [Power9] Optimize codgen for conversions of int to float128 adds 0e87e9463a9 [AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD adds 802e5e3d9a8 [ARM] ParallelDSP: only support i16 loads for now adds 45a7a31f486 [AArch64][SVE] Asm: Support for predicated FP rounding inst [...] adds 53a066525e5 Partial revert of "NFC - Various typo fixes in tests" adds 797624f8264 Reverting r336322 for now, as it causes an assert failure i [...] adds e816e742162 [NEON] Fix combining of vldx_dup intrinsics with updating o [...] adds f9df18f4ce3 [mips] Fix atomic operations at O0, v3 adds a7eead2e395 Try to fix -Wimplicit-fallthrough warning. NFCI. adds 5ad902a628b [X86][SSE] Add extra v16i16 shl x,c -> pmullw test adds c13d59697a3 [TableGen] Increase the number of supported decoder fix-ups. adds 816b1d58d7b Partially revert r336268 in address-offsets.ll adds c7654d92173 [ADT] Switch to indirect even the trivial case through an o [...] adds e941c764421 [AMDGPU] Add VALU to V_INTERP Instructions adds 363d86f9595 [llvm-exegesis][NFC]clang-format adds 7029d5a52f0 [SLPVectorizer] Begin abstracting InstructionsState alterna [...] adds b06fd494977 [AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC adds ef431bb8ee8 Fix comment typo. NFCI. adds 1b3251f9f41 [llvm-exegesis] Add uop computation for more X87 instructio [...] adds fd46678873a [llvm-objdump] Add --archive-headers (-a) option adds a86a3c2c457 [X86][SSE] Add srem x, (1 << c) combine tests adds 37aa5135e52 [Power9] Add lib calls for float128 operations with no equi [...] adds 78a28ad3b83 [llvm-objcopy] Fix timezone dependant tests adds 92712655cf6 [llvm-mca] Fix RegisterFile debug prints. NFC adds 5ccd8badb18 [llvm-objdump] Removed archive-headers-disas test adds a46b1e54f3f [CostModel][X86] Add UDIV/UREM by pow2 costs adds e5d3d151346 AMDGPU/GlobalISel: Implement custom kernel arg lowering adds 5ad067fad46 AMDGPU: Don't use spir_kernel in a test adds 30ba76520af Fix asserts in AMDGCN fmed3 folding by handling more cases of NaN adds 6e0b82fc61c [X86] Add SHUF128 to target shuffle decoding. adds c9994c8acfb [X86] Remove the last of the 'x86.fma.' intrinsics and auto [...] adds d4298974bd1 Testing commit permision adds 318e807d171 [ORC] In CompileOnDemandLayer2, clone modules on to differe [...] adds c0500faed50 This is a recommit of r336322, previously reverted in r3363 [...] adds 1a979dc8f20 [ORC] Add BitReader/BitWriter to target_link_libraries adds 95e1a0c65c2 [WebAssembly] Add missing _S opcodes of atomic stores to In [...] adds bda51c282f6 Revert r332168: "Reapply "[PR16756] Use SSAUpdaterBulk in J [...] adds 8c4cc472e7a objdump: Support newer ObjC image info flags adds 861969844e0 [X86][Disassembler] Fix LOCK prefix disassembler support adds 39c82afe637 [OpenEmbedded] Add OpenEmbedded vendor adds d20537eca5c Revert "objdump: Support newer ObjC image info flags" adds 04d15315b2a [x86]Add a test case to show missed vfnmadd generation. adds 1ba3969024d [PDB] Sort globals symbols by name in GSI hash buckets. adds 0b9754cd9ab [Power9] Add __float128 library call for frem adds 7f08d4abd84 [llvm-pdbutil] Dump more info about globals. adds e12c938bca7 [X86] Cleanup some of the avx512 masked fma tests to prepar [...] adds 89a40a3e5c2 [X86] Remove all of the avx512 masked packed fma intrinsics [...] adds ed10960040a Revert "[InstCombine] Delay foldICmpUsingKnownBits until si [...] adds 145133c3486 Reapply: "objdump: Support newer ObjC image info flags" adds a2b35082b00 [Support] Make support types more easily printable. adds a4e191b3237 [X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic [...] adds fc2b3d0ed07 [AArch64][ARM] Armv8.4-A: Trace synchronization barrier ins [...] adds 2d76367f823 CallGraphSCCPass: iterate over all functions. adds 9e7cb445ca5 [llvm-mca] improve the instruction issue logic implemented [...] adds 6b3f49c77fb [AArch64] Armv8.4-A: Flag manipulation instructions adds 681dbd52d12 Revert [AArch64] Armv8.4-A: Flag manipulation instructions adds eaaa4f4cfc8 [SelectionDAG] https://reviews.llvm.org/D48278 adds 4ebe5514a93 Added missing semicolon adds d1a03350b87 Recommit: [AArch64] Armv8.4-A: Flag manipulation instructions adds 55b2eb047f3 [dsymutil] Emit label at the begin of a CU adds 023b04f4507 [AArch64] Armv8.4-A: TLB support adds 2d706a67e35 [llvm-mca] A write latency cannot be a negative value. NFC adds c988f9e6c39 [LoopSink] Make the enforcement of determinism deterministic. adds ef8af9b997f Commit rL336426 cause buildbot failures adds f36b7500f84 [ARM] ParallelDSP: added statistics, NFC. adds 58b0c3857a1 [Constant] add undef element query for vector constants; NFC adds 79da1642b15 [Constants] extend getBinOpIdentity(); NFC adds 3f928c753ce AMDGPU: Fix UBSan error caused by r335942 adds 735ebc0759b [InstCombine] add more tests with poison and undef; NFC adds 0f83e1fc484 [Local] replaceAllDbgUsesWith: Update debug values before RAUW adds d3643492a56 [Debugify] Allow unsigned values narrower than their variables adds 5b4b9a07e87 Revert 336426 (and follow-ups 428, 440), it very likely cau [...] adds f72707ee11c [InstCombine] add more tests for potentially poisonous shifts; NFC adds 80e7ea0a47d [llvm-objcopy] Add support for static libraries adds 73b3f8bb2de [llvm-mca] Add HardwareUnit and Context classes. adds ce6569598e1 [X86] Add more FMA3 memory folding patterns. Remove pattern [...] adds 9159fc2036d [X86] Remove patterns for MOVLPD/MOVLPS nodes with integer types. adds cfc86d49874 [IR] Fix inconsistent declaration parameter name adds c2801b16401 Use Type::isIntOrPtrTy where possible, NFC adds c779b36d254 [PDB] One more fix for hasing GSI records. adds 21926ea0e19 Remove a redundant null-check in DIExpression::prepend, NFC adds ca9c12e96d9 Fix DIExpression::ExprOperand::appendToVector adds ec4a235223d [PDB] memicmp only exists on Windows, use StringRef::compar [...] adds 962a2856aa4 Revert "[SCEV] Strengthen StrengthenNoWrapFlags (reapply r3 [...] adds 8c87300f879 [X86] Merge INTR_TYPE_3OP_RM with INTR_TYPE_3OP. Remove unu [...] adds 4498596c195 [PM/LoopUnswitch] Fix PR37889, producing the correct loop n [...] adds 5fd5dc8e41a [Support] Clear errno before calling the function in RetryA [...] adds 4af4a557bf5 [MachineOutliner] Assert that Liveness tracking is accurate (NFC) adds 7d301039274 [MachineOutliner] Add missing liveness tracking info in MIR test. adds df921c67472 NFC - Typo fixes in X86 flags-copy-lowering.mir test adds 50f103a27d1 Test commit adds b68da8c2ed3 [CostModel][X86] Add SREM/UREM general and constant costs ( [...] adds 7671355ab9f [DAGCombiner] Add EXTRACT_SUBVECTOR to SimplifyDemandedVectorElts adds b58cfae435c Use const APInt& to avoid extra copy. NFCI. adds 074b7c3a09e [SelectionDAG] Split float and integer isKnownNeverZero tests adds 7bae6f41cec [X86] Regenerate PR14088 test. NFCI. adds 560d937f1dc [X86] Use a rounding mode other than 4 in the scalar fma in [...] adds 455fcc664fe [X86] Add new scalar fma intrinsics with rounding mode that [...] adds 5c9e6ab590d [X86] Add back some intrinsic table entries lost in r336506. adds 7d6057ca556 [LoopIdiomRecognize] Support for converting loops that use [...] adds 750b8ba6b61 [MCA][X86][NFC] Add BSF/BSR resource tests adds 330c7eb5b8c [X86][Basically NFC] Sched: split WriteBitScan into WriteBS [...] adds d160cee4e47 [X86] Set scheduler classes to unsupported. NFCI. adds 6656bc9f257 [X86][SSE] Combine v16i8 SHL by constants to multiplies adds 2ad74abae51 [X86] Enhance combineFMA to look for FNEG behind an EXTRACT [...] adds 1f94f5a559e [X86][Nearly NFC] Split SHLD/SHRD into their own WriteShift [...] adds 2ee4a67a673 [X86] Remove an AddedComplexity line that seems unnecessary. adds 73888073048 [X86] Improve the message for some asserts. Remove an if th [...] adds 51d3739fb8c [PGOMemOPSize] Preserve the DominatorTree adds ceac96362f6 [AccelTable] Dwarf5AccelTableEmitter -> Writer (NFC) adds f8d4a3aecfd [AccelTable] Provide abstraction for emitting DWARF5 accele [...] adds 4e2f2576ac5 [AArch64][SVE] Asm: Support for UZP and TRN instructions. adds 1c576638ca6 [AArch64][SVE] Asm: Support for ADR instruction. adds 5070d36f882 Lift JSON library from clang-tools-extra/clangd to llvm/Support. adds 1cbf1da4d65 [PM/Unswitch] Fix a nasty bug in the new PM's unswitch intr [...] adds 6da02771fb8 [Support] Fix GCC compile after r336534 adds 8d164e7fb3d [Support] Make JSON handle doubles and int64s losslessly adds ceb3c09eb4c [Support] Allow JSON serialization of Optional<T> for supported T. adds d77ac0d3a5b [llvm-mca] report an error if the assembly sequence contain [...] adds 93fba7b3ae4 [AArch64][SVE] Asm: Support for TBL instruction. adds b9d744a0d2c [mips] Addition of the [d]rem and [d]remu instructions adds f03a571cbf3 [InstCombine] fix shuffle-of-binops transform to avoid pois [...] adds 317ed53ce58 [AArch64][SVE] Asm: Support for remaining shift instructions. adds 0b08bea28be [Power9] Add __float128 support for compare operations adds 955b8d422de [CVP] Handle calls with void return value. No need to creat [...] adds da1756486d7 [AArch64][SVE] Asm: Support for CNT(B|H|W|D) and CNTP instr [...] adds dc4af2458e3 [VPlan][LV] Introduce condition bit in VPBlockBase adds 76feca7c86f [X86] Remove some seemingly unnecessary AddedComplexity lines. adds e7dd6fb9bef [X86] Remove some patterns that seems to be unreachable. adds a7002f57585 [X86] Remove some patterns that include a bitcast of a floa [...] adds fa29fd677fd [InstCombine] generalize safe vector constant utility adds 798b3ef0fcd [BitcodeReader] Infer the correct runtime preemption for Gl [...] adds a5d860c4719 [dsymutil] Add support for outputting assembly adds c2d5ed64547 [InstCombine] avoid extra poison when moving shift above shuffle adds 18f7f341df1 [X86][AVX] Regenerate AVX1 fast-isel tests. adds eb849ef7956 [X86] In combineFMA, make sure we bitcast the result of isF [...] adds 202c8c5e5bb [InstCombine] correct test comments; NFC adds fdaaa22a5ca [LoopInfo] Port loop exit interfaces from Loop to LoopBase adds 24020ee58bc Add bitcode compatibility test for 6.0 adds f2fd9eaa8e6 [SelectionDAG] Add VT consistency checks to the creation of [...] adds 5e8a352aa6d [DebugInfo] Change default value of FDEPointerEncoding adds 3ea14f7d95a [Power9] Add __float128 builtins for Round To Odd adds 378d508446e [Utils] Fix gdb pretty printers to work with Python 3. adds 9e386ad60d4 [X86][TLI] DAGCombine: Unfold variable bit-clearing mask to [...] adds 12d30e1e277 AMDGPU: Force inlining if LDS global address is used adds 28793aedf68 [AMDGPU][Waitcnt] fix "comparison of integers of different [...] adds d700c295ab8 [globalisel][irtranslator] Add support for atomicrmw and (s [...] adds 88b9c135285 RenameIndependentSubregs: Fix handling of undef tied operands adds 8e48754afe3 [Power9] [LLVM] Add __float128 support for trunc to double [...] adds 7b100837117 [WebAssembly] Improve readability of load/stores and tests. NFC. adds 7ee7123814d [Power9] Add __float128 builtins for Rounding Operations adds 211f0307b2f Fix line endings. NFCI. adds ae0f1dc9280 [ORC] Rename MaterializationResponsibility::delegate to rep [...] adds 401e29e8b78 Make llvm.objectsize more conservative with null adds 1897a62c2ef Use StringRef instead of `const char *`. adds c6da6867a1d llvm: Add support for "-fno-delete-null-pointer-checks" adds b737b070e3e [WebAssembly] Support for binary atomic RMW instructions adds 1cc2d659530 [InstCombine] allow more shuffle folds using safe constants adds 94f396c4e1e [DWARF][NFC] Refactor range list emission to use a static helper adds 3bda4ed0ecf Revert "AMDGPU: Force inlining if LDS global address is used" adds cc4b35dde44 [X86] Remove FloatVT from X86VectorVTInfo in X86InstrAVX512.td adds ed86411ba99 [X86] Add test cases that show failure to fold load into vf [...] adds 784e3eb4914 [X86] Correct vfixupimm load patterns to look for an intege [...] adds 0758f84dc32 [X86] Add back GCCBuiltin on mask_div_ss/sd_round. adds 40da47fe008 [X86] Remove some seemingly unnecessary patterns. adds 650cfa6dc06 [X86] Use IsProfitableToFold to block vinsertf128rm in favo [...] adds b66a4fe5b73 [X86] Regenerate vector-shuffle-512-v8.ll so the script wil [...] adds 237e0b6b434 [X86][SSE] Prefer BLEND(SHL(v,c1),SHL(v,c2)) over MUL(v, c3) adds 785db918619 [X86] Fast-isel tests for lowered truncation intrinsics adds f0e0135e659 [PM/Unswitch] Fix a collection of closely related issues wi [...] adds bdef81ad962 [PM/Unswitch] Fix unused variable in r336646. adds 9cec565a79f Fix MSVC "signed/unsigned mismatch" warning. NFCI. adds 20b07351273 [VPlan] Add VPlanTestBase.h with helper class to build VPla [...] adds 862b1ab9346 [DAGCombiner] Split SDIV/UDIV optimization expansions from [...] adds 18ff70955fb [Support] Harded JSON against invalid UTF-8. adds 8008d9214cc [LowerSwitch] Fixed faulty PHI nodes adds c5c3efb2ec3 [Hexagon] Add implicit uses even when untied explicit uses [...] adds 1a63bb49cb0 [DAGCombiner] visitREM - call visitSDIVLike/visitUDIVLike d [...] adds c1175857e2e [DebugInfo][LoopVectorize] Preserve DL in induction PHI and Add adds db58626da58 [InstCombine] allow more shuffle-binop folds with safe constants adds e07c9538b54 Reapply "AMDGPU: Force inlining if LDS global address is used" adds 321acf353ee [AArch64][SVE] Asm: Support for predicated unary operations. adds 4b885003421 [InstCombine] drop poison flags when shuffle mask undef pro [...] adds 4575d3492bd Support -fdebug-prefix-map in llvm-mc. This is useful to o [...] adds d94b2b4b7f8 [Hexagon] Change .mir testcase to make sure function is not [...] adds db3db6b2b65 Add CachedHashStringRef::data(). adds 57f9ec67396 [InstCombine] safely allow non-commutative binop identity c [...] adds 7176a5d65f5 Update test to work on Windows adds 74dc40422c2 [MC] Add interface to finish pending labels. adds 5e52c9ed250 AMDGPU/NFC: Fix typo in test name adds a553f67e44a [WebAssembly] Add missing a few {{$}}s to a test adds 8d4bfa624a5 [gcov] Fix ABI when calling llvm_gcov_... routines from ins [...] adds 91833b661fa [X86] Add srem/udiv/urem by constant tests adds 128882e5b63 [InstCombine] allow flag propagation when using safe constant adds febd9a0f028 AMDGPU: Make hidden argument metadata consistent with amdgp [...] adds c031419fe66 Revert "[AccelTable] Provide abstraction for emitting DWARF [...] adds fe8c951cfd9 [DAGCombiner] Add special case fast paths for udiv x,1 and [...] adds ab6c6cb9932 [Evaluator] Examine alias when evaluating function call adds c11402ea82d [GlobalISel][X86_64] Support for G_SITOFP adds 5c37ae1e46f [AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC) adds 7613264ef4a [CMake] Teach the build system to codesign built products adds 43680a049cc [X86] Remove AddedComplexity from MMX_X86movw2d patterns. adds f3303f010c0 [X86] Remove AddedComplexity from register form of NOT. NFCI adds 071f23bbb92 [CMake] Set per-runtime library directory suffix in runtimes build adds b0ec158d067 Revert r336653 "[VPlan] Add VPlanTestBase.h with helper cla [...] adds 4bac7448e75 [X86] Remove dead SDNode object from X86InstrFragmentsSIMD.td. NFC adds 7b0ba29ddb6 [ThinLTO] Use std::map to get determistic imports files adds 47362da9679 [AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC) adds d455726cf4f [X86] Remove X86ISD::MOVLPS and X86ISD::MOVLPD. NFCI adds 3b874f619c3 [NFC] typo adds 5fd5b23e94e [X86] Teach X86InstrInfo::commuteInstructionImpl to use MOV [...] adds 2c1b42aecbf Fix -Wmismatched-tags warning adds 42c5f73d3bb [X86] Remove AddedComplexity from all patterns that use X86 [...] adds b3a7b8e1235 Sort includes + include a missing `extern "C"` header adds 635418475ae [ORC] Generalize alias materialization to support re-export [...] adds 43b8da3b5b4 [ARM] Treat cmn immediates as legal in isLegalICmpImmediate. adds ca521172652 [LangRef] Clarify alloca of zero bytes. adds ab7abafe4c9 [TableGen] Fix some bad formatting. NFC adds cebe6b04b04 [test cases] add test cases for find more abs pattern adds 9e4aa1f63d0 [Power9] Add remaining __flaot128 builtin support for FMA r [...] adds 1399f710b38 [ORC] Use a gtest fixture to remove a bunch of boilerplate [...] adds 8cbf4142f33 [ORC] Drop constexpr in unit test to appease a bot. adds 153b1da7646 [WebAssembly] Add pass to infer prototypes for prototype-le [...] adds d16b7e57845 [ORC] Add unit tests for the reexports utility that were le [...] adds eb79fe37964 [ORC] Remove a shadowing definition. adds 25618d5e9e9 [X86] Remove some composite MOVSS/MOVSD isel patterns. adds bcf1a2ec72d Revert r336760: "[ORC] Add unit tests for the reexports uti [...] adds 002bef1dc82 [X86] The TEST instruction is eliminated when BSF/TZCNT is used adds d07522f0425 [WebAssembly] Only call llvm::value::dump() in debug build. adds 9cfd4e54080 [TableGen] Add a general-purpose JSON backend. adds 7adaa4250a0 [TableGen] Add missing std::moves to fix build failure. adds 8884a4f1aab [DAGCombiner] Add (urem X, -1) -> select(X == -1, 0, x) fold adds 1472199dc3a [DAGCombiner] Support non-uniform X%C -> X-(X/C)*C folds adds d1c9cdb25aa [mips] Remove dead code. NFC adds 6f6e8e488bf [llvm-mca] Add tests for partial register writes. adds 51a70b932d4 [SelectionDAG] Add constant buildvector support to isKnownN [...] adds cf6cd675f0f [NFC][InstCombine] Add variable names and regenerate icmp-l [...] adds 25074d6f872 [NFC][InstCombine] Fix extra space padding in icmp-mul-zext [...] adds 94b0940142a [llvm-readobj] Add -hex-dump (-x) option adds 762a5bb3aec [AArch64][SVE] Asm: Support for LAST(A|B) and CLAST(A|B) in [...] adds 2bb63d0b093 [NFC][InstCombine] icmp-logical.ll: add a few more tests. adds aae5bb5ebfd [AArch64] Regenerate SDIV tests adds 5ee4539c4ce Fix check-prefix vs check-prefixes typo in updated test adds dccc8cca6c3 [AArch64][SVE] Asm: Support for COMPACT instruction. adds be9aa7feff2 Recommit r336653: [VPlan] Add VPlanTestBase.h with helper adds f0c06bd7673 Use debug-prefix-map for AT_NAME adds f72585ca173 [ARM] ParallelDSP: multiple reduction stmts in loop adds 6c02a48ba4f [NFC][InstCombine] Tests for x & (-1 >> y) == x -> x u<= [...] adds 483861bc323 [llvm-mca] Use a different character to flag instructions w [...] adds 336c1aeeb5c [NFC][InstCombine] Converts isLegalNarrowLoad into isLegalN [...] adds aa6263071e1 [mips] Update the P5600 scheduler model not to use instruct [...] adds 873b4b66d3f [CodeGen] Ignore debug uses in MachineCopyPropagation adds 71b0da15d21 [SLPVectorizer] Add initial alternate opcode support for ca [...] adds abad63db770 Recommit r334887: [SmallSet] Add SmallSetIterator. adds 191ae9ef3c5 Revert rL336804: [SLPVectorizer] Add initial alternate opco [...] adds 86d8ba10055 [SLPVectorizer] Add some additional alternate cast tests adds 96954e8f95a [SLPVectorizer] Ensure alternate/passthrough doesn't vector [...] adds 33f4d61062f [SLPVectorizer] Add initial alternate opcode support for ca [...] adds 3a44ccd156e [llvm-objdump] Add -demangle (-C) option adds 9972f984825 [X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions. adds d5cfc836bb5 Fix llvm-objdump demangle test (added triple option) adds 67a7a09e83b [InstSimplify] add/move tests for add folds; NFC adds f8497881d6a [DebugInfo] Make children iterator bidirectional adds 04804b2f45b AMDGPU/NFC: Use already available explicit kernarg size ins [...] adds 7a7cfd8a89e [TargetTransformInfo] Add pow2 analysis for scalar constants adds f8a7a167d2a [X86] Remove patterns for inserting a load into a zero vector. adds 31b21da1552 Revert "[llvm-objdump] Add -demangle (-C) option" adds c642c1b4d70 [FileCheck] Don't permit overlapping CHECK-DAG adds 9f8f3ca775d Quick fix for some Windows bots adds 0e8a665664f Revert r336830: [FileCheck] Don't permit overlapping CHECK-DAG adds 2dd26c97a82 [InstCombine] Fold x & (-1 >> y) == x to x u<= (-1 >> y) adds adfcff45eef [DebugInfo] Fix getPreviousSibling after r336823 adds 35e8f7fa33f gold: Add ability to toggle function/data sections adds ea13527137d Revert "[docs] As of binutils 2.21.51.0.2, ld.bfd supports [...] adds ce57a4ff8c2 [FileCheck] Add -allow-deprecated-dag-overlap to failing ll [...] adds 0195c0bee91 [FileCheck] Don't permit overlapping CHECK-DAG adds 3c69e867ac4 finish: [FileCheck] Add -allow-deprecated-dag-overlap to fa [...] adds 1d6fd076a3d AMDGPU: Refactor Subtarget classes adds d2f9dac4f9e AMDGPU: Remove duplicate call to initializeSubtargetDependencies() adds 2517f169abe [NFC][InstCombine] Tests for x & (-1 >> y) != x -> x u> [...] adds 1935f944384 Temporarily reverting. adds 9c94a76f7ad [MemorySSA] Add APIs to move memory accesses between blocks [...] adds 469c8eebd97 AMDGPU/SI: Initialize InstrInfo before TargetLoweringInfo i [...] adds a6e34881bcb [LoopIdiomRecognize] Add a test case showing a loop we turn [...] adds 99a2c222c24 [LoopIdiomRecognize] Don't convert a do while loop to ctlz. adds 87c3b54a362 [CodeGen] Emit more precise AssertZext/AssertSext nodes. adds 15753b03821 IR: Skip -print-*-all after -print-* adds 9e49a81863c Add -allow-deprecated-dag-overlap to one of the experimenta [...] adds 18d8ba4a182 [X86] Remove and autoupgrade the scalar fma intrinsics with [...] adds 6c31f1e00d9 [x86] Fix EFLAGS copy lowering to correctly handle walking [...] adds 68cefd37e8e [X86] Add patterns to use VMOVSS/SD zero masking for scalar [...] adds 60aba7d664a [x86] Fix another trivial bug in x86 flags copy lowering th [...] adds d972c63af4b Temporarily revert "Recommit r328307: [IPSCCP] Use constant [...] adds f831f82f3ec [AsmParser] Fix inconsistent declaration parameter name adds 7d5acd8e56e [InstSimplify] simplify add instruction if two operands are [...] adds ad360c850d4 [X86] Remove patterns and ISD nodes for the old scalar FMA [...] adds 04d4b7fd45b [Dominators] Add isUpdateLazy() method to the DomTreeUpdater adds ae80745b73e Fix few typos in comments (write access test commit) adds ee39f0be06f [Support] Require llvm::Error passed to formatv() to be wra [...] adds 82b46012db9 [X86] Remove i128 type from FR128 regclass. adds f35639b8448 [mips] Mark standard encoded instructions as not being in MIPS16e adds 2a6ae651e56 [X86] Add UDIV by uniform/non-uniform constant tests adds 8bda54e5087 Fix -Wdocumentation warnings. NFCI. adds ecc246961c8 [UnJ] Use SmallPtrSets for block collections. NFC adds 2d2bdce25ce [X86][AVX] Use Zeroable mask to improve shuffle mask widening adds 36dba4ab0ce [InstCombine]add testcases for folding more SPFofSPF pattern adds 33468275adc [X86][SSE] Utilize ZeroableElements for canWidenShuffleElements adds cf57e1b7d10 [XRay] Fix machine verifier issues in X86 adds 0ae89b82685 [DebugInfo][X86] Add start-after flags to MIR tests adds f6e61654a19 [ThinLTO] Escape module paths when printing adds 83a86dd616b [InstCombine] Fold x & (-1 >> y) != x to x u> (-1 >> y) adds fd0e24d7eaa [InstCombine] icmp-logical.ll: restore the original intenti [...] adds e425a8e34ad [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset ins [...] adds 8840e88391b Follow up of r336913: forgot to add the new test files. adds e427001e40b [llvm-mca] Simplify eventing by adding an onEvent templated [...] adds d595b3ce746 [NFC][X86][AArch64] Add tests for the 'check for [no] signe [...] adds df4581eddcf Add --strip-all option back to llvm-strip. adds 0f2affe94be Reverted r336805 as it broke llvm-clang-x86_64-expensive-ch [...] adds 6e9115adb50 [X86][FastISel] Choose EVEX instructions when possible when [...] adds e3a92755ac6 [X86] Connect the flags user from PCMPISTR instructions to [...] adds c11a95fb078 [DWARF v5] Generate range list tables into the .debug_rngli [...] adds 50f2228bda9 CodeGen: Remove pipeline dependencies on StackProtector; NFC adds 87100fdc04a Revert "(HEAD -> master, origin/master, arcpatch-D37582) Co [...] adds 4835c04d29a AMDGPU: Fix assert in truncate combine with vectors adds 33929672874 [X86] Add show-mc-encoding to some fast-isel intrinsic test [...] adds 7cf5f05b8cd [X86][FastISel] Support EVEX version of sqrt. adds a120e0c37ce [PowerPC] [NFC] Update __float128 tests adds 3418676967e [SanitizerCoverage] Add associated metadata to 8-bit counters. adds 0a4671b355d [gold-plugin] Disable section ordering for relocatable links adds 54919303bfc Revert "[SLPVectorizer] Add initial alternate opcode suppor [...] adds 197f95f9b9f foo adds 30251f27e54 [X86] Add AVX512 equivalents of some isel patterns so we ge [...] adds 1a14ab01567 Remove redundant *_or_null checks; NFC adds 20f01a8a7d3 Revert r336950 and r336951 "[X86] Add AVX512 equivalents of [...] adds 9bd050eb937 [X86] Add AVX512 equivalents of some isel patterns so we ge [...] adds 07757b9f4ce [InstCombine] Simplify isKnownNegation adds b9bc17351ee [X86] Regenerate checks in sse-scalar-fp-arith.ll. adds 5c43c4ce5f1 [llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage. adds fda9d387d8f [llvm-mca] Constify SourceMgr::hasNext. NFC. adds 674f0a11744 Simplify recursive launder.invariant.group and strip adds d79789afc64 CodeGen: Remove pipeline dependencies on StackProtector; NFC adds 8a35df349b4 [InstCombine] return when SimplifyAssociativeOrCommutative [...] adds 9074a87ea5f [FileCheck] Implement -v and -vv for tracing matches adds bc2f48c38d3 [DomTreeUpdater] Ignore updates when both DT and PDT are nullptrs adds 8383d4d295e [X86] Remove isel patterns that turns packed add/sub/mul/di [...] adds 93177460538 [XRay][compiler-rt] Add PID field to llvm-xray tool and add [...] adds 1b59f048c70 [X86] Prefer MOVSS/SD over BLEND under optsize in isel. adds b76c4539710 [LiveDebugValues] Tracking copying value between registers adds 3723787cc35 [AArch64][SVE] Asm: Support for insert element (INSR) instr [...] adds 19f4c1ecb2b [ARM] Regenerated arg endian test adds 1726fda3b28 [AArch64] Updated bigendian buildvector tests adds ce729e20ee9 [AArch64][SVE] Asm: Vector Unpack Low/High instructions. adds 27babdf37a5 [llvm-mca] Removed unused arguments from methods in class P [...] adds ed770b652cb [llvm-mca] Simplify the Pipeline constructor. NFC adds 5f81eab1b7a [x86] Teach the EFLAGS copy lowering to handle much more co [...] adds c3bd8ccb0d7 [x86] Fix a capitalization that I failed to save in my edit [...] adds 0bc0c53ebab [UpdateTestChecks] Teach the x86 asm parser to skip over th [...] adds 1e086c7b69c [SLPVectorizer] Add initial alternate opcode support for ca [...] adds bd8c8d75985 [SLH] Introduce a new pass to do Speculative Load Hardening [...] adds 6069d4b651b DivergenceAnalysis: added debug output adds 3a90426c48f [TableGen] Support multi-alternative pattern fragments adds 8689f3429dd [NFC] Silence Wparentheses warning in DomTreeUpdater, intro [...] adds edc45eb6a43 Add parens to silence Wparentheses warning, introduced by 336990 adds 6ff281cc606 [llvm-mca] Improve a few debug prints. NFC adds 7c86c0663d5 [mips] Add microMIPS case to the tests and regenerate asser [...] adds 2eb5b221110 [json, test] Fix the json.td test - the path to python coul [...] adds 8352988dc15 [cfi-verify] Support AArch64. adds 674b14846a3 [PowerPC] Materialize more constants with CR-field set in l [...] adds f907c503aba [AArch64] Armv8.4-A: LDAPR & STLR with immediate offset ins [...] adds 0b0731cbb0b [dwarfdump] Pretty print DW_AT_APPLE_runtime_class adds 57726810dce [cfi-verify] Only run AArch64 tests when it is a supported target adds a97ad691465 [NFC][X86][AArch64] Negative tests for 'check for [no] sign [...] adds b7219f9e807 Revert "CallGraphSCCPass: iterate over all functions." adds f185b903488 [Tablegen] Optimize isSubsetOf() in AsmMatcherEmitter.cpp. NFC adds e61b6779e4a AMDGPU: Fix handling of alignment padding in DAG argument lowering adds 9c21e67b4cb AMDGPU: Properly handle shader inputs with split arguments adds c62320ccc0e [TableGen] Suppress type validation when parsing pattern fragments adds b6e0532b347 [llvm-mca][BtVer2] Add tests for dependency breaking instructions. adds 6ab694dd51e [dwarfdump] Add pretty printer for accelerator table based [...] adds 7dc602e5164 [LowerTypeTests] Limit when icall jumptable entries are emitted adds b4c1bb4999a Revert "[CMake] Pass Clang defaults to runtimes builds" adds 7d364253764 [NFC][InstCombine] Tests for 'check for [no] signed truncat [...] adds 20e85b879b1 [X86] Try fixing r336768 adds e6cdf32fe6d [X86][FastISel] Add EVEX support to sitofp handling. adds 504eed44cd3 AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp adds 3393e5b81db [ThinLTO] Ensure we always select the same function copy to import adds 6716a6f8768 [X86] Correct comment of TEST elimination in BSF/TZCNT adds 5119a48bec2 [LTO] Fix linking with an alias defined using another alias. adds f173f479c2e [X86][FastISel] Support uitofp with avx512. adds 37f081b80d3 AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minn [...] adds eede34f491c [X86] Use the correct types in some recently added isel patterns. adds af68baa2093 [ThinLTO] Require x86 target for new test adds 0f11eb4472d Clarify wording of a doxygen comment, NFC adds 2d1b15b0368 Fix comments which mixed up 'before' and 'after', NFC adds 1c00edf2e4f [docs] Update usage directive for llvm-cov report -show-functions adds 0f602cf8528 [X86][SLH] Regroup the instructions in isDataInvariantLoad [...] adds 2c5f2079745 [X86][SLH] Add VEX and EVEX conversion instructions to isDa [...] adds 7cd0250e8e6 [X86][SLH] Remove PDEP and PEXT from isDataInvariantLoad adds c31e75d1995 [LSR] If no Use is interesting, early return. adds e29dbca9525 [Hexagon] Avoid introducing calls into coalesced range of H [...] adds c9b1b5c60b7 Add a CHECK line for r337072. adds fab6a247ff4 Re-apply "[SCEV] Strengthen StrengthenNoWrapFlags (reapply [...] adds d0c165bf244 [ThinLTO] Add debug output to test adds 24ec170d118 [llvm-mca] Remove unused InstRef formal from pre and post e [...] adds 383081c48d2 [x86/SLH] Add an assert to catch if we ever end up trying t [...] adds 1382a3a7e81 Revert "AMDGPU: Fix handling of alignment padding in DAG ar [...] adds 73389a219db Revert "[ThinLTO] Add debug output to test" adds 43658456ae9 Revert "[ThinLTO] Ensure we always select the same function [...] adds 60ba444e117 [X86] Prefer blendi over movss/sd when avx512 is enabled un [...] adds 981f0755e21 Give llvm-lib rudimentary help output. adds b77be895f41 [X86] Fix a subtle bug in the custom execution domain fixin [...] adds 6490d2153ff [x86/SLH] Fix an issue where we wouldn't harden any loads i [...] adds 9d51c1875e9 [MachineOutliner] Check the last instruction from the seque [...] adds c52910957c4 Attempt to get test/tools/llvm-lib/help.test passing on san [...] adds 69508765409 [NFC][InstCombine] Add forgotten variable tests for foldICm [...] adds 3f53e3baf51 [NFC][InstCombine] Tests for x & (-1 >> y) u>= x to x u< [...] adds 21d6697e493 [InstCombine] Fold x & (-1 >> y) u>= x to x u<= (-1 >> y) adds 5dfb6962209 [NFC][InstCombine] Tests for x & (-1 >> y) u< x to x u> [...] adds 81c991bbc41 [InstCombine] Fold x & (-1 >> y) u< x to x u> (-1 >> y) adds 1c239349f3f [NFC][InstCombine] Tests for x u> x & C to x u> C fold. adds fc95a84f5d0 [InstCombine] Fold x u> x & C to x u> C adds 67041dddbe7 [NFC][InstCombine] Tests for x u<= x & C to x u<= C fold. adds d8e175bca59 [InstCombine] Fold x u<= x & C to x u<= C adds 39ce2d4bc8b [NFC][InstCombine] Tests for x s> x & (-1 >> y) to x s> [...] adds f938155483d [InstCombine] Fold x s> x & (-1 >> y) to x s> (-1 >> y) adds fe2b66265c0 [NFC][InstCombine] Tests for x s<= x & (-1 >> y) to x s< [...] adds 0e039b76e09 [InstCombine] Fold x s<= x & (-1 >> y) to x s<= (-1 >> y) adds 56ad5a26da7 [NFC][InstCombine] Tests for x & (-1 >> y) s>= x to x s< [...] adds 0d94eaa92c6 [InstCombine] Fold x & (-1 >> y) s>= x to x s<= (-1 >> y) adds ec6933aa840 [NFC][InstCombine] Tests for x & (-1 >> y) s< x to x s> [...] adds 3a68fbf4b51 [InstCombine] Fold x & (-1 >> y) s< x to x s> (-1 >> y) adds 6e43f22733d [NFC][InstCombine] foldICmpWithLowBitMaskedVal(): update comments. adds 37ac9396a03 [llvm-mca] Turn InstructionTables into a Stage. adds 674b07eaef7 [TableGen] Add some std::move to the PatternToMatch constructor. adds 7ed67c245ac [CMake] Pass CMAKE_INSTALL_DO_STRIP to external projects adds 9d61922fe7c [X86] Add some optsize patterns for 256-bit X86vzmovl. adds ecb89054528 [TableGen] Remove what seems to be an unnecessary std::map copy. adds cfe3c915262 [TableGen] std::move vectors into TreePatternNode. adds f23126d10ee [AVR] Document some public functions adds eaabc71261e [llvm-mca][BtVer2] teach how to identify false dependencies [...] adds 2d2ebb317ec [llvm-mca] Regenerate X86 specific tests. NFC adds 4dd709869f4 [InstSimplify] add tests for minnum/maxnum; NFC adds 268055dd8ce [InstSimplify] fold minnum/maxnum with NaN arg adds 24d52ec9f94 [AMDGPU] adjusted test checks because minnum with NaN gets [...] adds 7120b1dbea6 [InstSimplify] add fixme comment for PR37776; NFC adds 08378e6ecfb [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) adds 597deb92844 [InstCombine] Corrections in comments for division transfor [...] adds a464223848e [DAGCombiner] fix typo in comment; NFC adds c7482ced308 [X86] Use 128-bit ops for 256-bit vzmovl patterns. adds ea81bb5e03d [X86] Use 128-bit blends instead vmovss/vmovsd for 512-bit [...] adds 2012494a47b [X86] Add load patterns for cases where we select X86Movss/ [...] adds 29bd1172553 [X86] Add custom execution domain fixing for 128/256-bit in [...] adds 198f71f698c [x86/SLH] Extract one of the bits of logic to its own funct [...] adds 0ad50ac3b85 Prune empty directory. adds 3da6ce5ebe1 Recommit r335794 "Add support for generating a call graph p [...] adds 727a214dd58 [InstCombine] fold icmp pred (sub 0, X) C for vector type adds d27cef10a89 [InstCombine] add more SPFofSPF folding adds 07f0205adef [x86/SLH] Teach speculative load hardening to correctly har [...] adds d8c8d742377 [x86/SLH] Fix an unused variable warning in release builds [...] adds 40a777270d9 [X86] Merge the FR128 and VR128 regclass since they have id [...] adds 353f7b5433c [MemorySSAUpdater] Remove deleted trivial Phis from active workset adds 356f9421a19 Revert "[AMDGPU][Waitcnt] fix "comparison of integers of di [...] adds 249b255c788 run post-RA hazard recognizer pass late adds 0f2a60eba6d [MSan] factor userspace-specific declarations into createUs [...] adds a7209581698 [AMDGPU][Waitcnt] Re-apply fix "comparison of integers of d [...] adds 393d0de3894 [x86/SLH] Extract another small helper function, add better [...] adds ea9f37558a4 [AccelTable] Provide DWARF5AccelTableStaticData for dsymutil. adds 06a94a9b18a MSan: minor fixes, NFC adds 7847cb2c366 [x86/SLH] Fix a bug where we would try to post-load harden [...] adds fd7429c4e7b Avoid losing Hi part when expanding VAARG nodes on big endi [...] adds 1c521ba7c7a [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic adds fb8753f34b8 [Sparc] Use the names .rem and .urem instead of __modsi3 an [...] adds 84ab5c258ac [Sparc] Use the correct encoding for ta 3 adds 0c94a3b5119 [X86][AArch64][DAGCombine] Unfold 'check for [no] signed tr [...] adds f85073912f3 [MIPS GlobalISel] Select instructions to load and store i32 [...] adds 7d9d92b62e4 [mips] Eliminate the usage of hasStdEnc in MipsPat. adds 63110793937 [x86/SLH] Completely rework how we sink post-load hardening [...] adds 0a3ff055189 [InstrSimplify] add testcases for fold sdiv if two operands [...] adds e27b1d0b0f6 [cfi-verify] Abort on unsupported targets adds 92f58789014 Restore "[ThinLTO] Ensure we always select the same functio [...] adds 735bf22bd79 [RegAlloc] Skip global splitting if the live range is huge [...] adds a5425a350eb [InstCombine] Fold 'check for [no] signed truncation' pattern adds bffcc487e3e [llvm] Change 2 instances of std::sort to llvm::sort adds ac8c393bd50 [AMDGPU] [AMDGPU] Support a fdot2 pattern. adds 7d88286b7cf [CodeGen] Fix inconsistent declaration parameter name adds 51e4fb6e38b [llvm-objcopy] Add support for large indexes adds e5c7b32694a [NFC][InstCombine] Fine-tune 'check for [no] signed truncat [...] adds 937d2c0dee0 [LLVMDemangle] Move some utility classes to header files. adds d554de1ec8d Add missing includes. adds 9dce11c0cfb [llvm-mca][docs] Initial description of mca internals. NFC adds 41306baa27e [NFC][llvm-objcopy] Make helper functions static adds bb12f48c1c3 [Intrinsics] define funnel shift IR intrinsics + DAG builde [...] adds 2a147a15071 [WebAssembly] Remove ELF file support. adds 1fbf51fadc1 [X86] Add a missing FMA3 scalar intrinsic pattern. adds 40b80a4e12e [llvm-mca][docs] Add notes about cycle and resource callbac [...] adds d13c7c50a3c [testcases] move testcases to right place - NFC adds 605986cfafd [X86] Add test cases for selecting floor/ceil/trunc/rint/ne [...] adds 7904f0b1e7b [X86] Add full set of patterns for turning ceil/floor/trunc [...] adds 00e3426bc2b [Sparc] Do not depend on icc for ta 1 adds 7468eaa74b8 [X86] Properly qualify some MOVSS/MOVSD patterns with OptSize. adds 46f56568b28 [AArch64][SVE] Asm: Support for EXT instruction. adds 6151dbec931 [AArch64][SVE] Asm: Support for SPLICE instruction. adds 15fa57ae79a Fix MSVC "result of 32-bit shift implicitly converted to 64 [...] adds ead04a95599 [DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_ [...] adds ca47e5e7673 [AArch64][SVE] Asm: Support for predicated FP operations. adds f948d85a47d [llvm-objcopy] Run not with any python, but the python conf [...] adds 1907eb80ac0 [LLVM-C] Add target triple normalization to the C API. adds 938172a55a8 [LLVM-C] Fix name mangling on AggressiveInstCombine adds 7d1879721b1 Don't assert that a size_t fits into 64bit. adds 1c105a00ab9 [NFC][testcases] add testcases for folding srem whose opera [...] adds 5431fe06df8 [AArch64][SVE] Asm: Support for predicated FP operations (F [...] adds 79ed3bcca7d More fixes for subreg join failure in RegCoalescer adds de720479bb1 [SLPVectorizer] Don't attempt horizontal reduction on point [...] adds 73739643d7b [AArch64][SVE] Asm: FP fused multiply-add/subtract instructions. adds 35603461c5a [IPSCCP] Run Solve each time we resolved an undef in a function. adds 87d8be53fdd [Mips][FastISel] Fix handling of icmp with i1 type adds a5d63899381 Recommit r334887: [SmallSet] Add SmallSetIterator. adds eabdfbb4b22 [AArch64][SVE]: Integer multiply-add/subtract instructions. adds 1885077d4c3 [Tablegen][PredicateExpander] Fix a bug in `expandCheckImmO [...] adds 95e53c28897 [llvm-mca][docs] Revert mca internals docs. adds c1bbb5ef59c [llvm-mca][x86] Add LEA resource tests (PR32326) adds b31fad1c7b0 [llvm-mca][x86] Add displacement-only and additional scale= [...] adds e40f77a66b7 [X86] Remove some standalone patterns in favor of the patte [...] adds cf065f71183 [WebAssembly] Update WebAssemblyLowerEmscriptenEHSjLj to ha [...] adds cc5fc420331 [llvm-mca][x86] Add BSWAP resource tests adds a5ec686ea52 Revert rL337292 due to another MSVC STL problem. adds c8068fe5e7d [llvm-mca][x86] Add MOVBE resource tests to all supporting targets adds 7c3ca4315c0 [llvm-mca][x86] Add extend, carry-flag and CMP instructions [...] adds dc80a6e18ec [x86/SLH] Flesh out the data-invariant instruction table a [...] adds bbdc5a72a79 Remove an errant piece of !dbg metadata from a test, NFC adds f241fec5ea9 [InstCombine] Preserve debug value when simplifying cast-of-select adds dc84f3b6c1a Add some helper functions to the demangle utility classes. adds 08ea6f8319e Add missing include. adds cf121a0f053 [Demangle] Add missing header files adds 372f8c4f074 [X86] Add test case for missed opportunity to use MOVLPS on [...] adds 8fe83c7092e [X86] Add patterns for folding full vector load into MOVHPS [...] adds 1ea502b3c15 [LangRef] Clarify which fast-math flags affect fcmp. adds 9ff02efe80b [LangRef] nnan and ninf produce poison. adds 48ef58e6c15 [LangRef] Clarify semantics of load metadata. adds a29ff2e0f94 MC: Implement support for new .addrsig and .addrsig_sym dir [...] adds 03bb42af9d1 CodeGen: Add a target option for emitting .addrsig directiv [...] adds 9722c06a8a8 [X86] Remove the vector alignment requirement from the patt [...] adds b5b60c3d145 [NFC][llvm-objcopy] Cleanup namespace usage in llvm-objcopy. adds 70df6e955a6 CodeGen: Don't create address significance table entries fo [...] adds adf4ac8b228 Revert "[InstCombine] Fold 'check for [no] signed truncatio [...] adds 34ada1b5236 Add PowerPC e500(v2) core scheduler and directives. adds e0adf6dabf3 Complete the SPE instruction set patterns adds c486a43e863 Introduce codegen for the Signal Processing Engine adds b14a5d35fad [X86] Generate v2f64 X86ISD::UNPCKL/UNPCKH instead of X86IS [...] adds a65225ba1f4 [X86] Remove patterns that mix X86ISD::MOVLHPS/MOVHLPS with [...] adds e282c3c35e8 Fix build failures from r337347, found by clang adds f8f02e122b8 [NFC] fix trivial typos in comments adds a29d420a5f3 [X86] Regenerate fma.ll checks using current version of the [...] adds de4051f80c4 [X86] Add test case for missed opportunity to commute vunpc [...] adds b20ca5fcaa0 [X86] Enable commuting of VUNPCKHPD to VMOVLHPS to enable l [...] adds 6cf11788591 [AArch64][SVE] Asm: Support for integer MUL instructions. adds 8b3fece49e1 Revert test changes part of "Revert "[InstCombine] Fold 'ch [...] adds 8b80d4ecc24 [llvm-readobj] - Teach tool to dump objects with >= SHN_LOR [...] adds 10c3b3d15ed [llvm-objdump] - Stop reporting bogus section IDs. adds 9e5f1ea427c [NFC][InstCombine] i65 tests for 'check for [no] signed tru [...] adds c8f4a56750f [CMake] Export the LLVM_LINK_LLVM_DYLIB setting adds 3caa90973aa Fix -Wdocumentation warning. NFCI. adds 07e34c66633 Fix -Wdocumentation warning. NFCI. adds f600b10dd2a [AArch64][SVE] Asm: Integer divide instructions. adds 55222c9183c [Sparc] Use the IntPair reg class for r constraints with va [...] adds 9c475e370b8 [llvm-objdump] - An attempt to fix BB after r337361. adds a0223d639d9 [AArch64][SVE] Asm: Support for UDOT/SDOT instructions. adds 9500eff8991 Revert "[Sparc] Use the IntPair reg class for r constraints [...] adds 0c246047310 [X86][SSE] Add extra scalar fop + blend tests for commuted inputs adds 1cd41cb2709 [InstCombine] Re-commit: Fold 'check for [no] signed trunca [...] adds 3ac65c443f7 [Tablegen][PredicateExpander] Add the ability to define che [...] adds f1ed5421fd9 [NFC] Make a test more neat adds 73ce7fc085c [TargetInstPredicate] Add definition of CheckInvalidRegiste [...] adds 41ef3985c79 [AArch64][SVE] Asm: Support for unpredicated FP operations. adds 99893224eb0 ARM: deduplicate hard-float detection code. NFC. adds feb1bb8b826 ARM: switch armv7em triple to hard-float defaults and libcalls. adds b7eb4975c40 ARM: stop explicitly marking armv7k libcalls as hard-float. NFC. adds a50de627562 [X86][SSE] Remove BLENDPD canonicalization from combineTarg [...] adds 32e74a6f99f [Support] Build fix for Haiku when checking for a local filesystem adds 1a0909c7b21 [SLPVectorizer] Avoid duplicate scalar cost calculations in [...] adds f32280c8cd9 [x86/SLH] Add the design document for Speculative Load Hard [...] adds bd2bb96fb18 [mips] Fix predicate for the MipsTruncIntFP pattern adds 106f868ca63 [MC] Fix nested macro body parsing adds 8562c439b44 [llvm-objcopy] %python wants to be in quotes, because it mi [...] adds c279de70f62 [NFC][X86][AArch64][DAGCombine] More tests for optimizeSetC [...] adds baea3f05000 [llvm-objdump] Add -demangle (-C) option adds 19723d91b87 [RegAlloc][NFC] Fix the help string of the option "huge-siz [...] adds 7f233b7000a [docs] Update GoldPlugin documentation adds 9f006d32f1b [llvm-readobj] Generic -string-dump option adds 461ab257e2f [ScheduleDAG] Fix unfolding of SUnits to already existent nodes. adds 7e2280c100b [DebugInfo] Dwarfv5: Avoid unnecessary base_address specifi [...] adds 1b4d2184e19 [DAG] Add testcase. adds ca593328f30 Add (very partial) Kate syntax highlighting definition for [...] adds 5aa954ccaf2 Skip debuginfo intrinsic in markLiveBlocks. adds 6e4fb35e808 [X86][SSE] Canonicalize scalar fp arithmetic shuffle patterns adds d5bb6fb05a5 Fix some tests that had (implied) duplicate mtriple adds f7eb2f0fcb7 Revert "ARM: switch armv7em triple to hard-float defaults a [...] adds 9dc116b0c7e [WebAssembly] Add missing -mattr=+exception-handling guards adds e601e5fe08b Rename __asan_gen_* symbols to ___asan_gen_*. adds 62b518b75a7 [SCEV] Fix buggy behavior in getAddExpr with truncs adds ef2fcbd30cf Fix spelling mistake in comments. NFCI. adds cfc3a3cba21 Use std::reference_wrapper instead of llvm::ReferenceStorage adds 3a2e78e840c [DAGCombiner] Add rotate-extract tests adds d13704d44f3 [x86/SLH] Major refactoring of SLH implementaiton. There ar [...] adds 91823932bda [UnJ] Document unroll and jam pass and loop metadata adds 95f104ac2d5 ARM: switch armv7em MachO triple to hard-float defaults and [...] adds 629edfbb7a4 [Docs] Testing Debug Info Preservation in Optimizations adds 2a478d43e1f [ThinLTO] Enable ThinLTO WholeProgramDevirt and LowerTypeTe [...] adds efd8832ecba [llvm-readobj] - Do not report invalid amount of sections. adds 19ad9309e1e [X86][SSE] Add FPEXT vXf32 - vXf64 tests adds 3b09b9e80ea [X86][BtVer2] correctly model the latency/throughput of LEA [...] adds ae72a8c5708 [LoadStoreVectorizer] Use getMinusScev() to compute the dis [...] adds 5b81b48075a [libFuzzer] Update documentation regarding MSan. adds 3bb52cad65a [APInt] Keep the original bit width in quotient and remainder adds a02ad35dfa9 [OpenEmbedded] Add a unittest for aarch64-oe-linux adds 6e502837915 [Analysis] Fix typo in assert. NFC adds f9fb677cc24 [Power9] Code Cleanup - Remove needsAggressiveScheduling() adds b2f9f92413f [LSV] Refactoring + supporting bitcasts to a type of differ [...] adds a34dfe65428 Fix -Wsign-compare in llvm-readobj adds 85eba188bc6 [X86] Fix some 'return SDValue()' after DCI.CombineTo inste [...] adds 0d0107000d2 Disable GCC's -Wclass-memaccess warning adds b1b35797986 Work around bug in mingw-w64 GCC 8.1.0 adds e05bab28b64 [llvm-mca][docs] Add Timeline and How MCA works. adds 91284ba1d6e [X86][AVX] Use extract_subvector to reduce vector op widths [...] adds f97a90d9582 [DAGCombiner] Teach DAGCombiner that A-(-B) is A+B. adds d11d789e5ef [ThinLTO] Only emit referenced type id records in index files adds b3e4684b358 ADT: Shrink size of SmallVector by 8B on 64-bit platforms adds 7e9afd4946f Skip out of SimplifyDemandedBits for BITCAST of f16 to i16 adds 88c3cbe6a72 [SCCP] Don't use markForcedConstant on branch conditions. adds fc138001126 [docs] Add support for Markdown documentation in Sphinx adds 8e3c7f6cf64 [x86/SLH] Clean up helper naming for return instruction han [...] adds 0ee7ae5caa2 Revert "ADT: Shrink size of SmallVector by 8B on 64-bit platforms" adds ed6266d5795 [WebAssembly] Disable a test that violates DR1696 adds 40d8d2b15d4 Revert "[docs] Add support for Markdown documentation in Sphinx" adds 604b45ddcfd Reapply "ADT: Shrink size of SmallVector by 8B on 64-bit pl [...] adds 2bbe26162ea [DAGCombiner] Fold X - (-Y *Z) -> X + (Y * Z) adds 14b97bb6303 Add x86_64-unkown triple to llc for x86 test. adds 8d6095aa061 [AArch64][SVE] Asm: Support for FTMAD instruction. adds f5878e6b347 [AArch64][SVE] Asm: Support for bit/byte reverse operations. adds 06b493f7f03 Reapply "AMDGPU: Fix handling of alignment padding in DAG a [...] adds f638e5271d8 Improved sched model for X86 BSWAP* instrs. Differential Re [...] adds 8c93523c814 [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/Read [...] adds 9bdae65513e [UBSan] Also use blacklist for 'Address; Undefined' setting adds 16429798515 Revert "[LSV] Refactoring + supporting bitcasts to a type o [...] adds b15f0ae4d4f [SystemZ] Test case formatting fixes adds 3876c1deaef [NFC][testcases] more testcases for folding srem if its two [...] adds e53157e9ebc [DebugInfo] Generate .debug_names section when it makes sense adds da67c6d0eff [InstSimplify] fold srem instruction if its two operands ar [...] adds 077efdaae0c Regenerate remainder test. adds ca4d424e2e6 [X86][AVX] Convert X86ISD::VBROADCAST demanded elts combine [...] adds 1ba71c6ab7a Recommit r328307: [IPSCCP] Use constant range information f [...] adds 60fb40346bf [NFC][testcases] fold sdiv if two operands are negated and [...] adds 6dde8495c07 Regenerate partial vector fold test. NFCI. adds 59b3465a59e [IPSCCP] Fix for bot failure caused by r337548 adds 7b7da9f3c10 [X86][AVX] Add 256-bit vector horizontal op redundant shuff [...] adds d5c8d8bb016 [DAG] Fix Memory ordering check in ReduceLoadOpStore. adds 09babe53b1d [X86][AVX] Add support for 32/64 bits 256-bit vector horizo [...] adds cb80e4d222b DwarfDebug: Reduce duplication in addAccel*** methods adds 708378d3558 [DAG] Avoid Node Update assertion due to AND simplification adds bb7c99a9c22 Fix build breakage from r337562 adds 0ec1f16b4e3 [X86][AVX] Add v16i16 horizontal op redundant shuffle tests adds 42411242d60 [X86][AVX] Add support for i16 256-bit vector horizontal op [...] adds 7ba70e88cc0 [llvm-objcopy, tests] Fix several llvm-objcopy tests adds 8ec2a959fa2 [X86][SSE] Use SplitOpsAndApply to improve HADD/HSUB lowering adds 7d86834e82c [MSan] run materializeChecks() before materializeStores() adds f51ced79104 Rewrite the VS integration scripts. adds cd6f3910e90 Add llvm::Any. adds 6649de34e98 [ARM] Add new feature to enable optimizing the VFP registers adds ee762a8b97e Change bool_constant to integral_constant. adds 86a77cda68e [MSan] Hotfix compilation adds 354367414b3 [X86][XOP] Fix SUB constant folding for VPSHA/VPSHL shift lowering adds c2a416a076b [MemorySSA] Add API to update MemoryPhis, following CFG changes. adds 3dac3fac6c9 [Any] Fix a typo: didn't use the correct argument adds 42e40ea33ee Add a Microsoft Demangler. adds 7d1ac03f353 [llvm-mca][x86] Add movsx/movzx instructions to general x86 [...] adds 32922e691b8 Fix linker failure with Any. adds a7a130cbf71 [X86] Remove what appear to be unnecessary uses of DCI.CombineTo adds 34f6b250b3e [X86] Remove isel patterns for MOVSS/MOVSD ISD opcodes with [...] adds aeb65f137ae Fix a few warnings and style issues in MS demangler. adds 70215f556ff [Demangler] Add missing overrides adds cea401e58a5 [ORC] Replace SymbolResolvers in the new ORC layers with se [...] adds ec3e95710f4 [ORC] Simplify VSO::lookupFlags to return the flags map. adds 7891d706dae [ORC] Add new symbol lookup methods to ExecutionSessionBase [...] adds 3dd57df1d16 [Demangler] Correctly factor in assignment when allocating. adds 5f6eec8ceb9 Make check-llvm depend on llvm-undname adds bc0cffa673a Remove a superfluous semicolon adds 502e1bf6141 And add a lit substitution for llvm-undname, as the comment [...] adds ff83113c2f5 [llvm-objcopy] Add basic support for --rename-section adds a46c1d6b583 [FileCheck] Fix search ranges for DAG-NOT-DAG adds 6bb56ed1173 Reapply "[LSV] Refactoring + supporting bitcasts to a type [...] adds 1f565f54cd4 Revert r337595 "[ORC] Add new symbol lookup methods to Exec [...] adds 4571da68d10 [FileCheck] Provide an option for FileCheck to dump origina [...] adds 3631b664083 [COFF] Adjust how we flag weak externals adds 337fc79e64d [COFF] Use symbolic constants instead of hardcoded numbers. NFCI. adds 9f7b7482cbb [llvm-undname] Remove a superfluous semicolon. NFC. adds a69ec545d20 Revert "[X86][AVX] Convert X86ISD::VBROADCAST demanded elts [...] adds 8f2b72e7d1b AMDGPU: Use existing function to check for VGPRs adds 43c7ac58945 Change the cap on the amount of padding for each vtable to [...] adds 15f33310a86 [Hexagon] Disable packets in test to avoid ordering issues [...] adds c53ade08d70 [ADT] Only run death tests in !NDEBUG adds 845fa153ca1 Re-apply r337595 with fix for LLVM_ENABLE_THREADS=Off. adds 9d8e9ef4914 [ORC] Re-apply r336760 with fixes. adds 1d13545e10c [DebugInfo] Add a new DI flag to record if a C++ record is [...] adds ebc7653063d [InstrSimplify] fold sdiv if two operands are negated and n [...] adds ed64ebdb3f6 Early exit with cheaper checks adds 0754d77d6ad Fix the MSVC Visualizers for SmallVector classes. adds 322f6d046b0 [llvm-undname] Flush output before demangling. adds d0914d174ca [mips] Move out the WrapperPat declaration from the NotInMi [...] adds 7d957555181 [mips] Factor out register class selection for global base [...] adds bdf2ac006fb [llvm-mca][docs] Add documentation for the statistic output [...] adds bd64674cdec [X86] Add more MADD recurrence test cases with larger and n [...] adds 8c41af6002b [SelectionDAGBuilder] Restrict vector reduction check to ty [...] adds 7a0e9e5b054 [SelectionDAGBuilder] Use APInt::isZero instead of comparin [...] adds a747d6134aa [ORE] Move loop invariant ORE checks outside the PM loop. adds 13ee34b3354 [X86] Remove the max vector width restriction from combineL [...] adds c6b3cc723aa Test commit, fix a minor typo. adds 32b278468b1 [x86/SLH] Rename and comment the main hardening function. NFC. adds 9e30933ab10 [x86/SLH] Add a test covering indirect forms of control flow. NFC. adds d0f4fb1b00c [x86/SLH] Fix a bug where we would harden tail calls twice [...] adds dbf6cfb47d5 [GVNHoist] safeToHoistLdSt allows illegal hoisting adds e3427c2f095 [NFC][MCA] ZnVer1: add partial-reg-update tests adds 7fdea0d4185 [NFC][MCA] ZnVer1: Update RegisterFile to identify false de [...] adds ef8ab912b61 [Support] Add a UniqueStringSaver: like StringSaver, but de [...] adds 40f8300dd17 [MemorySSAUpdater] Update Phi operands after trivial Phi el [...] adds 576662c3d6b [GVN] Don't use the eliminated load as an available value i [...] adds 942fbb23308 [ARM] ARMCodeGenPrepare backend pass adds e1487414326 [Docs] Fix LLVM_YAML_IS_DOCUMENT_LIST_VECTOR adds fabe54b1977 [FPEnv] Legalize double width StrictFP vector operations adds f1a7318d1a2 [SystemZ] Fix dumpSU() method in SystemZHazardRecognizer. adds 65db7c5dccb [ARM][NFC] ParallelDSP reorganisation adds 7a4d8f6dc1a [mips] Add more checks to the tls.ll test case. NFC adds eac6487bf2a [Legalize] Elide MERGE_VALUES created by scalarizeVectorLoad. adds 524f8982b85 [ARM] Add doFinalization() to ARMCodeGenPrepare pass. adds ad863f56576 [ARM] Follow-up to r337709. adds 2741a66921e OpChain has subclasses, so add a virtual destructor. adds 83862fefd9a [ARM] Use unique_ptr to fix memory leak introduced in r337701 adds 7550101af9b [lit] Move the shtest-xunit-output check lines into shtest-format adds c250bf82878 Fixing a typo; NFC. adds 7bf2466873c [Demangle] Attempt to fix arena memory leak adds 6884c73229b [Hexagon] Handle unnamed globals in HexagonConstExpr adds f3f578d2866 [yaml2obj] Add default sh_entsize for dynamic sections adds 3acc5604543 [docs] Add support for Markdown documentation in Sphinx adds d24baad0e0e Revert "[docs] Add support for Markdown documentation in Sphinx" adds 8454ad66268 Add inline asm aliasing test. adds 820d48f45c6 Fix RegScavenger::unprocess adds e6aaf315db3 [llvm-mca][docs] Define IPC where it is first mentioned. NFC. adds d3db945575b Re-land r335297 "[X86] Implement more of x86-64 large and m [...] adds 7321ba268a1 ConstantFolding: Avoid a crash. adds 94363b3cf67 [gdb] Fix SmallVector pretty printer after r337514 adds 4f40986a056 [DebugCounters] Keep track of total counts adds 2f14f1125a7 [ThinLTO] Ensure the TargetLibraryInfo is constructed early enough adds 113fd07750c [SelectionDAG] Reduce DanglingDebugInfo memory traffic, NFC adds 217be219024 [utils] Fix the llvm::Optional data formatter adds 09465e9be5f [AArch64] Use MCAsmInfoMicrosoft and MCAsmInfoGNUCOFF as ba [...] adds c819c64d039 [COFF] Fix assembly output of comdat sections without an at [...] adds ae3e2f02439 [MC] Add a separate flag for skipping comdat constant secti [...] adds faddb71dd9f [demangler] call terminate() if allocation failed adds 073f01b8db4 [LTO] Handle __imp_ (dllimport) symbols consistently with lld adds 3e597f45e6c [DWARF v5] Refactor range lists dumping by using a more gen [...] adds 2d6fb152e57 Embed a template specialization in a namespace to work arou [...] adds 55b2a35d066 Fix typo in test/CodeGen/Mips/dins.ll adds 6ee94ea43df [DWARF] Use deque in place of SmallVector to fix use-after- [...] adds 3813cf4b746 [x86/SLH] Remove complex SHRX-based post-load hardening. adds ae41ebb3a69 [x86/SLH] Simplify the code for hardening a loaded value. NFC. adds a4afd1f12d5 [Debugify] Move interface definitions to a header, NFC adds 499e3df2ce6 [Debugify] Export per-pass debug info loss statistics adds c4c8d7b1655 Add PerfJITEventListener for perf profiling support. adds 031045ec8db AMDGPU/GlobalISel: Remove unnecessary legality constraint f [...] adds 46356154bf7 llvm-xray: Broken chrome trace event format output adds 6779fccada2 AMDGPU/GlobalISel: Legalize G_INSERT adds b454fa1b407 [DebugInfo] Generate DWARF debug information for labels. adds 6eec3c8253d [x86] Update the CHECK lines of this test to use the latest [...] adds b79cc9e7eb3 [x86] Clean up and convert test to use generated CHECK lines. adds 35ffbe6bcf3 Revert "[DebugInfo] Generate DWARF debug information for labels." adds f2cead440d9 Recommit r334887: [SmallSet] Add SmallSetIterator. adds d61e7c72367 ADT: Shrink SmallVector size 0 to 16B on 64-bit platforms adds 99421a402fb [ARM] Disable ARMCodeGenPrepare by default adds 0cb06771b3b [x86/SLH] Tidy up a comment, using doxygen structure and wo [...] adds ab7df71889e [x86/SLH] Extract the core register hardening logic to a lo [...] adds dab9d81b7c2 [mips] Fix local dynamic TLS with Sym64 adds ae8e83e5e72 [PredicateInfo] Use custom mangling to support ssa_copy wit [...] adds cef24f0d3b7 Use SCEV to avoid inserting some bounds checks. adds f381561a76c [MachineOutliner][NFC] Sink some candidate logic into Outli [...] adds 6f78ca4aa02 [MachineOutliner][NFC] Move missed opt remark into its own [...] adds 264d8038e84 [MachineOutliner][NFC] Make Candidates own their call information adds 3e6b79abab2 [docker] Fix LLVM_EXTERNAL_PROJECTS cmake variable value adds a3de0cbb8f4 [X86] Add test case to show failure to combine away negates [...] adds e944ca86b15 [Inliner] Teach inliner to merge 'min-legal-vector-width' f [...] adds f48b4d01aaa [x86] Teach the x86 backend that it can fold between TCRETU [...] adds 5df3f9e0708 Put "built-in" function definitions in global Used list, fo [...] adds 742c37184cc [MachineOutliner][NFC] Move target frame info into Outlined [...] adds e38c32aa3b4 [MachineOutliner][NFC] Move outlined function remark into i [...] adds bd6cf0e2e7a [X86] Change multiply by 19 to use (9 * X) * 2 + X instead [...] adds 15bfd7a6941 [WebAssembly] Add tests for weaker memory consistency orderings adds 89b692c8285 [X86] Generalize the multiply by 30 lowering to generic mul [...] adds a783e1fbc23 [X86] When expanding a multiply by a negative of one less t [...] adds 78dd298f340 [SCEV] Add zext(C + x + ...) -> D + zext(C-D + x + ...)<nuw [...] adds 222b8becdda [LV] Fix for PR38110, LV encountered llvm_unreachable() adds e2033feaa49 [X86] Change multiply by 26 to use two multiplies by 5 and [...] adds a1d740bf957 [X86] Add test cases for multiply by 37, 41, and 73. adds 7cc443c91a5 [X86] Use a two lea sequence for multiply by 37, 41, and 73. adds d277be2a297 [X86] Expand mul by pow2 + 2 using a shift and two adds sim [...] adds 0bca0d9f065 [X86] Use a shift plus an lea for multiplying by a constant [...] adds 9416121005f [x86/SLH] Teach the x86 speculative load hardening pass to [...] adds bce5b55ff31 [profile] Support profiling runtime on Fuchsia adds fc5040103f2 [RegisterBankInfo] Ignore InstrMappings that create impossi [...] adds 2f4f56849c8 [X86] Autogenerate complete checks and fix a failure introd [...] adds 434ff8b75b9 [X86] Use X86ISD::MUL_IMM instead of ISD::MUL for multiply [...] adds a23be0643b8 [Dominators] Assert if there is modification to DelBB while [...] adds f9c35fb62e2 [mips] Replace custom parsing logic for data directives by [...] adds cc954f3fcb3 [x86/SLH] Improve name and comments for the main hardening [...] adds b5ba78c96b1 [x86/SLH] Sink the return hardening into the main block-wal [...] adds cac968ea784 [llvm-readobj] Generic hex-dump option adds 05d358bad52 [llvm-objdump] Add dynamic section printing to private-head [...] adds ac1626ec4dd Fix PR34170: Crash on inline asm with 64bit output in 32bit GPR adds 413e39f9df1 Recommit r333268: [IPSCCP] Use PredicateInfo to propagate f [...] adds f5b8d1cf394 [SystemZ] Use tablegen loops in SchedModels adds b1674d0d93b dwarfgen: Add support for generating the debug_str_offsets section adds 3de71f627ed [MIPS GlobalISel] Lower pointer arguments adds a47b5f6ca0a Revert "dwarfgen: Add support for generating the debug_str_ [...] adds 6a84cfbab18 Move JIT listener C binding fallbackks to ExecutionEngineBi [...] adds 030afdf934a dwarfgen: Add support for generating the debug_str_offsets [...] adds a9364fc1850 [Hexagon] Properly scale bit index when extracting elements [...] adds a70431e931a Revert "dwarfgen: Add support for generating the debug_str_ [...] adds 07e41a65933 Fix llvm::ComputeNumSignBits with some operations and llvm.assume adds a31192b5376 [AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion adds d1f49bb39a2 Fix corruption of result number in LegalizeVectorOps.cpp adds 8544cc867df Add an option to specify the name of an function whose CFG [...] adds 4f30db4325f [windows] Don't inline fieldFromInstruction on Windows adds d844c8fc2cb [SCEV] Add [zs]ext{C,+,x} -> (D + [zs]ext{C-D,+,x})<nuw><ns [...] adds 999d8967886 [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1. adds 25eb40c0141 [LangRef] Clarify undefined behavior for function attributes. adds a81fbf2f94c [COFF] Hoist constant pool handling from X86AsmPrinter into [...] adds f2f6b9cfe05 [COFF] Use comdat shared constants for MinGW as well adds 4ed456cbf1c Add missing 'override', fixing compilation with some compil [...] adds 95ba9814e6d Revert r337904: [IPSCCP] Use PredicateInfo to propagate fac [...] adds fab866fa9c2 [GlobalMerge] Allow merging globals with arbitrary alignment. adds d73322deb3b [AArch, PowerPC] add more tests for legal rotate ops; NFC adds 406c0440c5f [LSV] Look through selects for consecutive addresses adds 2b264247a9d [SelectionDAG] try to convert funnel shift directly to rota [...] adds 261e479ae9e [GlobalMerge] Handle llvm.compiler.used correctly. adds 596b78875d4 bpf: new option -bpf-expand-memcpy-in-order to expand memcp [...] adds 7c767bd7868 [dsymutil] Add support for generating DWARF5 accelerator tables. adds 327eaad5f0c [DWARF v5] Don't emit multiple DW_AT_rnglists_base attribut [...] adds 12c27f5b539 [MCA] Avoid an InstrDesc copy in mca::LSUnit::reserve. adds ee571f2b410 CodeGen: Cleanup regmask construction; NFC adds b94181c027c InitializePasses: Sort declarations; NFC adds 663f587f45b CodeGen.cpp: Sort initializers; NFC adds 3a7b5a66665 RegUsageInfo: Cleanup; NFC adds 77618f2a517 [LoadStoreVectorizer] Use const reference adds 7bfb55f7a4d [DWARF v5] Don't report an error when the .debug_rnglists s [...] adds a145774c76e [GlobalISel] Fall back to SDISel for swifterror/swiftself a [...] adds f4c9d7c0dc4 [Support] Introduce createStringError helper function adds cbe902c02cc [X86] Remove some unnecessary explicit calls to DCI.AddToWorkList. adds aaa4c838e96 Revert r337981: it breaks the debuginfo-tests adds 00c4d032c89 [Docs] Update of Xray page adds 1726a8cfd34 [X86] Don't use CombineTo to skip adding new nodes to the D [...] adds f96e99c4f0d [AsmParser] Fix preserve-comments-crlf.s on FreeBSD adds 1ba2ba3af88 [ConstProp] Fix calls-math-finite.ll on FreeBSD adds fcfe10d3d0a [AArch64] Armv8.2-A: add the crypto extensions adds 7b3bfc8151f [AArch64][NFC] Removed tab characters from test files. adds 65b1f6fe0ac Allow users of the GCOV API to extend the FileInfo class to [...] adds 9c2cf1492d7 [test] Do dsymutil update in place adds a0882e9c6c7 [x86/SLH] Extract the logic to trace predicate state throug [...] adds 078cc9c528c Revert "[COFF] Use comdat shared constants for MinGW as well" adds 4f48c840d00 [mips] Sign extend i32 return values on MIPS64 adds 99cfb5c8a74 dwarfgen: Don't create an AsmPrinter with an invalid ObjFil [...] adds 6678e03e560 Fix raw_fd_ostream::write_impl hang with large output adds cb0c8af1cb8 Enable some pointer authentication instructions for aarch64 [...] adds 4dcaa89c887 [test] Disable dsymutil update test on windows adds bffd929d5b0 dwarfgen: Add support for generating the debug_str_offsets [...] adds 0b19d8a7b1d [UnJ] Common some code. NFC adds 6069e66e2ca [ADT] Replace std::isprint by llvm::isPrint. adds ec700d4f8fc Revert r338027 to pacify build bot adds 3615fab87ed [DEBUGINFO, NVPTX] Set `DW_AT_frame_base` to `DW_OP_call_fr [...] adds da3868db1ab [InstCombine] add tests for udiv with common factor; NFC adds 01c573fe17b [DEBUGINFO, NVPTX] Emit correct debug information for local [...] adds 24c0aa9af62 [DAGCombine] optimizeSetCCOfSignedTruncationCheck(): handle [...] adds 8aa95af9e5c MacroFusion: Fix macro fusion with ExitSU failing in top-do [...] adds 23f8b780224 [RISCV] Add support for _interrupt attribute adds ededc9899f1 [InstCombine] fold udiv with common factor from muls with nuw adds 7531be0d757 [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits adds 3c58d5b196e [MS Demangler] Demangle data member pointers. adds 1028e2499b5 Handle the lack of a symbol table correctly. adds 70e518f5234 [MC] Add support for the .rva assembler directive for COFF targets adds d4bb30eca16 [MS Demangler] Demangle pointers to member functions. adds 3a62886fee0 Add missing tests from ms-mangle.cpp. adds eedd47c7f5a [MS Demangler] Add ms-arg-qualifiers.test adds c2403ba5de8 [MS Demangler] Print calling convention inside parentheses. adds 081d211981d [DebugInfo] LowerDbgDeclare: Add derefs when handling CallI [...] adds 8818f00dd61 [RegisterCoalescer] Fixed inconsistent followCopyChain with subreg adds 235b4df870a ADT: Document advantages of SmallVector<T,0> over std::vector adds db695a11d79 [SCEV] Add an expandAddToGEP overload for a single operand. NFC. adds 3cb83a57794 [SCEV] Don't expand Wrap predicate using inttoptr in ni addrspaces adds c20481951cf [MS Demangler] Properly handle function parameter back-refs. adds fa36b7f50db Fix -Wsign-compare warning. adds afc6e834feb [DAGCombiner] Remove some calls to AddToWorklist that shoul [...] adds c91e9d7b377 [SelectionDAG] Add MLOAD/MSTORE/MGATHER/MSCATTER to AddNode [...] adds c0e32a59eda [DWARF v5] Reposting r337981, which was reverted in r337997 [...] adds aeb706baf5a [InstrProf] Use comdats on COFF for available_externally functions adds 1393b8f6d79 [SelectionDAGBuilder] Add masked loads to PendingLoads rath [...] adds 8049eb58063 [X86] When removing sign extends from gather/scatter indice [...] adds 976b9f9f2df [InstCombine] canonicalize abs pattern Differential Revisio [...] adds ae832cbb544 [X86] Add matching for another pattern of PMADDWD. adds 01a1fe5ce8b Replace LLVM_ALIGNAS with alignas as a follow-up of r337330 adds 10a832fe97f [LTO] Don't internalize declarations adds 949469ba7e5 [X86] Remove an unnecessary 'if' that prevented treating IN [...] adds 6dce5ed08b2 AMDGPU/GlobalISel: Fix crash in regbankselect on non-power- [...] adds f44aafb1ce1 [NFC] Remove an empty line. adds 07cbe1baa39 [Docs] Remove hard tab character from code block in optbise [...] adds 951194fd1c4 [LV][DebugInfo] Set DL to the middle block Icmp instruction adds 7eb8348d106 [InstSimplify] tests for D48828: fold extraction from std::pair adds e4b83127155 Revert "[LV][DebugInfo] Set DL to the middle block Icmp ins [...] adds ffc1a1ca6a1 PatternMatch: Add wrappers for fabs and canonicalize adds f3b5d6dfcf8 DAG: Remove unnecessary .str() adds e9c22aa83fd AMDGPU: Fix code size for return_to_epilog pseudo adds ef4fb1985c1 [Support] Bring std::errc::not_supported to llvm::errc. adds 9c24b380dc0 [SimplifyIndVar] Canonicalize comparisons to unsigned while [...] adds 9ac57f95b0b [InstCombine] add tests for not+sub; NFC adds 4582fbe0624 [InstCombine] not(sub X, Y) --> add (not X), Y adds cbda3f80430 [CMake] Followup for r337366: Only export LLVM_LINK_LLVM_DY [...] adds ed46696aff3 [AArch64][SVE] Asm: Support for FRECPE and FRSQRTE. adds 275c00cc764 [AArch64][SVE] Asm: Support for FEXPA and FTSSEL. adds 26a258012a9 [AArch64][SVE] Asm: Predicated floating point reductions. adds e2d5b7575fd [AMDGPU][MC][DOC] Updated AMD GPU assembler description adds addbabf0a80 [AArch64][SVE] Asm: Predicated integer reductions. adds 0a1753ac2dd AMDGPU/R600: Add MOV instructions to BFE patterns adds 13b09222ff2 [Support] Use unsigned char for xxHash 64-bit adds b9dee6e2c28 [AArch64] add more tests for signbit math; NFC adds 67980f703ba [PowerPC] add more tests for signbit math; NFC adds a0c25fcea2b [x86] add more tests for signbit math; NFC adds 125191a9e0c [DAGCombiner] fold 'not' with signbit math adds 6f446a56af7 Enable MachineOutliner by default under -Oz for AArch64 adds 767b5de4f4a bpf: add missing RegState to notify MachineInstr verifier n [...] adds f25070cb8b0 Revert "Enable MachineOutliner by default under -Oz for AArch64" adds 4d940e78155 [demangler] Support for reference collapsing adds fac43a31235 [AArch64, PowerPC, x86] add more signbit math tests; NFC adds dd4e083abf3 [ARM] Add new target feature to fuse literal generation adds 4ec15997d0a [MachineOutliner] Exit getOutliningCandidateInfo when we er [...] adds c9159350aee [AArch64, PowerPC, x86] add more signbit math tests; NFC adds ea66136bc88 [SLC] Test simplification of pow(x, 0.333...) to cbrt(x) (NFC) adds 8ab74e6b402 [InstCombine] [NFC] [Tests] Fold Select with AND/OR condition adds 031332e7888 Recommit "Enable MachineOutliner by default under -Oz for AArch64" adds 4cca12faa69 [InstCombine] [NFC] [Tests] Fold Select with AND/OR conditi [...] adds cc0c5b9ce0d [WebAssembly] Added default stack-only instruction mode for MC. adds b6a0f6b8e00 [InstrProf] Don't register __llvm_profile_runtime_user adds 2ccd4fbdb9c [llvm-objcopy] Make --strip-debug strip .zdebug* (zlib-gnu) [...] adds 7d3adcd95a0 [X86] Add support expanding multiplies by constant where th [...] adds 134080471cd [Support] Remove unnecessary MemoryBuffer::anchor (where th [...] adds bbe055241a2 Revert "[WebAssembly] Added default stack-only instruction [...] adds e593ad899af [SimpleLoopUnswitch] Fix DT updates for trivial branch unsw [...] adds fefdba1e17f [DAGCombiner] Teach DAG combiner that A-(B-C) can be folded [...] adds 17313457855 [docs] Clarify role of DIExpressions within debug intrinsics adds e061215a7e5 [Dominators] Make applyUpdate's documentation less confusing [NFC] adds 840922e2b4a [demangler] Fix an oss-fuzz bug from r338138 adds cf073c23aa2 [InstCombine] Fold Select with AND/OR condition adds d38f49543ed [GlobalOpt] Test array indices inside structs for out-of-bo [...] adds 3d794576ede AMDGPU: Stop trying to extend arguments for clover adds f02d879e99f DAG: Add calling convention argument to calling convention funcs adds 6f476979f90 [InstSimplify] Moved Select + AND/OR tests from InstCombine adds 8a22271900d [AArch64][SVE] Asm: Data-dependent loop predicate partition [...] adds c358be353a3 AMDGPU: Stop wasting argument registers with v3i32/v3f32 adds 234c23e0a02 [AArch64][SVE] Asm: Support for PFALSE and PTEST instructions. adds bd68890e8f0 [InstCombine] try to fold 'sub' to 'not' adds 8a20db36739 [InstCombine] Tests for fold Select with binary op adds 52b10b8b07e Add VS natvis support for LLVMDemangle's StringView. adds b03e51dff43 [X86] Use alignTo and divideCeil to make some code more rea [...] adds e192af49a17 [X86] Correct the immediate cost for 'add/sub i64 %x, 0x80000000'. adds acb4985d700 [SelectionDAG] Pass std::vector by reference instead of by [...] adds 789dd7b8055 Fix crash on inline asm with 64bit matching input in 32bit GPR adds 71650da2ad2 [MS Demangler] Refactor some of the name parsing code. adds 32d3bbcc6c7 [AArch64][SVE] Asm: Instructions to perform serialized operations. adds 11c523d2b15 [AArch64][SVE] Asm: Support for WHILE(LE|LO|LS|LT) instructions. adds ebd090bd41e [AVR] Re-enable expansion of ADDE/ADDC/SUBE/SUBC in ISel adds 04eda8fb6f1 revert r338206 because the test does not pass adds 769bf94359c [InstSimplify] refactor intrinsic simplifications; NFCI adds 58d4a39f630 [dsymutil] Simplify temporary file handling. adds c817c924d52 [InstSimplify] add tests for funnel shift intrinsics; NFC adds 5c9b7b9b828 [InstSimplify] fold funnel shifts with 0-shift amount adds 866b9e6fe19 [MS Demangler] NFC - Remove state from Demangler class. adds 02b53da6b65 [InstCombine] add tests for another sub-not variant; NFC adds 19a2e2a495f [InstCombine] try to fold 'add+sub' to 'not+add' adds 28b397746c3 [DAGCombiner] Remove unnecessary calls to AddToWorklist. adds c84f7e82fc4 [MS Demangler] Demangle symbols in function scopes. adds 5240109d473 Try to fix build. adds ef9e348db2a [NFC] Prepare GuardWidening for widening of cond branches adds ec18b801a33 [RegisterScavenger] Fix debug print adds dc8a4c5d74e [ARM] Fix over-alignment in arguments that are HA of 128-bi [...] adds bfada8913e3 AMDGPU: Force skip over s_sendmsg and exp instructions adds 6476cb62059 Revert "[X86] Correct the immediate cost for 'add/sub i64 % [...] adds 8c6201cde53 [MachineOutliner][X86] Use TAILJMPd64 instead of JMP_1 for [...] adds 7ca84ad7ea6 [GVNHoist] Re-enable GVNHoist by default adds df2b9399fe9 [BasicAA] Use PhiValuesAnalysis if available when handling [...] adds 86dcb58e5df AMDGPU: Make fneg combine handle fcanonicalize adds 78e0f474878 AMDGPU: Reduce code size with fcanonicalize (fneg x) adds 86e834abd60 Adjust opt pass pipeline tests to cope with combination of [...] adds 2618edfa4ca [Hexagon] Simplify A4_rcmp[n]eqi R, 0 adds aee71c080d5 [doc] Fix Getting Started typo. adds b8b1cb30e78 [InstCombine] [NFC] Added tests for Select with binop fold adds c80d03aba54 [AArch64][SVE] Asm: Add MOVPRFX instructions. adds d0973b1cc35 [AArch64][SVE] Asm: Enable instructions to be prefixed. adds 8a876198f4a [X86] Regenerate fast-isel tests. adds cd2281d9372 [X86] Regenerate PKU test to merge 32/64-bit rdpkru checks adds 68c3d4fad41 [X86] Regenerate NOBMI/BMI combine-select tests. adds fb73e7ba915 [SLC] Refactor the simplication of pow() (NFC) adds 1453140bcb1 Attempt to fix Windows test failure caused by r338133 adds 690afef84f0 Fix uninitialized read in ARM's PrintAsmOperand adds 005ad0240a6 Reapply "Fix crash on inline asm with 64bit matching input [...] adds 44dc58d645c [DAGCombiner] Bug 31275- Extract a shift from a constant mu [...] adds e1239522278 Add machine verifier to arm64-opt-remarks-lazy-bfi adds 63006f4c992 Recommit r338204 "[X86] Correct the immediate cost for 'add [...] adds 45a1b043b06 [X86] Fix typo in comment. NFC adds 54b04a891a5 [MachineOutliner][AArch64] Add support for saving LR to a register adds 7e678dc65bb [InstSimplify] [NFC] Tests for Select with AND/OR fold adds b22576f80da [Inline] Copy "null-pointer-is-valid" attribute in caller. adds af7b1832a03 Remove trailing space adds aec199b9d76 Revert "[GVNHoist] Re-enable GVNHoist by default" adds 3e5ff188671 Revert r338222 "[DAGCombiner] Remove unnecessary calls to A [...] adds a5603d18b0a [InstCombine] Fold Select with binary op adds f264341a831 [DAGCombiner][PowerPC][AArch64] Pass Created vector by refe [...] adds e9f23bb5b17 [TargetLowering] In BuildSDIV, add the MULHS/SMUL_LOHI to t [...] adds 865d24fcb44 [ORC] Add SerializationTraits for std::set and std::map. adds 1715f28483f This fixes a crash when a second pass is required for the C [...] adds 00f1a051eff [VPlan] Introduce VPlan-based dominator analysis. adds 648b708c20e [DAGCombiner] transform sub-of-shifted-signbit to add adds d08e6c74a6f [llvm-mca][docs] Add instruction flow documentation. NFC. adds ef4200131b9 [MS Demangler] Add rudimentary C++11 Support adds 4a5776cc933 [DAGCombiner][TargetLowering] Pass a SmallVector instead of [...] adds cbb0dfe533d [MS Demangler] Add ms-return-qualifiers.test. adds be764dbd779 [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockad [...] adds 58ce02a3b60 [AArch64][GlobalISel] Make G_BLOCK_ADDR legal. adds a422671937f [AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR. adds e558f30bfb2 [MS Demangler] Better demangling of template arguments. adds f7d1ac1d98f [RISCV] Fixed test case failure due to r338047 adds 816cd634769 [X86] Stop accidentally running the Bonnell LEA fixup path [...] adds 41daa756aa8 Revert r338340 "[MS Demangler] Better demangling of templat [...] adds b2970fad9bf [VPlan] Introduce VPLoopInfo analysis. adds 8b661d1f712 [NFC] Collect statistics in GuardWidening adds 24f705031bf [InstSimplify] tests for D48828, D49981: fold extraction fr [...] adds 9325cc92edd [InstSimplify] tests for D48828, D49981: fold extraction fr [...] adds d8319b3d669 Test commit. adds a52192cab50 [ARM] Revert r337821 adds 90e3e8259bc [AArch64] Support the .inst directive for MachO and COFF targets adds 4c60168fd23 [ARM] Support the .inst directive for MachO and COFF targets adds c5db03f3384 [ARM] Allow automatically deducing the thumb instruction si [...] adds 05daff0b996 [X86][SSE] isFNEG - Use getTargetConstantBitsFromNode to ha [...] adds b2deef92d96 [X86] Improved sched models for X86 SHLD/SHRD* instructions [...] adds f8c29cb84b8 [InstCombine] move/add tests for xor+add fold; NFC adds b80d74e072c [X86] Improved sched models for X86 BT*rr instructions. htt [...] adds 44442fbe1a2 [InstCombine] simplify code for A & (A ^ B) --> A & ~B adds 6108c027cf8 [SystemZ] Improve decoding in case of instructions with fou [...] adds 947573c21d9 Revert r338365: [X86] Improved sched models for X86 BT*rr i [...] adds 0915eb50a32 [ELF][ARM] Add Arm ABI names for float ABI ELF Header flags adds e4002873382 [llvm-mca][BtVer2] Teach how to identify dependency-breakin [...] adds 07f371fc510 [ARM] Complete enumeration values for Tag_ABI_VFP_args adds 8d00765ed12 AMDGPU: Fix test check line bugs adds 8f44f41e0f3 AMDGPU: Fold undef fcanonicalize to qNaN adds 1ae9ed698a7 [SLP] Fix PR38339: Instruction does not dominate all uses! adds 55c7db8b2ea AMDGPU: Don't handle FP16_TO_FP in isCanonicalized adds 48e2f473006 DAG: Fix PromoteFloatResult for fcanonicalize adds f241788fa53 [InstSimplify] Fold another Select with And/Or pattern adds 9e1f67df4fc [MemDep] Use PhiValuesAnalysis to improve alias analysis results adds 8838d03a84a [llvm-mca] Remove README.txt adds 99862d39d7c Enrich inline messages adds 07836bef1a3 [InstCombine] auto-generate checks; NFC adds 757fc2f38e7 Revert Enrich inline messages adds f03f9e8cd4d [DebugInfo] Generate DWARF debug information for labels. adds c22c96db495 [DebugInfo][LCSSA] Preserve debug location in lcssa phis adds d3bdf1f29b6 [InstCombine] regenerate checks and add tests for D50035; NFC adds c49e38382fc [llvm-mca][docs] Always use `llvm-mca` in place of `MCA`. adds d9904414c21 Fix InstCombine address space assert adds 8f61a2ac041 [Dominators] Make slow walks shorter adds 7eb35db2b9b [DebugInfo] Fix build failed in 'clang-cmake-armv8-full'. adds 150fbb2f391 [X86] Preserve more liveness information in emitStackProbeInline adds f8da0e7688c [X86] Add test cases that could use PMADDUBSW. adds bc59a99d64a [X86] Add pattern matching for PMADDUBSW adds b4a81ed64e5 Resubmit r338340 "[MS Demangler] Better demangling of templ [...] adds 09bfc1d89e1 [llvm-mca][x86] Add 32-bit instruction resource tests adds 2c3c78e685e Make ICF log output order deterministic. adds 31004d79ff2 [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lo [...] adds bee8996fbdf Revert "[DebugInfo] Generate DWARF debug information for labels." adds c122af5f3b2 [llvm-mca][docs] Improve the "How LLVM-MCA works" section. adds efe67ede2a4 [X86] WriteBSWAP sched classes are reg-reg only. adds 8073c6502e4 [llvm-mca][docs] Replace "temporary" with "physical registe [...] adds 0a67b1c905b AMDGPU: Scalarize vector argument types to calls adds a7336f29220 [CodeView] Minimal support for S_UNAMESPACE records adds b9d99ce19e4 AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls adds 4b6157df8bf AMDGPU: Break 64-bit arguments into 32-bit pieces adds 613bccbc84d [CodeView] Add coverage test for r338308 (Fixed crash in ty [...] adds e946b0193e9 DAG: Correct pointer type used for stack slot adds df2a6d7985c [SystemZ] Fix bad assert composition. adds 99802f3deb0 [llvm-mca] Update the help text to reflect "physical" regis [...] adds 2f227c480af Add DebugCounters to DivRemPairs adds fa5ec153c2d AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests adds 7cef9e8fc8a [DWARF] Do not create a .debug_ranges section when no range [...] adds 0da00372337 Revert r338431: "Add DebugCounters to DivRemPairs" adds 402cad06199 [llvm-objcopy] Make --strip-debug strip .gdb_index adds 1c247de5eec [SLC] Refactor the simplication of pow() (NFC) adds 9a8677da0d7 [DWARF] Support for .debug_addr (consumer) adds fc3a3b78d41 [WebAssembly] Fix debug info tests after r338437. adds 1fa19f68007 Revert r338354 "[ARM] Revert r337821" adds 6baa465afec [PATCH] [SLC] Test simplification of pow() for vector types (NFC) adds a3904966ff8 [MachineOutliner] Clean up subtarget handling. adds bf9b77d2fac Tidy up logic around unique section name creation and remov [...] adds 5311a6ea832 Simplify selectELFSectionForGlobal by pulling out the entry [...] adds b47f061f5bb AMDGPU: Add clamp bit to dot intrinsics adds 59a658d8e21 [GlobalISel][IRTranslator] Use RPO traversal when visiting [...] adds 2bdc8dd491b [DebugInfo] Generate fixups as emitting DWARF .debug_line. adds 2dead59c8f0 [x86/slh] Add unwind info to several tests to make it more [...] adds 2671ee17f9d [x86] Fix a really subtle miscompile due to a somewhat glar [...] adds 3472a740824 [X86] Adding more test patterns for lea-opt (PR37939) adds c8a8300f9ab [DebugInfo] Fix build failed in clang-x86_64-linux-selfhost [...] adds d967b3d2e7f [InstSimplify] fold extracting from std::pair (1/2) adds 6f455447cbb [DWARF] Basic support for producing DWARFv5 .debug_addr section adds a79cc075efb [X86] When looking for (CMOV C-1, (ADD (CTTZ X), C), (X != [...] adds 4e7dc16e1cf [AArch64] Disallow the MachO specific .loh directive for windows adds 788bdbbd5c9 Enrich inline messages adds f0efa56f804 Add llvm-rc to LLVM_TOOLCHAIN_TOOLS (PR38386) adds 8e70a95cbce Revert "Enrich inline messages", tests fail adds f4bd4b26895 [MIPS GlobalISel] Select global address adds 86e18055e60 [DebugInfo] Have custom std::reverse_iterator<DWARFDie> adds 3afffc7790f [X86] Improved sched models for X86 BT*rr instructions. Dif [...] adds 4bd72473d80 [DebugInfo] Improve consistency in DWARFDie.h (NFC) adds 122a371c30a [DebugInfo] Remove ambiguity to fix Windows bots adds 7dce6b6631c [llvm-mca] Improve code comments. NFC. adds f09d159b577 [llvm-mca][x86] Add STC + STD instruction resource tests adds c6fbe17b987 [X86] Use isNullConstant helper. NFCI. adds afca5c23cfc [SystemZ, TableGen] Fix shift count handling adds 185957447e5 Fix build bot after r338521 adds a9d3893accd [AMDGPU] Optimize _L image intrinsic to _LZ when lod is zero adds 6c7ea834f85 [MC] Report fatal error for DWARF types for non-ELF object files adds caa9b8f4ab1 Fix "not all control paths return a value" MSVC warning. adds 41514bcef96 [X86] Use isNullConstant helper. NFCI. adds c690a0177e3 [llvm-mca][x86] Add CMPS/LODS/MOVS/STOS string instruction [...] adds 3289ee65825 [dsymutil] Convert recursion in lookForDIEsToKeep into worklist. adds 57bb7d2d705 Bump the trunk version to 8.0.0svn adds 0dcbff2f349 [llvm-mca][x86] Add CLFLUSHOPT instruction resource tests adds 83c5e86709e [AArch64] Fix FCCMP with FP16 operands adds e17bf017767 Clear release notes and update version adds 682f0ada213 [FPEnv] Widen illegal width StrictFP vector operations as needed adds a18a727cde1 [llvm-mca][x86] Add more x86-64 system instruction resource tests adds 97a41801565 [llvm-mca][x86] Add LEA instruction resource tests adds 9a071608670 [llvm-exegesis] Provide a way to handle memory instructions. adds 6260bdfbb97 [ARM] Armv8.2-A FP16 vector intrinsics tests adds 9aed24e38ae AMDGPU: Allow fp32-denormals feature for r600 targets adds 7e1cf4b0c45 [llvm-mca][x86] Add SET/TEST instruction resource tests adds 9e6a27fb0cb [llvm-mca] Correctly update the rank in `Scheduler::select()`. adds 742c679d08b [llvm-objcopy] Add support for --rename-section flags from [...] adds 08b4b50725a [llvm-mca][x86] Add PCLMUL instruction resource tests adds 4619b05f78c [llvm-mca][x86] Add PREFETCHW instruction resource tests adds dc21a6f3288 [NFC][FunctionAttrs] Remove duplication in old/new PM pipeline adds a2d22f73a3f [SelectionDAG] Make binop reduction matcher available to al [...] adds 887eb8d03ab [x86] add tests to show miscompile for funnel shift with we [...] adds 8fe02fad970 [SelectionDAG] fix bug in translating funnel shift with non [...] adds 1bf2ea0a053 [x86] remove stale FIXME note from test; NFC adds 17a47fdd425 [llvm-mca][x86] Add CMPXCHG instruction resource tests adds 41983c4c676 [X86] Assign from a brace initializer to match style guide. NFCI. adds 48d710e2cb4 [X86] FastISel fall back on !absolute_symbol GVs adds a227166d0e1 [NFC] small addendum to r334242, FMF propagation adds 68d8e287995 [MS Demangler] Don't crash as often when demangling. adds 5999ebb85cc [MS Demangler] Properly demangle templated operators. adds 39fff696974 [llvm-undname Add an option to dump back references. adds bf6429d608c AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS adds 6bc30a81e71 [X86] Add test cases for the patterns used by __builtin_ffs. adds 89d0eefc17e [X86] Canonicalize the pattern for __builtin_ffs in a simil [...] adds 0d49c36e8db Try to fix FreeBSD build. adds 83de8211787 [DEBUGINFO] Disable emission of the dwarf sections, but all [...] adds 81f99ce8f5a [WebAssembly] Support for a ternary atomic RMW instruction adds 6446fcd61ad AMDGPU: Partially fix handling of packed amdgpu_ps arguments adds 7943061ff9b AMDGPU: Improve hack for packing conversion ops adds 55a0ed21cd4 [DebugInfo/DWARF] [1/4] De-templatize DWARFUnitSection. NFC adds 2b9857ed4fb [DebugInfo/DWARF] [2/4] Type units no longer in a std::deque. NFC adds bc7a6422c5d AMDGPU: Use SPseudoInst helper adds 72eb9b0a58f [DebugInfo/DWARF] [3/4] Rename DWARFUnitSection to DWARFUni [...] adds a42866d162e [DebugInfo/DWARF] [4/4] Unify handling of compile and type [...] adds de10da00241 [llvm-objcopy] Add missing -I command line flag alias for - [...] adds 27222373998 [ORC] Add a 'Callable' flag to JITSymbolFlags. adds 0318cbc235d [ASAN] Use the correct shadow offset for ASAN on FreeBSD/mips64. adds 886a8633738 Load from the GOT for external symbols in the large, PIC co [...] adds 5ea9eaae861 [InstSimplify] move minnum/maxnum with same arg fold from i [...] adds baed6422b25 Reland r338431: "Add DebugCounters to DivRemPairs" adds 4dbc3320660 Add maybe-unused attribute to a variable. adds 6b6a4ee7d77 [AArch64] DWARF: do not generate AT_location for thread local adds 121bd57dbe0 [PowerPC] Do not round values prior to converting to integer adds 1c8763a4dce [ADT] Add some documentation for GraphTraits. adds 4f8fe653608 [LICM] hoisting/sinking legality - bail early for unsupport [...] adds b4d32d09c57 Fix FCOPYSIGN expansion adds 218719c51e6 [LICM] Expand tests to highlight an oddity in sinking imple [...] adds b41c2e390dc [LICM] Factor out fault legality from canHoistOrSinkInst [NFC] adds e815ef97079 Test commit. adds 6e63f1c5224 [AArch64] Add support for got relocated LDR's adds f166ea7ca2d [UnJ] Add debug messages for why loops are not unrolled. NFC adds c6ba19258a5 lit: bump version number adds b30285c9707 utils/release/tag.sh: add debuginfo-tests to project list adds 8c575a1c2ec [GlobalISel] Rewrite CallLowering::lowerReturn to accept mu [...] adds 47b593936e4 [emacs] Indent statement continuation to match clang-format adds 9808d690618 [GlobalISel] Fix typo with missed override specifier adds 87ee9baa74a [X86][SSE] Pull out duplicate VSELECT to shuffle mask code. NFCI. adds 4d0538ee448 Add include guard adds 7cb2547b5f8 [X86][SSE] Add more UDIV nonuniform-constant vector tests adds a9ba7266d45 [llvm-exegesis] Rename InstructionInstance into Instruction [...] adds a86b69635fd [llvm-mca] Use a vector to store ResourceState objects in t [...] adds 2153e58d865 [llvm-ar] Correct help text adds bd8ff3504a8 [llvm-ar] Fix help text test. NFC. adds c9baad19d31 AMDGPU: Fix scalarizing v4f16 fcanonicalize adds 2920ef78158 DAG: Fix vector widening fcanonicalize adds fd0862123da [ValueTracking] fix maxnum miscompile for cannotBeOrderedLe [...] adds 5907e1ea986 [ARM][NFC] Follow up of r338568 adds e1c9b76cd3d [InstSimplify] move minnum/maxnum with undef fold from instcombine adds 24c4936dc05 [InstCombine] [NFC] Tests for select with binop fold adds 79b60e464bf [X86][SSE] Add uniform/non-uniform exact sdiv vector tests [...] adds 00c90457120 [SLC] Refactor simplification of pow() (NFC) adds 9cb26abb0fb [X86] Allow fake unary unpckhpd and movhlps to be commuted [...] adds f58835b3b61 [MS Demangler] Resolve back-references lazily. adds c6b30d1f129 Use %.*s instead of %*s when formatting strings with explic [...] adds 7de6a1524c2 Fix a couple of warnings. adds fb1454729e4 Update the LLVM VS integration to sign the assembly. adds 2eed0509599 Fix one more warning. adds 63fe07e426a [WebAssembly] Ensure bitcasts that would result in invalid [...] adds 15bc9858adf [Support] fix TempFile infinite loop and permission denied errors adds 7811a54d576 [itanium demangler] Support dot suffixes on block invocatio [...] adds 0380d77b497 CMake: Remove LLVM_DYLIB_SYMBOL_VERSIONING adds 4aec14e3f66 [NFC] clang-format cleanup of a couple files in llvm-objcopy. adds 710aab8e4fe [Support] [NFC] change comment about retries in createUniqueEntity adds 5c1bd30b863 [SCEV] Properly solve quadratic equations adds ddedb75c1d0 [DebugInfo/DWARF] Remove redundant iterator type. NFC adds 40eb37919a1 Unbreak build after r338758: specify lambda return type explicitly adds fbf5dde96bf [Support] Add an enable bit to our DebugCounters adds e3f12bdc7ba [ORC] Add a re-exports fallback definition generator. adds df48071db73 [X86] Autogenerate complete checks. NFC adds 913533ec00b [Unittests] Fix returning string in SolveQuadraticEquationWrap adds 0ac578037cc [WebAssembly] Support for atomic.wait / atomic.wake instructions adds 0b5d0cfa8e5 [Hexagon] Simplify CFG after atomic expansion adds f1aa92e7028 [MS Demangler] Fix some tests that are no longer broken. adds 5e96e38d965 [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor adds fe4807d1761 [X86] Add NEG and NOT test cases to atomic_mi.ll in prepara [...] adds 0c927928e41 [X86] Allow 'atomic_store (neg/not atomic_load)' to isel to [...] adds 79905333cdf [AMDGPU] Reworked SIFixWWMLiveness adds 25b58860e76 [AMDGPU] Minor change to d16 buffer load implementation adds f4a5ef1f003 [GlobalMerge] Allow merging globals with explicit section m [...] adds 58b1de483d3 objdump: Better handling of Mach-O universal binaries adds fb8aeadb5e5 [LICM] Remove unneccessary safety check to increase sinking [...] adds ee462eee339 [X86] Prevent promotion of i16 add/sub/and/or/xor to i32 if [...] adds f24d85d9be1 [X86] Autogenerate complete checks. NFC adds 1435ef31d85 [X86] Autogenerate complete checks. NFC adds bf116bb82d0 [X86] Add R13D to the isInefficientLEAReg in FixupLEAs. adds f5ce968e81e [X86] Autogenerate complete checks. NFC adds be1098c24b9 [X86] When post-processing the DAG to remove zero extending [...] adds 18e311ebbb7 [Dominators] Convert existing passes and utils to use the D [...] adds ebab95406fe [InstSimplify] fold extracting from std::pair (2/2) adds 91fa1be82c2 [X86] Support fp128 and/or/xor/load/store with VEX and EVEX [...] adds a9028ca1b43 [Dominators] Refine the logic of recalculate() in the DomTr [...] adds 1e182a91377 build_llvm_package.bat: Add OpenMP back adds 92ac75817fa [X86] Remove all the vector NOP bitcast patterns. Use a few [...] adds ea39027a818 [XRay][llvm] Load XRay Profiles adds 1760333a4bc [XRay] Fixup: remove 'noexcept' in defaulted move members adds afa9b4c739d [XRay] fixup: Add missing std::move(...) adds c45dda4fda4 [XRay] fixup: add one more missing std::move(...) adds 0c1e01d11aa [ARM] FP16: support VFMA adds f1843f8e41d [X86] Add example of 'zero shift' guards on rotation patter [...] adds 93e0d05b71d [XRay][tools] Use Support/JSON.h in llvm-xray convert adds 33493244220 [ARM] FP16: support vector zip and unzip adds 80d3cc7363b [llvm-exegesis] Renaming classes and functions. adds 5bf23c0ee01 [TargetLowering] Generalise BuildSDIV function adds 8602af619ee [Windows FS] Allow moving files in TempFile::keep adds 00ccfbc5889 [NFC] Move some methods into static functions adds 8d89c08c5ba [NFC] Add missing comment adds b49e61777a7 [SystemZ] Improve handling of instructions which expand to [...] adds 73b8421aafd [DebugInfo/Verifier] Don't emit error for missing module in index adds 3a8b61c1b61 convert some tabs to spaces adds 614e6127d2f [llvm-mca][docs] Improve the CommandLine documentation. adds 1a16c79be03 [Dominators] Make RemoveUnreachableBlocks return false if t [...] adds d6b95e9be38 [llvm-mca] Speed up the computation of the wait/ready/issue [...] adds 54c1354d1ea [WebAssembly] Cleanup of the way globals and global flags a [...] adds 5e1d4374735 [Partial Inlining] Fix small bug in detecting if we did something adds a02557d1b8e [X86] Fix line endings. adds dfa0460a549 [llvm-mca][docs] Move the code marker text into its own sub [...] adds 1a17324d819 Fix crash in bounds checking. adds 8ef7ef81f78 [SLC] Refactor shrinking of functions (NFC) adds e60d78fd125 [X86] Add test cases for the current codegen of __builtin_parity. adds 8d1ce331584 [X86] Add a DAG combine for the __builtin_parity idiom used [...] adds 9f9755d867f [NVPTX] Handle __nvvm_reflect("__CUDA_ARCH"). adds 7166ee595d5 DAG: Enhance isKnownNeverNaN adds bb272977e85 [Support] Don't initialize compressed buffer allocated by z [...] adds 027b97fe0ac [SelectionDAG] Teach LegalizeVectorTypes to widen the mask [...] adds f8fba9029f6 [TRE][DebugInfo] Preserve Debug Location in new branch instruction adds b37b5c5bb2e [X86] Autogenerate complete checks. NFC adds 91f64a0abdd [X86] Remove RELEASE_ and ACQUIRE_ pseudo instructions. Use [...] adds a845a92bfa7 [X86] Layout tests exactly as update_llc_test_checks.py would adds db7ed853528 [X86] Make abi-isel.ll like update_llc_test_checks.py output adds c2be4a7cdda [X86] Re-generate abi-isel.ll checks with update_llc_test_c [...] adds 592e45f05e2 [X86] Add test cases to show missed opportunity to use RMW [...] adds a5b8d5a2e75 [X86] Add isel patterns for atomic_load+sub+atomic_sub. adds 1090c4ba259 Use the same constants as zlib to represent compression level. adds ec2a7945782 Fix buildbot breakage. adds a347456a98f [GISel]: Add Opcodes for CTLZ/CTTZ/CTPOP adds 8d82395b2d2 Reverted r338825 and all the following tries to fix issues [...] adds 134b06ddd01 [ADCE] Remove the need of DomTree adds 18aa36fa4fc [llvm-objdump] Remove continue after report_error which is [...] adds 30fa583f843 [TailCallElim] Preserve DT and PDT adds b2e68027e06 [ADT] Add an early-increment iterator-like type and range adaptor. adds f7da01387d0 [InstCombine] [NFC] Tests for strcmp to memcmp transformation adds f6904f8484b [X86] Remove stale comments from a test. NFC adds 02c1957ea82 [NFC][InstCombine] Regenerate set.ll test adds fd7de2bbcf3 [NFC][InstCombine] Add tests for sinking 'not' into 'xor' ( [...] adds 6dac043f8ce Revert "Add a warning if someone attempts to add extra sect [...] adds 88ab6705571 Enrich inline messages adds d4945d6147c [NFC] Fixed inliner tests adds 40868d43719 [NFC] Fixed inliner tests - 2 adds 9a3ece15dd3 [ORC] Change JITSymbolFlags debug output, add a function fo [...] adds c64ea65b564 [ORC] Remove an incorrect use of 'cantFail'. adds d78e43427f4 [docs] Reinstate r337730 - Add support for Markdown documen [...] adds c0cb45a2cf1 [docs] Turn of `nasm` highlighting for a code block. adds 7290db8e11c [docs] Fix an LLVM-syntax code block to actually be valid L [...] adds 4c31db3adf7 [docs] Remove an example that isn't well formed LLVM IR and [...] adds 512e317975b [docs] Correct the basic syntax structure of the DISubrange [...] adds 63c6deda4e5 [docs] Switch debug info metadata blocks to use `text` inst [...] adds cb6242dabbc [DebugInfo] Refactor DbgInfoIntrinsic class hierarchy. adds e3fd2cc5fea [NFC] Fixed unused function warning adds 5158029c058 [NFC] Fix typo adds a1706269a05 [GuardWidening] Widen guards with conditions of frequently [...] adds b71ba51d81f [ValueTracking] Teach isKnownNonNullFromDominatingCondition [...] adds d9c4e386780 Try to fix buildbot adds 376c0870719 Revert rL338990 to see if it causes sanitizer failures adds 86b1509b594 [docs] Stop trying to parse the ThinLTO summary IR fragment [...] adds f6ba2bc74ba [docs] Remove the `dso_local` tag from these functions. adds 084fdcc27e8 [docs] Continue working around broken Sphinx parsing of LLV [...] adds 1aa1d5cfe7c Re-enable "[ValueTracking] Teach isKnownNonNullFromDominati [...] adds c7a69f138e2 ARM-MachO: don't add Thumb bit for addend to non-external r [...] adds 06ef1791538 Fix modules build with different technique to suppress Knut [...] adds fe95ff1e0b1 [AArch64] Fix assertion failure on widened f16 BUILD_VECTOR adds 2813b7a46da [NFC] Fixed unused function warning adds 5b20e129cf9 Revert unused function fix adds 5edce4ca15d [NFC] Fixed unused function warnings adds c3263d7deef AMDGPU: Rename check prefixes in test adds 4e1ab5cbfb6 ValueTracking: Handle canonicalize in CannotBeNegativeZero adds 273374717eb AMDGPU: Fold v_lshl_or_b32 with 0 src0 adds 5b8a7e263c1 Fix raw_fd_ostream::write_impl hang due to an infinite loop [...] adds 62f717097f0 Fix typo in the MSVC Visualizer for SmallVector class adds 5312a9b038b [RegisterCoalescer] Delay live interval update work until t [...] adds 87986de4303 [X86] Add test cases to show bad use of "and $0" and "orl $ [...] adds beea2e2b69d [X86] When using "and $0" and "orl $-1" to store 0 and -1 f [...] adds 0b1717033ef [X86] Recognize a splat of negate in isFNEG adds fabcc790fc0 [llvm-pdbutil] Support PDBs without a DBI stream adds f064d04716a [SLC] Fix shrinking of pow() adds 9f5cab6fbe5 [LICM] Add tests highlighting missing hoists for intrinsics [NFC] adds 5c412ae2f6a [X86] Fix assertion in subreg extraction adds 63e7c725f46 [LICM] Strengthen invariant.start hoisting tests [NFC] adds 7ac42ca6410 Fix a -Wsign-compare adds f0fa788ac74 AMDGPU: Fix implementation of isCanonicalized adds 13888fd13af [LICM] Further strengthen tests for hoisting guards and inv [...] adds a0ad7973811 AMDGPU: Conversions always produce canonical results adds f583815bba9 AMDGPU: Treat more custom operations as canonicalizing adds f06afc396f5 MC: Redirect .addrsig directives referring to private (.L) [...] adds 418492e425f [LICM] Extract a helper function for readability [NFC] adds 2a710f9b488 AMDGPU: Refactor fcanonicalize combine adds a8868c6067a AMDGPU: Push fcanonicalize through partially constant build_vector adds a27199db06e [lit, python] Always add quotes around the python path in lit adds 6ae1bfa7a50 AMDGPU: Handle some vector operations in isCanonicalized adds f966a408531 AMDGPU: cvt_pk_rtz_f16 canonicalizes adds 7e13b7e2965 [WebAssembly] Replace SIMD expression types with V128 adds 3e2cfa03da4 [WebAssembly] Enable atomic expansion for unsupported atomicrmws adds bc569e6512c [NFC] Factor out implicit control flow logic from GVN adds ca626b31973 [lit, tests] Fix failing lit test: shtest-format.py adds 300176c132f [XRay] Improve error reporting when loading traces adds a4b4e86ad88 [SelectionDAG][X86] Rename getValue to getPassThru for gath [...] adds a6d27860a53 [SelectionDAG][X86] Rename MaskedLoadSDNode::getSrc0 to get [...] adds faf46314a8e AMDGPU: Add feature vi-insts adds 20e8e6e68f6 [ARM][NFC] Replaced tab characters in test file vfcmp.ll. adds b40956fe649 [yaml2obj] - Add a support for changing EntSize. adds af11d878af2 vs integration: fix default path to clang-cl adds 1e99c608efe vs integration: update the publisher name adds bb0d1d0b486 vs integration: bump version number adds 8a69efc9542 [X86][SSE] Add more non-uniform exact sdiv vector tests cov [...] adds 4fcef69e659 [TargetLowering] Add support for non-uniform vectors to BuildUDIV adds 23332c50c13 [DebugInfo] Reduce debug_str_offsets section size adds 6d74417eb4f [Tablegen] In TargetSchedule.td: Remove unused argument `pf [...] adds 82571dfdc11 [mips] Handle branch expansion corner cases adds b2fdb72a010 Fix inconsistency with/without debug information (-g) adds 926b53bb067 [GVN,NewGVN] Move patchReplacementInstruction to Utils/Local.h adds c8c3302c884 [SystemZ] NFC: Remove redundant check in SystemZHazardRecognizer. adds daf385e5698 [SystemZ] Comment update. adds 1b7b25a0230 [InstSimplify] move misplaced minnum/maxnum tests; NFC adds 7e35c221fbd [InstSimplify] add tests for minnum/maxnum with shared op; NFC adds 5ab217ce421 [InstSimplify] move minnum/maxnum with common op fold from [...] adds ee2e6d806cf [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions [...] adds 13f3fc4d277 [TargetLowering] Use pre-computed Shift value type in Build [...] adds 29e9277c6c2 [DAG] Allow non-uniform constant vectors to call BuildSDIV adds 5aa74422b69 [ARM] FP16: codegen support for VACGT adds 512264ba6eb [GVN,NewGVN] Keep nonnull if K does not move. adds b0e8dee0f66 [RFC] Build LLVM-C.dll on MSVC that exports only the C API adds bddc6e21c75 [SelectionDAG][X86][SystemZ] Add a generic nonvolatile_stor [...] adds bd8a67bd05d [SelectionDAG] When splitting scatter nodes during DAGCombi [...] adds 9ff34990e52 [LICM] Strengthen assume hoisting tests [NFC] adds 9ff4d237d03 [SampleFDO] Fix a bug in getOrCompHotCountThreshold/getOrCo [...] adds 0b9e7ad06cc [SLP] Fix insert point for reused extract instructions. adds b651cfc7119 [InstSimplify] add tests for fadd/fsub; NFC adds ef9e4010080 Update msbuild integration warnings: Don't warn on /Zi and /X adds c10f372ba1e [InstSimplify] fold fsub+fsub with common operand adds c544ebb3658 [WebAssembly] CFG sort support for exception handling adds a8ab9e6d20b [Local] Add dbg location on unreachable inst in changeToUnr [...] adds a5d9c8f92a2 [InstSimplify] fold fadd+fsub with common operand adds c517d08361a [InstSimplify] fold fsub+fadd with common operand adds 9b5ab2cc213 [Hexagon] Allow use of gather intrinsics even with no-packets adds 638925075c5 [lit, python3] Update lit error logging to work correctly i [...] adds ab3088f7413 [lit] Disable shtest-timeout on Windows adds 4f8862743a4 [WebAssembly] Update SIMD binary arithmetic adds dcf686e1e73 AMDGPU: Remove broken i16 ternary patterns adds 5718b6f1bcb Refactor FileCheck to make it usable as an API adds 4d56d49ce18 [Coverage] Delete getCounterMismatches, it's dead code (NFC) adds 71a5ad442b3 [Coverage] Ignore 'unused' functions with non-zero executio [...] adds 80b87c3cb3f [InstCombine] add tests for fneg of fmul/fdiv with constant; NFC adds eeed30a7348 [NFC] adding tests for Y - (X + Y) --> -X adds aa84ac19e44 [InstCombine] fix FP constant in test; NFC Too many digits... adds b69cebd658b [InstCombine] add tests for fneg fold including FMF; NFC adds 70dbc396c83 [tablegen] Improve performance of -gen-register-info by rep [...] adds 31a9127a617 [MS Demangler] Properly handle backreferencing of special names. adds 84029c02723 [NFC] Add some tests on mustexec adds ea2a187f0de [ARM] FP16: support the vector vmin and vmax variants adds 9b16a0bf49b [NFC][InstCombine] Cleanup demorgan-sink-not-into-xor.ll test adds ba39c1b56cd Support inline asm with multiple 64bit output in 32bit GPR adds 93ef7cf14b5 [ARM] FP16: support vector INT_TO_FP and FP_TO_INT adds 2b9bc063aef [TargetLowering] BuildUDIV - Early out for divide by one (PR38477) adds 6c395a1b585 [Wasm] Don't iterate over MachineBasicBlock::successors whi [...] adds b10a250635f [X86][SSE] Add divide-by-one exact sdiv vector test adds 648f1e065da [ARM] FP16: vector VMUL variants adds 32fc17a3577 [ARM] FP16: vector vmov and vdup support adds 52db212f747 [ARM] FP16: codegen support for VEXT adds b6b375c7eca [InstCombine] De Morgan: sink 'not' into 'xor' (PR38446) adds f925727f874 test commit access adds 98bb3fb6304 [TargetLowering] Remove APInt divisor argument from BuildEx [...] adds cee64098465 [X86][SSE] PR38477 test is more cleanly tested with udiv in [...] adds 752da31e957 [InstCombine] fold fneg into constant operand of fmul/fdiv adds c1affcdede1 Add a CommandGuide for llvm-objdump adds 497f7d27c63 [ARM][NFC] Replaced tab-characters in test file vtrn.ll adds 2c34155a200 [RISCV] Add InstAlias definitions for add[w], and, xor, or, [...] adds 8a325745713 [TargetLowering] BuildUDIV - Add support for divide by one [...] adds 5e1abaf015b [RISCV] Add mnemonic alias: move, sbreak and scall. adds 2235c76a9bf [CodeGen] emit inline asm clobber list warnings for reserved adds 15de990f32d [PowerPC] Improve codegen for vector loads using scalar_to_vector adds cf105970b5e [DAG] DAGCombiner::visitSDIVLike - remove unnecessary isCon [...] adds caea841122c [InstCombine] add tests for fsub folds; NFC adds bd96310a2c7 [InstCombine] fold fsub+fsub with common operand adds 6b0047a7da8 [InstCombine] fold fadd+fsub with common operand adds 86e6f59695e [DebugInfo] Fine tune emitting flags as part of the producer adds 7689b8dd09a [WASM] Fix overflow when reading custom section adds 35d3bbfa095 AMDGPU: Fix shifts for i128 adds f1757fd8077 AMDGPU: Error more gracefully on libcalls adds 18b615c1644 [Hexagon] Diagnose misaligned absolute loads and stores adds 26f3bc576f6 revert '[CodeGen] emit inline asm clobber list warnings for [...] adds 6e073ca8401 [MS Demangler] Create a new backref context for template in [...] adds 741af08ef57 revert tests of '[CodeGen] emit inline asm clobber list war [...] adds 650bbe0ff0d Fix missing C++ mode comment in header adds aae8303b436 [ARM] Avoid spilling lr with Thumb1 tail calls. adds 1f6a7581c2d cmake: Store LLVM_VERSION_SUFFIX in LLVMConfig.cmake adds c007b4db6bc [cmake] Append LLVM_VERSION_SUFFIX to SOVERSION adds 71299703e41 [DWARF] Unclamp line table version on Darwin for v5 and later. adds e32dc0cc26c [x86] add tests for fsub+fadd with FMF; NFC adds 85ffa199e1c [ADT] Normalize empty triple components adds e52df1611ad [Demangle] Add another test for ItaniumPartialDemangler adds e6de6e24204 [DAGCombiner] move fadd simplification ahead of other folds adds a521995ff00 [DAGCombiner] loosen constraints for fsub+fadd fold adds f44662e5c40 [x86] add test for commuted variant for fsub fold; NFC adds f787c2d837a [DWARF] Verifier now handles .debug_types sections. adds 13ced78da16 [CMake] Use normalized Windows target triples adds 0cb6e749d53 [LICM] Add an assert to ensure all instruction types needin [...] adds f67b15406f7 [NFC] ConstantMerge: don't insert when find should be used adds dad5e8aacd2 [LICM] Add tests for future hoisting of fence instructions [NFC] adds 8e0b205f3bd [RISCV] Add "lla" pseudo-instruction to assembler adds 8da71ffd55f [NVPTX] Select atomic loads and stores adds 2b0633ba70f cmake: don't pack system libs unless CMAKE_INSTALL_UCRT_LIB [...] adds d6879f9d248 [X86] Improved sched models for X86 XCHG*rr and XADD*rr ins [...] adds 3e3f55fb7f0 vs integration: update the manifest to require VS 2017 adds 660ae1d9b90 vs integration: bump version number adds 2a529f7aa0b [X86][SSE] Combine (some) target shuffles with multiple uses adds d5be0360b62 [X86][SSE] Remove PMULDQ/PMULUDQ by zero adds cc67ca7ead1 [ARM] FP16: codegen support for VTRN adds c5db0e0f7c7 [TargetLowering] Add BuildSDIVPattern helper to BuildExactS [...] adds 2998722fb03 [InstCombine] reduce code duplication; NFC adds ead8b39fb5b [MC] Remove PhysRegSize from MCRegisterClass adds d99d65710d0 [MC][PredicateExpander] Extend the grammar to support simpl [...] adds 5e77ae5ff56 [ARM] Replace processor check with feature adds 431efe4a237 [ARM] Adjust the feature set for Exynos adds 5a282e54d07 extend folding fsub/fadd to fneg for FMF adds 6bbc345f937 [llvm-objcopy] Add --dump-section adds 3d464de9687 [SelectionDAG] try harder to convert funnel shift to rotate adds cddb95c7bc9 [GlobalOpt] Don't apply fastcc if it would break inalloca i [...] adds 123d5beafd7 [InstCombine] add vector tests for fsub+fmul; NFC adds ffc59809e8c [llvm-objcopy] Add --prefix-symbols option adds 2c03a06c9e8 SCEV should forget all loops containing a deleted block. adds 0ea64366b04 [Hexagon] Map ISD::TRAP to J2_trap0(#0) adds 4afd04a7bb6 [NFC] Remove magic bool param in RAUW adds 425788d8b59 Fix few g++ 8 warning with non obvious copy object operations adds ccbe637eb27 [InstCombine] allow fsub+fmul FMF folds for vectors adds 677e12bf9f7 Remove obsolete policy settings adds 33f1bc4cd7b Fix typo adds fbcccaf8cc6 [LICM] hoist fences out of loops w/o memory operations adds f88a6410d3a [RISC-V] Fixed alias for addi x2, x2, 0 adds 3173bbdb726 [LICM] Suppress a compiler warning noticed by one of the bots adds 9d9ecd48fb7 ConstantMerge: update MadeChange when change is made adds 01d33f7676b [NFC] ConstantMerge: factor out some functions adds 43efefa1c86 Add owner for llvm-objcopy adds 54b09599fc4 [InstSimplify] move minnum/maxnum with Inf folds from instcombine adds 3b9733f095c [MC] Move EH DWARF encodings from MC to CodeGen, NFC adds 2c938a6f65d [WebAssembly] Fix wasm backend compilation on gcc 5.4: vari [...] adds 0904319a620 ValueTracking: Start enhancing isKnownNeverNaN adds 024925d385a [llvm-objcopy] NFC: Add some color to error() adds e598b5c8618 [X86] Qualify one of the heuristics in combineMul to only a [...] adds 36f54002c93 [WebAssembly] Gate i64x2 and f64x2 on -wasm-enable-unimplemented adds af0751b6c0c [InstCombine] Transform str(n)cmp to memcmp adds 3e5777f3b95 [MemorySSA] "Fix" lifetime intrinsic handling adds 252445ebb1e [MSan] Shrink the register save area for non-SSE builds adds 224f18f3582 [NFC] Add tests that demonstrate that MustExecute is fundam [...] adds 201534e1aa6 Rename the cfguard module flag to cfguardtable adds 6ec2af8bc68 [Tablegen][SubtargetEmitter] refactor method `emitSchedMode [...] adds be12728bc54 Fix -Wimplicit-fallthrough warning introduced in rL339397. adds a59f7f099c7 [X86][SSE] Pull out repeated shift getOpcode() calls. NFCI. adds c709c56b9ad [ARM] Disallow zexts in ARMCodeGenPrepare adds f034be4325e [MS Demangler] Fix several issues related to templates. adds 2255d8ef79a [MS Demangler] Disable a couple of tests. adds 10ff79db772 [MS Demangler] Properly demangle conversion operators. adds abd85864811 [InstCombine] rearrange code for foldSelectBinOpIdentity; NFCI adds 78f83ec7216 [InstCombine][NFC] Added tests for select with binop fold adds 395e45dbe5c [InstCombine] revert r339439 - rearrange code for foldSelec [...] adds 9f42ecf77b0 [hwasan] Add -hwasan-with-ifunc flag. adds 807955f3a5c [llvm-objcopy] NFC: consistently use typename ELFT::<X> def [...] adds 8da2e112bcd [MS Demangler] Add conversion operator tests. adds b5eef713770 [InstCombine] add/update tests for selectBinOpIdentity; NFC adds 5aaa8205c76 Update the coding standards and developer policy documentat [...] adds 2388a7db339 AMDGPU: Add LLVM_FALLTHROUGH adds 4d8cda85adf AMDGPU: Match isfinite pattern to class instructions adds 203b8a7809b AMDGPU: Turn class x, p_zero|n_zero into fcmp oeq x, 0 adds a13d395b9e1 AMDGPU: Combine and of seto/setuo and fp_class adds 3119fcce36e revert r339450 - [MS Demangler] Add conversion operator tests adds 7f32e5e1904 AMDGPU: More canonicalized operations adds f819cf9ca33 [MS Demangler] Demangle cv qualifiers on template args. adds bdbdf525e9b Resubmit r339450 - [MS Demangler] Add conversion operator tests adds 55b4407c7d6 [InstCombine] add tests to show disabling of libcall/intrin [...] adds 2427dc2a353 [llvm-mca] Make InstrBuilder::getOrCreateInstrDesc private. NFC. adds c5553c47ec1 [InstCombine] rearrange code for foldSelectBinOpIdentity; NFCI adds 65ef1d041c5 [InstCombine] add tests for fsub factorization; NFC adds cffbbb125ea [MS Demangler] Support extern "C" functions. adds 0365cb94940 [ARM] Adjust AND immediates to make them cheaper to select. adds eb8079e8235 [WebAssembly] Added default stack-only instruction mode for MC. adds df25b5d38f4 [NFC] More ConstantMerge refactoring adds 033cdeca678 Fix unused lambda capture warning from r339472. adds a82514350b2 Revert "[NFC] More ConstantMerge refactoring" adds c0723309373 [LICM] Hoist assumes out of loops adds 018235abdfc Re-commit "[NFC] More ConstantMerge refactoring" adds 202efa74090 AMDGPU/GlobalISel: Define instruction mapping for G_INSERT adds 1c0dd31a783 [gold] Fix Tests cases on i686 adds 5b2a776ed94 Fix WebAssembly instruction printer after r339474 adds 6534d1052fd [X86] Change the MOV32ri64 pseudo instruction to def a GR64 [...] adds 91ac2ac7f5d [X86] Remove ADD8mi and ADDmr from the macro fusion shouldS [...] adds 85b787154c9 [X86] Add the mem-reg form of CMP to the macro fusion shoul [...] adds df14c7f5472 [X86] Remove the AL/AX/EAX/RAX short immediate forms from t [...] adds d2a6b5951c9 [UnJ] Create a hasInvariantIterationCount function. NFC adds 6fb93f326da [UnJ] Improve explicit loop count checks adds bfd4fdf0e5f [Dominators] Remove the DeferredDominance class adds 4751420c7e3 [X86] Remove unnecessary AddedComplexity line. NFC adds 80ad764eba7 [TargetLowering] Use APInt::isSubsetOf to simplify some code. NFC adds a19815f1d99 [TargetLowering] Simplify one of the special cases in Simpl [...] adds 8750be505da AMDGPU: Fix packing undef parts of build_vector adds 3b2fa4ee595 AMDGPU: Use splat vectors for undefs when folding canonicalize adds 10398322afa AMDGPU: Check NSZ MI flag when folding omod adds ac6c5d8a364 [InstSimplify] Guard against large shift amounts. adds 09ceeb3f508 [InstCombine] move/add tests for fadd/fsub factorization; NFC adds fa0e915a8e4 [InstCombine] fix/enhance fadd/fsub factorization (X * Z) [...] adds 9ff5ab2f4e0 [InstCombine] Fold Select with binary op - non-commutative opcodes adds cac6dd83b25 [Support][JSON][NFC] Silence GCC warning about broken stric [...] adds 3d3659c1e9f [NFC] Renamed test file adds bae42d6404a [NFC] Fixed build, updated tests adds f0912abc34c DAG: Check no-signed-zeros instead of unsafe-fp-math adds 1f25a887f69 AMDGPU: Cleanup min/max legacy tests adds d0ee5d297e8 [globalisel] Remove dead code from GlobalISelEmitter adds 3bc135240d9 [X86] Add constant folding for AVX512 versions of scalar fl [...] adds 069f0c31f78 [InstCombine] Replace call to haveNoCommonBitsSet in visitX [...] adds 6145f7d3cff [InstCombine] Fix typo in comment. NFC adds 7bbb4c9b165 [SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast [...] adds fa3003a7832 Restore correct x86_64 EH encodings in kernel code model adds 36c59846ae3 [SelectionDAG] In PromoteIntRes_BITCAST, when the input is [...] adds 3638207d8f9 [SelectionDAG] In PromoteFloatOp_BITCAST, insert a bitcast [...] adds ffc8c538b70 [GuardWidening] Widen very likely non-taken br instructions adds 4514ca2f1dd [ARM] Added FP16 VREV Vector Instrinsic CodeGen support adds 5da7a1c1e5e Remove extra semicolon (fixes -Wpedantic warning). NFCI. adds ef546c9d7f2 [Sparc] Add support for the cycle counter available in GR740 adds 61e1c20944b [Tablegen][SubtargetEmitter] Improve expansion of predicate [...] adds 4177d36e035 [CGP] Fix GEP issue with out of range APInt constant values [...] adds 47b52ac4d99 [DAGCombiner] simplifyDivRem - add comment describing divid [...] adds a73fb6d0ab6 [X86] Add tests showing missing div/rem 0, X -> 0 combines adds 6cc0fcd6bb5 [SystemZ] Increase the amount of inlining. adds d9eaefb8663 Check for tied operands adds 01087accf22 Revert "[Sparc] Add support for the cycle counter available [...] adds 423c85b5519 [Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC adds 87972c49190 [Tablegen] Replace uses of formatted_raw_ostream with raw_o [...] adds 13b933258d8 [SLC] Expand simplification of pow() for vector types adds 709aadb7c35 [InstCombine] auto-generate full checks and add cos intrins [...] adds 77d3f0227a5 [itanium demangler] Add llvm::itaniumFindTypesInMangledName() adds d2f20dd1d7c [InstCombine] Limit simplifyAllocaArraySize constant foldin [...] adds b4de19d7ebf [ADT] Implemented unittests for ImmutableList adds 31ff4125c7d Attempt to fix some MSVC build errors. adds 3a74b4221a7 [SimplifyLibCalls] reduce code for optimizeCos; NFCI adds 09af9d2e29f [X86][BtVer2] Use NoSchedPredicate to model default transit [...] adds fd195ce798b [llvm-mca] Propagate fatal llvm-mca errors from library cla [...] adds b15a8309585 [InstCombine] add more tests for trig reflections; NFC (PR38458) adds 7b19ab70e3e [CodeGen] Fix assert in SelectionDAG::computeKnownBits adds e8a927c34a0 [InstCombine][NFC] Tests for 'signed truncation check' opti [...] adds 8b80050699f [SimplifyLibCalls] add reflection fold for -sin(-x) (PR38458) adds f3c7df4a0ed NFC: Add a test to LV showing that reduction is not possibl [...] adds 6c5927533a7 [SimplifyLibCalls] don't drop fast-math-flags on trig refle [...] adds 6a6b35cd86b revert r339608 - [SimplifyLibCalls] don't drop fast-math-fl [...] adds 3edbc102ddf [InstCombine] Optimize redundant 'signed truncation check p [...] adds 8244893b611 Revert "[InstCombine] Optimize redundant 'signed truncation [...] adds a391f98615b [llvm-objcopy] NFC: Fix minor formatting issues adds 9ee8a957cc4 [SimplifyLibCalls] don't drop fast-math-flags on trig refle [...] adds 7705bede805 [NFC][InstCombine] Add a test for D50465 that used to assert adds f91b41f4020 [InstCombine] Re-land: Optimize redundant 'signed truncatio [...] adds 656d5d59d3a [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit [...] adds 5fada2e94d8 [AST] Cleanup code by using MemoryLocation utility [NFC] adds 20a211a99b5 [AST] Minor formatting cleanup [NFC] adds f0b29b88a47 [Support] NFC: Allow modifying access/modification times in [...] adds a297d964167 Revert "[WebAssembly] Added default stack-only instruction [...] adds 3ea7b0a0b1e [BasicAA] Don't assume tail calls with byval don't alias allocas adds d64c9dd5388 [ThinLTO] Handle optional args in assembly format for ConstVCalls adds 78ac4b1f01c [CMake] Split -gx strip flag into -g -x adds d3b60bef640 [ThinLTO] Fix printing of WPD remarks adds a3a6a7d1b97 [NFC] Add comprehensive test of AliasSetTracker with guards adds b0ee0d322a6 [NFC] Modify comment to make it more precise adds 35b2115503a [ARM] ParallelDSP: add option to enable/disable the pass adds 8ec69ac247c [X86] Lowering addus/subus intrinsics to native IR adds 7525376ccf3 Test commit: fix punctuation adds 1fb2ad5ddc4 [RISCV] Fix incorrect use of MCInstBuilder adds 17454e67ca5 [X86] Constant folding of adds/subs intrinsics adds 922ac36549e Fix MSVC "compiler limit: blocks nested too deeply" error. NFCI. adds 62fcc622307 [TableGen] Pass string/vector types by const reference (PR3 [...] adds 0904155b95b [GlobalISel][IRTranslator] Fix a bug in handling repeating [...] adds cb8c5e417d5 [DebugInfo] Generate DWARF debug information for labels. (F [...] adds 08a2e24fdca [X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to [...] adds 8bdeb675f27 [InstCombine] regenerate checks; NFC adds dd807ea799a [Inliner] add inliner stats to new pm version of inliner adds 0e18d0dcb9c [InstCombine] regenerate checks; NFC adds 76cf1f6a8b0 [X86][SSE] Add shuffle combine tests for OR(PSHUFB,PSHUFB) [...] adds 9c0c0a23efe [X86][SSE] Add shuffle combine support for OR(PSHUFB,PSHUFB [...] adds 2f6f2fb76a6 [DAG] Avoid redundant chain transversal in store merge cycl [...] adds f921d44a03e Expose CFG Update struct. Define GraphTraits to get childre [...] adds 1645076dc8e [NFC] Tests for select with binop fold - FP opcodes adds dd11fa16f91 [DomTree] Cleanup Update and LegalizeUpdate API moved to Su [...] adds a06c0f8edb7 [X86][SSE] Avoid duplicate shuffle input sources in combine [...] adds e747ac6d9aa [GraphDiff] Make InverseGraph a property of a GraphDiff. adds 8c444324e7b Revert "[DebugInfo] Generate DWARF debug information for la [...] adds 1464f16217a [LV] Teach about non header phis that have uses outside the loop adds e9759ddbdc5 [Tablegen][MCInstPredicate] Removed redundant template argu [...] adds 95688ee84cf [WebAssembly] SIMD extract_lane adds addd2704187 [MS Demangler] Fix some minor formatting bugs. adds 35b45c96579 [WebAssembly] Fix encoding of non-SIMD vector-typed instructions adds 18a9130c102 [InstCombine] add tests for pow->sqrt; NFC adds 35b8f4b065f [WebAssembly] SIMD encoding tests adds adcef01bd74 [InstCombine] fix typos in tests; NFC adds c4d19094354 [DebugInfoMetadata] Added DIFlags interface in DIBasicType. adds a3fdc1d2931 NFC: Clarify comment in loop vectorization legality adds 5c7c276dd6d Add proper headers in CFGUpdate.h and add CFGDiff.h in the [...] adds 3bd565f2797 Remove vestiges of configure buildsystem adds 4db82cd15b0 [SanitizerCoverage] Add associated metadata to PC guards. adds 1a5e05d0703 [ARM] Make PerformSHLSimplify add nodes to the DAG worklist [...] adds ca4f10703e3 [FPEnv] Scalarize StrictFP vector operations adds c35538fcabb [WebAssembly] Delete a specific push number from test expectations adds fc187011bee [SDAG] Remove the reliance on MI's allocation strategy for [...] adds 34c8f3ddbad [WebAssembly] SIMD Splats adds 6203c9bd082 [hwasan] Add a basic API. adds f464242872b [SDAG] Update the AVR backend for the SelectionDAG API chan [...] adds eb72488593a [X86] Change legacy SSE scalar fp to integer intrinsics to [...] adds 7caa753e199 [NFC][LICM] Make hoist method void adds a3bb636475f [NFC] Add sanitizing assertion to ICF tracker adds d823f47a683 [NFC] Refactoring of LoopSafetyInfo, step 1 adds 9e9c1c4ddd5 [AliasSetTracker] Do not treat experimental_guard intrinsic [...] adds 90048a82062 [ARM] Allow pointer values in ARMCodeGenPrepare adds 81654d23626 [ARM] Allow signed icmps in ARMCodeGenPrepare adds 7e6dd0cff77 [TargetLowering] Add support for non-uniform vectors to Bui [...] adds c60b833f830 [DagCombiner] Don't bother adding to the work list if TLI.B [...] adds 0f7eb9f5326 [TargetLowering] Minor refactor to TargetLowering::BuildUDI [...] adds 406608e1b08 [X86] Add sibling-call test cases adds da4cfd320c2 [X86][SSE] Add sdiv by nonuniform constant vector tests adds a5f4d299297 [UnJ] Rename hasInvariantIterationCount to hasIterationCoun [...] adds f965428b0ed [TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI. adds 3ea0447ec7a [yaml2obj] - Teach tool to produce SHT_GROUP section with a [...] adds 8ae415fb86e Remove lambda default argument to fix gcc pedantic warning. adds 47bbfe3bd01 [llvm-mca] Fix PR38575: Avoid an invalid implicit truncatio [...] adds 7c82b970fb5 [PowerPC] Don't run BV DAG Combine before legalization if i [...] adds 3dd52420555 [ARM] TypeSize lower bound for ARMCodeGenPrepare adds 312924a2b1c [yaml2obj] - Teach yaml2obj to produce SHT_GROUP section wi [...] adds 0566eefef9c [SimplifyCFG] Remove pointer from SmallPtrSet before deletion adds d9e857fb583 [SystemZ] New CL option to enable subreg liveness adds 33a5d47e0f1 [GVN] Fix typo in IsValueFullyAvailableInBlock. NFC. adds 9f59a11e239 [SystemZ] Replace subreg_r with subreg_h adds 4df6ca02ff2 [PowerPC] Enhance the selection(ISD::VSELECT) of vector type adds 165c0cc4857 [SystemZ] Add testcase for r339778 adds d7a0236f295 [RegAlloc] Check that subreg liveness tracking applies to g [...] adds ffcf1047060 [WebAssembly] SIMD replace_lane adds 28f0c7ef0ac [RegisterCoalescer] Reset VNInfo def when copying segments over adds b581cf5c17b [x86] add tests for poor vector intrinsic lowering via lega [...] adds 6faab4de878 [x86] add fabs test for vector intrinsic to potential libca [...] adds 0d5de60cbee [RegisterCoalescer] Ensure that both registers have subrang [...] adds 8529a08ceb1 [AArch64] add tests for poor vector intrinsic lowering via [...] adds 41df26a4e56 [MemorySSA] Expose the verify as a debug option. adds 9dfeae47a7c [InstCombine] Fix IC trying to create a xor of pointer types. adds 8bb6fcb54b3 [WebAssembly] Test commit adds a2ac910471e llvm-readobj: Fix addend in relocations for android packed format adds e94c82ccbba [WebAssembly][NFC] Standardize SIMD multiclass format adds e0dc5c1ea20 [Support] Add a basic C API for llvm::Error. adds 30db32fcf12 Revert "[ARM] Allow signed icmps in ARMCodeGenPrepare" adds c2a24b87802 [MCJIT] Fix a case of Error::success() being passed to repo [...] adds e79e42e6c4d DAG: Try to custom lower when promoting float operands adds 1cdda230e96 [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeB [...] adds 982d395b2af DAG: Use getObjectOffset helper adds abf0ee059c4 AMDGPU: Address todo for handling 1/(2 pi) adds 6737250f979 AMDGPU: Stop producing icmp/fcmp intrinsics with invalid types adds ecc93786a13 [X86] Improve AVX1 shuffle lowering for v8f32 shuffles wher [...] adds 5f9b848ed3e AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 adds 6030329f4bc AMDGPU: Improve extract_vector_elt reduction combine adds d82cfba790c AMDGPU: Fold fneg into fmed3 adds c4dcd354354 [CodeGenPrepare] Add BothExtension type to PromotedInsts adds 61d7ed20677 [llvm-mca] Minor style changes. NFC adds 8f94a553bfa [Metadata] Replace a SmallVector with an array; NFC adds 21f571c07cb [BFI] Use rounding while computing profile counts. adds d914c51df99 [x86] Actually initialize the SLH pass with the x86 backend [...] adds ec2710fb9b3 [X86] Correct some bad FileCheck prefixes in tests. Add tes [...] adds 58d47fbc549 [X86] Remove the unused masked 128 and 256-bit masked padds [...] adds 6914988dcf2 [X86] Remove masking from the 512-bit padds and psubs intri [...] adds 2a96c80ff2a [NFC] Add missing const modifier adds 83b908472d7 [NFC] Remove const modifier to allow further development in LICM adds 87ed975f8b5 [mips] Remove dead code from MipsPassConfig adds 7d16ffe5b76 [ARM] Allow signed icmps in ARMCodeGenPrepare adds 547d94c0203 [ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX adds ff51b9f280e [RISCV][MC] Don't fold symbol differences if requiresDiffEx [...] adds fd2bee90f5b [ARM] Allow zext in ARMCodeGenPrepare adds d9d671112da [yaml2elf] - Simplify code, add a test. NFC. adds 3591e4cd934 [ARM] Ignore GEPs in ARMCodeGenPrepare adds 4b96e82fd27 [yaml2elf] - Use check-next in test. adds f23f849bd17 [yaml2obj] - Allow to use numeric sh_link (Link) value for [...] adds 7edab834d4b [InstCombine] move vector compare before same-shuffled ops adds 0cd45cda8dd [cmake] Prevent LLVMgold.so from being unloaded on Linux adds 46fd9f609b6 [TableGen] Return ValueTypeByHwMode by const reference from [...] adds cfeb0f3b987 [llvm-mca] Small refactoring in preparation for another pat [...] adds 935c1e9f5aa [InstCombine] Expand the simplification of pow(x, 0.5) to sqrt(x) adds 37d2a3546f0 [TableGen] Avoid self getPredicates() != comparison. NFCI. adds 5ae4a74cc0d [ConstantFolding] add tests for funnel shift intrinsics; NFC adds fc96bec77d1 [TableGen] TypeSetByHwMode::operator== optimization adds 8d7767b85e2 [MS Demangler] Don't fail on MD5-mangled names. adds 404ae7db546 [MS Demangler] Demangle string literals. adds 89bba358f5f Add support for AVX-512 CodeView registers. adds 6a67b308fac Fix -Wmicrosoft-goto warnings. adds fd8c4124545 [MC][X86] Enhance X86 Register expression handling to more [...] adds 3c6e3abc6cf [MC] Remove unused variable adds 8c9b074b573 unittests: Don't install TestPlugin.so adds 3b2cfd19a0d [TargetLowering] Refactor BuildSDIV in preparation for D507 [...] adds 25358c8f56e [NFC] Fix typo in test cases adds b35922e680c [X86][SSE] Add sdiv by nonuniform constant vector test cont [...] adds a0d83d520ea AMDGPU: Custom lower fexp adds 550dfae3742 Revert "unittests: Don't install TestPlugin.so" adds cd2d2cfae69 [MC] Cleanup noop default case spelling. NFC. adds 9d1f82a2cc3 [codeview] Use push_macro to avoid conflicts instead of a prefix adds 465c62b8d3e [TargetLowering] Add support for non-uniform vectors to BuildSDIV adds 3174d7c7791 Fix memory leak in demangling of string literals. adds d9c9d827167 [RegisterCoalescer] Shrink to uses if needed after removeCo [...] adds 7b455c4fd2f [llvm-strip] Add support for -p/--preserve-dates adds cb762f1f3dd [SelectionDAG] Improve the legalisation lowering of UMULO. adds 8744f36d0bb [llvm-mca] Refactor how execution is orchestrated by the Pipeline. adds 5ede58d7d77 [MachineVerifier] Check if predecessor is jointly dominated [...] adds fb684e186b0 [WebAssembly] Remove temporary workaround for function bitcasts adds 382c2c9899a [X86] Pre-commit test case for D50827. adds ad8a8d12bf8 Add missing test file from r339799. adds 516dc8bd511 [llvm-mca] Fix -Wpessimizing-move warnings introduced by r339923. adds 4a208889a6c [LICM][NFC] Restructure pointer invalidation API in terms o [...] adds d020e74d683 [SystemZ] Require asserts in subregliveness-06.mir adds 73646782e5d [MemLoc] Fix a bug causing any use of invariant.end to cras [...] adds 17543750d37 [AST] Speculative build fix for a polly buildbot adds 86864df0931 add a missed case for binary op FMF propagation under select folds adds cf8a4a5d5e7 DebugInfo: Add metadata support for disabling DWARF pub sections adds 2a752bfdae6 [MI] Change the array of `MachineMemOperand` pointers to be [...] adds a9c1926d01f [MC] Improve COFF associative section lookup adds d2a106bf4ee Factor Node creation out of the demangler. No functionality [...] adds 2e94bd60b5a [X86] In EFLAGS copy pass, don't emit EXTRACT_SUBREG instru [...] adds 34d0ecae3a4 [DAGCombiner] Don't reassociate operations that have the ve [...] adds 96b3ee568e0 [DomTree] Add constructor to create a new DT based on curre [...] adds 218ada7811f [docs] Try to clarify the FuzzingLLVM docs adds 1f402bfa4fd Update MemorySSA in Local utils removing blocks. adds 7c82ae6d941 [InstCombine] add tests for tan with negated arg; NFC adds 41bee7d4780 [InstrProf] Use atomic profile counter updates for TSan adds 3964940ceb1 [InstCombine] add reflection fold for tan(-x) adds e90d44039a6 [x86/MIR] Implement support for pre- and post-instruction s [...] adds 5e5a9f7ee34 [WebAssembly] CFG stackify support for exception handling adds 1466a5a3703 DebugInfo: Remove command line (& target-based) disabling o [...] adds 3c76da17f7b [WebAssembly] Modify LateEHPrepare one-line description (NFC) adds bc3032830f2 [ADT] Replace a member initializer of a union with an expli [...] adds 907fb9abe88 [GISel]: Add Opcodes for a few LLVM Intrinsics adds 7de28914d7d [Support] Add a public API to allow clearing all (static) t [...] adds d91f0329ac6 [llvm-mc-assemble-fuzzer] Update API - Pass MCObjectWriter [...] adds 7debc334e64 Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics adds 6d4546ea14a [NFC] Add tests to ensure that improvement of MustThrow ana [...] adds 18374180e36 [MustExecute] Fix algorithmic bug in isGuaranteedToExecute. [...] adds 5a4ec120f8e [ARM][NFC] ARMCodeGenPrepare: some refactoring and algorith [...] adds 12061ae7173 [MISC]Fix wrong usage of std::equal() Differential Revision [...] adds 3ec6e52a80d [Sparc] Flush register windows for @llvm.returnaddress(1) adds 8d97f0d4be3 Fix "control reaches end of non-void function" -Wreturn-typ [...] adds 2f779737ec6 [Sparc] Get sret arg size from CallLoweringInfo.getArgs() adds 19640950ddf [DAGCombine] Improve (sra (sra x, c1), c2) -> (sra x, (add [...] adds 3a4d2d38bf8 [ARM/AArch64] TargetParserTest fixes adds c30814805cc [ARM/AArch64] Support FP16 +fp16fml instructions adds aec303a986c [InstCombine] Remove unused method FAddCombine::createFDiv(). NFC adds 19852c64c09 [DAGCombiner] extractShiftForRotate - fix out of range shift issue adds ac879930f81 [PowerPC] Generate Power9 extswsli extend sign and shift im [...] adds fd520f179d9 Revert extraneous directory added by accident in rL340016 adds 0633fddd687 [AArch64] - Generate pointer authentication instructions adds e1166b22b67 [TableGen] TypeSetByHwMode::insert - cache the default MVT. NFCI. adds 77ce59def02 [ConstantFolding] add simplifications for funnel shift intrinsics adds ac92a12e99e [RISCV] Remove unused function adds 9122aa2aace [LICM] Add a diagnostic analysis for identifying alias information adds f148aeb2480 [AtomicExpandPass] Widen partword atomicrmw or/xor/and befo [...] adds c7000f73ec2 [Hexagon] Expand vgather pseudos during packetization adds 1bf795160f3 [InstrSimplify,NewGVN] Add option to ignore additional inst [...] adds 46146670291 [NewGVN] Add tests for r340031. adds af922fde219 [X86] Fix liveness information when expanding X86::EH_SjLj_ [...] adds 12b9cde1952 [x86] Fix test breaking on Darwin after r339962 adds 91bcc605308 [llvm-mca] Removed references to HWStallEvent in Scheduler.h. NFCI adds 81e04e9e9ac [PowerPC] Generate lxsd instead of the ld->mtvsrd sequence [...] adds adb0f66b579 [DebugInfo] Generate DWARF debug information for labels. (F [...] adds 8f783892855 [TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode adds 6c36cc6f616 [MS Demangler] Rework the way operators are demangled. adds 39b5a02c6fe [ThinLTO] Add option for printing import failure reasons adds 5ec0e9dcab9 [IDF] Teach Iterated Dominance Frontier to use a snapshot C [...] adds 545c5cb20b5 [TableGen] Don't separately search for DefaultMode when we' [...] adds 4baf8510375 [X86] Use hasOneUse instead of isOnlyUserOf. NFCI adds 061d7fa2aef [NFC] Expand test cases for simplifying pow() adds f896970b071 [InstCombine] Refactor the simplification of pow() (NFC) adds 7250585b4e5 [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLW adds b7e2745eb46 [Support] NFC: Fix docstring in FileSystem.h. adds 40198e78bb5 [llvm-mca] Reformat a few lines (fix spacing). NFC. adds 18da2d12953 [IDF] Make GD const. adds 9ce73cfd3e9 Remove a hardcoded address in test/DebugInfo/X86/vla-multi.ll adds f3a3ccda026 Test commit adds cd514b66e80 [llvm-objcopy] Add support for -I binary -B <arch>. adds 30a2cc03dc2 Fix windows buildbots by removing : from filenames adds 218b727473c [AST] Adapt Polly to AnalysisSetTracker changes. NFC. adds 00e6049559b [Hexagon] Remove unused functions from HexagonInstPrinter, NFC adds c1011528465 [MS Demangler] Demangle all remaining types of operators. adds 7aacef06ca5 [ORC] Rename VSO to JITDylib. adds fbdb20b2ab5 DAG: Fix isKnownNeverNaN for basic non-sNaN cases adds 651c0bf01a4 [X86] Remove detectAddSubSatPattern. adds 0a4b8880796 [MS Demangler] Properly print all thunk types. adds 2661a6cb5c2 [MC] Improve error message when a codeview register is unknown adds 7f03ac80bc8 ValueTracking: Add tests for isKnownNeverNaN adds a04ab7c2136 [AST] Add tests for argmemonly calls [NFC] adds 803952bdf02 [AST[Tests] Shorten tests using noalias params adds 709fda69699 [AST][Tests] Clarify what each test is doing adds 68cedc8ad59 [DebugCounters] don't do redundant map lookups; NFC adds dc7a8880207 [llvm-objcopy] Implement -G/--keep-global-symbol(s). adds c351fea480b [AST] Clarify printing of unknown size locations [NFC] adds c3f36baa5fa [GISel]: Add Legalization/lowering code for bit counting op [...] adds 8efb13000b8 MC: Remove dead code from WinCOFFObjectWriter.cpp. NFCI. adds 7af2fdceb02 [ORC] Rename 'finalize' to 'emit' to avoid potential confusion. adds eb7a43e43f3 [ORC] Fix some parameter names. NFC. adds b8cf2a3e85f Add the extended XMM registers mappings for AVX-512. adds c9e51dd5ede [DAGCombiner] Allow divide by constant optimization on opaq [...] adds 73258a24136 [X86] Add a signed test case for PR38622. Use nounwind to r [...] adds cf774b7bcc6 [DebugInfo] In FastISel, convert llvm.dbg.label to DBG_LABEL MI. adds 54cf5674ae4 [X86] Merge shift/rotate schedule class instregexs adds 1b130f83bfb [X86] Replace all single match schedule class instregexs wi [...] adds 88048c20048 [RuntimeDyld] Fix a bug in RuntimeDyld::loadObjectImpl that [...] adds 05de30e0954 [MS Demangler] Resolve backreferences eagerly, not lazily. adds ea726c66144 [X86] Add test cases to show missed opportunities to use 51 [...] adds 70fe12d401c [X86] Add support for using 512-bit PSUBUS to combineSelect. adds 88618843c34 [X86] Simplify the PADDUS legality check in combineSelect t [...] adds 03fa7f358cb [X86] Use SDValue::operator== instead of DAG.isEqualTo in s [...] adds a83fad8a70b Updating MergeFunctions.rst adds 1dca6ea705d [X86] Add a test case showing an issue in our addusw patter [...] adds 8a969265baf [X86] Fix an issue in the matching for ADDUS. adds 0f4ea22b4f7 [X86][SSE] Add PACKSS test showing ComputeNumSignBits failu [...] adds 5992c546c18 [SelectionDAG] Add basic demanded elements support to Compu [...] adds 692afe0b2cc [InstCombine] Add test cases for an icmp combine that is mi [...] adds 8bf9e9a0179 [C-API][DIBuilder] Added DIFlags in LLVMDIBuilderCreateBasicType adds 7c767e2cf3d [LLVM-C] Add coroutine passes adds b52e8dcdd12 [bindings/go] Add coroutine passes adds 12df467aacd [PowerPC] Add a peephole post RA to transform the inst that [...] adds b02c5266971 [InstCombine] Move some variable declarations into a more a [...] adds ba88b2b9ee7 [SimplifyCFG] Replace some uses of bitwise or with logical or adds ade2e57434d [llvm] Make YAML serialization up to 2.5 times faster adds 2ca8e676279 [AArch64][SVE] Asm: Add SVE System registers adds f90beef2bb3 Use LLVM_BUILTIN_TRAP not __builtin_trap to appease windows [...] adds f030fcc4ba4 [DWARF] Refactor DWARF classes to use unified error reporti [...] adds 8b5b8b504d5 [X86] Drop unnecessary exact qualifier from packss test adds 11c78fa4d09 [X86][SSE] Add PACKSS test showing ComputeNumSignBits failu [...] adds cdb82fb9b07 [X86][SSE] Fix PACKSS bitcast test from rL340166 adds 956102d0d8b [SelectionDAG] Add partial sign-bit support to ComputeNumSi [...] adds ce61d9b9836 Fix an undefined behavior when storing an empty StringRef. adds 52379849f94 AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space adds 836382087a3 AMDGPU: fix compilation errors since r340171 adds a8767a6d09e [SelectionDAG] Reuse the Op's VT. NFCI. adds 681bdae9774 [llvm-mca] Make the LSUnit a HardwareUnit, and allow derive [...] new 8b1a840e1ea Creating branches/google/stable and tags/google/stable/2018 [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. 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6 +- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 30 +- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h | 33 +- .../ARM/MCTargetDesc/ARMMachObjectWriter.cpp | 10 +- lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 38 +- .../ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp | 7 +- lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp | 15 +- lib/Target/ARM/MLxExpansionPass.cpp | 24 +- lib/Target/ARM/Thumb1FrameLowering.cpp | 2 +- lib/Target/ARM/Thumb2ITBlockPass.cpp | 4 +- lib/Target/ARM/Thumb2InstrInfo.cpp | 4 +- lib/Target/ARM/Thumb2SizeReduction.cpp | 18 +- lib/Target/ARM/ThumbRegisterInfo.cpp | 2 +- lib/Target/AVR/AVR.h | 2 + lib/Target/AVR/AVRExpandPseudoInsts.cpp | 52 +- lib/Target/AVR/AVRISelDAGToDAG.cpp | 10 +- lib/Target/AVR/AVRISelLowering.cpp | 7 + lib/Target/AVR/AVRInstrInfo.cpp | 4 +- lib/Target/AVR/AVRRegisterInfo.h | 5 + lib/Target/AVR/AsmParser/AVRAsmParser.cpp | 4 +- lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp | 17 +- lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h | 16 +- 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lib/Target/X86/Utils/X86ShuffleDecode.cpp | 22 +- lib/Target/X86/X86.h | 2 + lib/Target/X86/X86.td | 33 +- lib/Target/X86/X86AsmPrinter.cpp | 117 +- lib/Target/X86/X86AsmPrinter.h | 3 - lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp | 70 +- lib/Target/X86/X86CallFrameOptimization.cpp | 2 +- lib/Target/X86/X86CallLowering.cpp | 41 +- lib/Target/X86/X86CallLowering.h | 4 +- lib/Target/X86/X86CallingConv.h | 2 +- lib/Target/X86/X86CmovConversion.cpp | 20 +- lib/Target/X86/X86DomainReassignment.cpp | 75 +- lib/Target/X86/X86EvexToVex.cpp | 102 +- lib/Target/X86/X86FastISel.cpp | 108 +- lib/Target/X86/X86FixupBWInsts.cpp | 8 +- lib/Target/X86/X86FixupLEAs.cpp | 72 +- lib/Target/X86/X86FlagsCopyLowering.cpp | 408 +- lib/Target/X86/X86FloatingPoint.cpp | 66 +- lib/Target/X86/X86FrameLowering.cpp | 73 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 453 +- lib/Target/X86/X86ISelLowering.cpp | 4628 +++-- lib/Target/X86/X86ISelLowering.h | 97 +- lib/Target/X86/X86IndirectBranchTracking.cpp | 4 - lib/Target/X86/X86Instr3DNow.td | 17 +- lib/Target/X86/X86InstrAVX512.td | 4748 +++-- lib/Target/X86/X86InstrArithmetic.td | 192 +- lib/Target/X86/X86InstrCMovSetCC.td | 39 +- lib/Target/X86/X86InstrCompiler.td | 407 +- lib/Target/X86/X86InstrControl.td | 28 +- lib/Target/X86/X86InstrExtension.td | 8 +- lib/Target/X86/X86InstrFMA.td | 376 +- lib/Target/X86/X86InstrFMA3Info.cpp | 406 +- lib/Target/X86/X86InstrFMA3Info.h | 302 +- lib/Target/X86/X86InstrFPStack.td | 30 +- lib/Target/X86/X86InstrFoldTables.cpp | 5412 ++++++ lib/Target/X86/X86InstrFoldTables.h | 85 + lib/Target/X86/X86InstrFormats.td | 31 +- lib/Target/X86/X86InstrFragmentsSIMD.td | 92 +- lib/Target/X86/X86InstrInfo.cpp | 4883 +---- lib/Target/X86/X86InstrInfo.h | 105 +- lib/Target/X86/X86InstrInfo.td | 498 +- lib/Target/X86/X86InstrMMX.td | 272 +- lib/Target/X86/X86InstrMPX.td | 60 +- lib/Target/X86/X86InstrSGX.td | 6 +- lib/Target/X86/X86InstrSSE.td | 3240 ++-- lib/Target/X86/X86InstrShiftRotate.td | 76 +- lib/Target/X86/X86InstrSystem.td | 208 +- lib/Target/X86/X86InstrVMX.td | 24 +- lib/Target/X86/X86InstrVecCompiler.td | 307 +- lib/Target/X86/X86InstrXOP.td | 197 +- lib/Target/X86/X86InstructionSelector.cpp | 40 +- lib/Target/X86/X86InterleavedAccess.cpp | 20 +- lib/Target/X86/X86IntrinsicsInfo.h | 852 +- lib/Target/X86/X86LegalizerInfo.cpp | 12 +- lib/Target/X86/X86MCInstLower.cpp | 757 +- lib/Target/X86/X86MachineFunctionInfo.h | 2 +- lib/Target/X86/X86MacroFusion.cpp | 26 +- lib/Target/X86/X86OptimizeLEAs.cpp | 31 +- lib/Target/X86/X86PadShortFunction.cpp | 2 +- lib/Target/X86/X86PfmCounters.td | 22 +- lib/Target/X86/X86RegisterBankInfo.cpp | 11 + lib/Target/X86/X86RegisterInfo.cpp | 7 +- lib/Target/X86/X86RegisterInfo.td | 114 +- lib/Target/X86/X86RetpolineThunks.cpp | 11 +- lib/Target/X86/X86SchedBroadwell.td | 1406 +- lib/Target/X86/X86SchedHaswell.td | 1600 +- lib/Target/X86/X86SchedPredicates.td | 56 + lib/Target/X86/X86SchedSandyBridge.td | 1354 +- lib/Target/X86/X86SchedSkylakeClient.td | 1719 +- lib/Target/X86/X86SchedSkylakeServer.td | 4057 +--- lib/Target/X86/X86Schedule.td | 530 +- lib/Target/X86/X86ScheduleAtom.td | 477 +- lib/Target/X86/X86ScheduleBtVer2.td | 911 +- lib/Target/X86/X86ScheduleSLM.td | 417 +- lib/Target/X86/X86ScheduleZnver1.td | 914 +- lib/Target/X86/X86SpeculativeLoadHardening.cpp | 2247 +++ lib/Target/X86/X86Subtarget.cpp | 157 +- lib/Target/X86/X86Subtarget.h | 227 +- lib/Target/X86/X86TargetMachine.cpp | 27 +- lib/Target/X86/X86TargetObjectFile.cpp | 97 - lib/Target/X86/X86TargetObjectFile.h | 21 +- lib/Target/X86/X86TargetTransformInfo.cpp | 201 +- lib/Target/X86/X86VZeroUpper.cpp | 8 +- lib/Target/X86/X86WinEHState.cpp | 12 +- .../XCore/Disassembler/XCoreDisassembler.cpp | 4 +- lib/Target/XCore/InstPrinter/XCoreInstPrinter.h | 2 +- lib/Target/XCore/XCoreAsmPrinter.cpp | 6 +- lib/Target/XCore/XCoreFrameLowering.cpp | 2 +- lib/Target/XCore/XCoreISelDAGToDAG.cpp | 5 +- lib/Target/XCore/XCoreISelLowering.cpp | 4 - lib/Target/XCore/XCoreInstrInfo.cpp | 42 +- lib/Target/XCore/XCoreLowerThreadLocal.cpp | 2 +- lib/Target/XCore/XCoreMCInstLower.cpp | 2 +- lib/Target/XCore/XCoreMCInstLower.h | 2 +- lib/Target/XCore/XCoreMachineFunctionInfo.h | 6 +- lib/Target/XCore/XCoreRegisterInfo.cpp | 22 +- lib/Target/XCore/XCoreRegisterInfo.h | 2 +- lib/Target/XCore/XCoreSubtarget.h | 2 +- lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp | 4 +- lib/ToolDrivers/llvm-lib/LibDriver.cpp | 6 + lib/ToolDrivers/llvm-lib/Options.td | 6 +- .../AggressiveInstCombine.cpp | 170 +- .../AggressiveInstCombine/TruncInstCombine.cpp | 7 +- lib/Transforms/Coroutines/CoroElide.cpp | 50 +- lib/Transforms/Coroutines/CoroFrame.cpp | 33 +- lib/Transforms/Coroutines/CoroSplit.cpp | 8 +- lib/Transforms/Coroutines/Coroutines.cpp | 19 +- lib/Transforms/IPO/AlwaysInliner.cpp | 6 +- lib/Transforms/IPO/ArgumentPromotion.cpp | 36 +- lib/Transforms/IPO/BarrierNoopPass.cpp | 2 +- lib/Transforms/IPO/BlockExtractor.cpp | 9 +- lib/Transforms/IPO/CalledValuePropagation.cpp | 30 +- lib/Transforms/IPO/ConstantMerge.cpp | 108 +- lib/Transforms/IPO/DeadArgumentElimination.cpp | 50 +- lib/Transforms/IPO/ExtractGV.cpp | 2 +- lib/Transforms/IPO/ForceFunctionAttrs.cpp | 4 +- lib/Transforms/IPO/FunctionAttrs.cpp | 79 +- lib/Transforms/IPO/FunctionImport.cpp | 402 +- lib/Transforms/IPO/GlobalOpt.cpp | 212 +- lib/Transforms/IPO/IPConstantPropagation.cpp | 16 +- lib/Transforms/IPO/InlineSimple.cpp | 2 +- lib/Transforms/IPO/Inliner.cpp | 210 +- lib/Transforms/IPO/Internalize.cpp | 6 +- lib/Transforms/IPO/LowerTypeTests.cpp | 232 +- lib/Transforms/IPO/MergeFunctions.cpp | 262 +- lib/Transforms/IPO/PartialInlining.cpp | 15 +- lib/Transforms/IPO/PassManagerBuilder.cpp | 45 +- lib/Transforms/IPO/PruneEH.cpp | 6 +- lib/Transforms/IPO/SampleProfile.cpp | 257 +- lib/Transforms/IPO/StripSymbols.cpp | 2 +- lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 49 +- lib/Transforms/IPO/WholeProgramDevirt.cpp | 13 +- lib/Transforms/InstCombine/CMakeLists.txt | 4 + lib/Transforms/InstCombine/InstCombineAddSub.cpp | 543 +- lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 351 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 863 +- lib/Transforms/InstCombine/InstCombineCasts.cpp | 154 +- lib/Transforms/InstCombine/InstCombineCompares.cpp | 208 +- lib/Transforms/InstCombine/InstCombineInternal.h | 157 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 100 +- .../InstCombine/InstCombineMulDivRem.cpp | 259 +- lib/Transforms/InstCombine/InstCombinePHI.cpp | 23 +- lib/Transforms/InstCombine/InstCombineSelect.cpp | 308 +- lib/Transforms/InstCombine/InstCombineShifts.cpp | 69 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 307 +- lib/Transforms/InstCombine/InstCombineTables.td | 11 + .../InstCombine/InstCombineVectorOps.cpp | 215 +- .../InstCombine/InstructionCombining.cpp | 165 +- .../Instrumentation/AddressSanitizer.cpp | 111 +- lib/Transforms/Instrumentation/BoundsChecking.cpp | 114 +- lib/Transforms/Instrumentation/CFGMST.h | 16 +- lib/Transforms/Instrumentation/CGProfile.cpp | 100 + lib/Transforms/Instrumentation/CMakeLists.txt | 1 + .../Instrumentation/DataFlowSanitizer.cpp | 5 +- .../Instrumentation/EfficiencySanitizer.cpp | 4 +- lib/Transforms/Instrumentation/GCOVProfiling.cpp | 301 +- .../Instrumentation/HWAddressSanitizer.cpp | 56 +- .../Instrumentation/IndirectCallPromotion.cpp | 28 +- lib/Transforms/Instrumentation/InstrProfiling.cpp | 29 +- lib/Transforms/Instrumentation/MemorySanitizer.cpp | 497 +- .../Instrumentation/PGOInstrumentation.cpp | 60 +- lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp | 72 +- .../Instrumentation/SanitizerCoverage.cpp | 16 +- lib/Transforms/Instrumentation/ThreadSanitizer.cpp | 8 +- lib/Transforms/ObjCARC/BlotMapVector.h | 2 +- lib/Transforms/ObjCARC/DependencyAnalysis.h | 2 +- lib/Transforms/ObjCARC/ObjCARC.h | 4 +- lib/Transforms/ObjCARC/ObjCARCAPElim.cpp | 12 +- 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lib/Transforms/Scalar/GVNHoist.cpp | 20 +- lib/Transforms/Scalar/GVNSink.cpp | 31 +- lib/Transforms/Scalar/GuardWidening.cpp | 342 +- lib/Transforms/Scalar/IndVarSimplify.cpp | 53 +- .../Scalar/InductiveRangeCheckElimination.cpp | 120 +- lib/Transforms/Scalar/InferAddressSpaces.cpp | 16 +- lib/Transforms/Scalar/InstSimplifyPass.cpp | 144 + lib/Transforms/Scalar/JumpThreading.cpp | 226 +- lib/Transforms/Scalar/LICM.cpp | 350 +- lib/Transforms/Scalar/LoopDataPrefetch.cpp | 12 +- lib/Transforms/Scalar/LoopDeletion.cpp | 25 +- lib/Transforms/Scalar/LoopDistribute.cpp | 125 +- lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 124 +- lib/Transforms/Scalar/LoopInstSimplify.cpp | 221 + lib/Transforms/Scalar/LoopInterchange.cpp | 393 +- lib/Transforms/Scalar/LoopLoadElimination.cpp | 81 +- lib/Transforms/Scalar/LoopPredication.cpp | 92 +- lib/Transforms/Scalar/LoopRerollPass.cpp | 359 +- lib/Transforms/Scalar/LoopSimplifyCFG.cpp | 23 +- lib/Transforms/Scalar/LoopSink.cpp | 20 +- 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lib/Transforms/Scalar/SimplifyCFGPass.cpp | 2 +- lib/Transforms/Scalar/Sink.cpp | 10 +- lib/Transforms/Scalar/SpeculateAroundPHIs.cpp | 61 +- lib/Transforms/Scalar/SpeculativeExecution.cpp | 10 +- .../Scalar/StraightLineStrengthReduce.cpp | 2 +- lib/Transforms/Scalar/StructurizeCFG.cpp | 99 +- lib/Transforms/Scalar/TailRecursionElimination.cpp | 86 +- lib/Transforms/Utils/AddDiscriminators.cpp | 8 +- lib/Transforms/Utils/BasicBlockUtils.cpp | 97 +- lib/Transforms/Utils/BuildLibCalls.cpp | 132 +- lib/Transforms/Utils/BypassSlowDivision.cpp | 4 +- lib/Transforms/Utils/CMakeLists.txt | 3 +- lib/Transforms/Utils/CallPromotionUtils.cpp | 12 +- lib/Transforms/Utils/CloneFunction.cpp | 50 +- lib/Transforms/Utils/CloneModule.cpp | 4 +- lib/Transforms/Utils/CodeExtractor.cpp | 143 +- lib/Transforms/Utils/CtorUtils.cpp | 2 +- lib/Transforms/Utils/DemoteRegToStack.cpp | 2 +- lib/Transforms/Utils/EscapeEnumerator.cpp | 6 +- lib/Transforms/Utils/Evaluator.cpp | 220 +- lib/Transforms/Utils/FlattenCFG.cpp | 12 +- lib/Transforms/Utils/FunctionComparator.cpp | 7 +- .../Utils/ImplicitControlFlowTracking.cpp | 93 + lib/Transforms/Utils/InlineFunction.cpp | 47 +- lib/Transforms/Utils/IntegerDivision.cpp | 22 +- lib/Transforms/Utils/LCSSA.cpp | 26 +- lib/Transforms/Utils/LibCallsShrinkWrap.cpp | 22 +- lib/Transforms/Utils/Local.cpp | 736 +- lib/Transforms/Utils/LoopRotationUtils.cpp | 33 +- lib/Transforms/Utils/LoopSimplify.cpp | 38 +- lib/Transforms/Utils/LoopUnroll.cpp | 146 +- lib/Transforms/Utils/LoopUnrollAndJam.cpp | 809 + lib/Transforms/Utils/LoopUnrollPeel.cpp | 35 +- lib/Transforms/Utils/LoopUnrollRuntime.cpp | 34 +- lib/Transforms/Utils/LoopUtils.cpp | 69 +- lib/Transforms/Utils/LoopVersioning.cpp | 11 +- lib/Transforms/Utils/LowerInvoke.cpp | 6 +- lib/Transforms/Utils/LowerSwitch.cpp | 78 +- lib/Transforms/Utils/MetaRenamer.cpp | 2 +- lib/Transforms/Utils/OrderedInstructions.cpp | 33 +- lib/Transforms/Utils/PredicateInfo.cpp | 86 +- lib/Transforms/Utils/PromoteMemoryToRegister.cpp | 37 +- lib/Transforms/Utils/SSAUpdater.cpp | 40 +- lib/Transforms/Utils/SSAUpdaterBulk.cpp | 20 +- lib/Transforms/Utils/SimplifyCFG.cpp | 231 +- lib/Transforms/Utils/SimplifyIndVar.cpp | 168 +- lib/Transforms/Utils/SimplifyInstructions.cpp | 152 - lib/Transforms/Utils/SimplifyLibCalls.cpp | 818 +- lib/Transforms/Utils/SplitModule.cpp | 12 +- lib/Transforms/Utils/SymbolRewriter.cpp | 2 +- lib/Transforms/Utils/UnifyFunctionExitNodes.cpp | 2 +- lib/Transforms/Utils/Utils.cpp | 1 - lib/Transforms/Utils/VNCoercion.cpp | 12 +- lib/Transforms/Vectorize/CMakeLists.txt | 4 + lib/Transforms/Vectorize/LoadStoreVectorizer.cpp | 218 +- .../Vectorize/LoopVectorizationLegality.cpp | 1073 ++ .../Vectorize/LoopVectorizationPlanner.h | 211 +- lib/Transforms/Vectorize/LoopVectorize.cpp | 2255 +-- lib/Transforms/Vectorize/SLPVectorizer.cpp | 1055 +- lib/Transforms/Vectorize/VPRecipeBuilder.h | 131 + lib/Transforms/Vectorize/VPlan.cpp | 42 +- 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test/CodeGen/AMDGPU/or.ll | 18 +- test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 261 +- test/CodeGen/AMDGPU/partial-shift-shrink.ll | 138 + test/CodeGen/AMDGPU/perfhint.ll | 111 + test/CodeGen/AMDGPU/permute.ll | 221 + test/CodeGen/AMDGPU/print-mir-custom-pseudo.ll | 4 +- test/CodeGen/AMDGPU/private-element-size.ll | 6 +- .../AMDGPU/promote-alloca-invariant-markers.ll | 4 +- test/CodeGen/AMDGPU/r600.extract-lowbits.ll | 430 + test/CodeGen/AMDGPU/r600.func-alignment.ll | 13 + test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll | 9 +- test/CodeGen/AMDGPU/rcp_iflag.ll | 21 + .../reduce-build-vec-ext-to-ext-build-vec.ll | 20 + .../CodeGen/AMDGPU/reduce-store-width-alignment.ll | 8 +- test/CodeGen/AMDGPU/reduction.ll | 509 + test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir | 239 + test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 2 +- test/CodeGen/AMDGPU/rename-independent-subregs.mir | 18 + test/CodeGen/AMDGPU/reqd-work-group-size.ll | 501 + test/CodeGen/AMDGPU/ret.ll | 6 + test/CodeGen/AMDGPU/rewrite-out-arguments.ll | 2 +- test/CodeGen/AMDGPU/sad.ll | 36 +- test/CodeGen/AMDGPU/scalar-store-cache-flush.mir | 2 +- test/CodeGen/AMDGPU/scalar_to_vector.ll | 33 + test/CodeGen/AMDGPU/sched-crash-dbg-value.mir | 3 +- test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll | 15 +- test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll | 15 +- test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll | 591 + test/CodeGen/AMDGPU/sdiv.ll | 6 +- test/CodeGen/AMDGPU/sdivrem24.ll | 18 +- test/CodeGen/AMDGPU/sdwa-peephole.ll | 6 +- test/CodeGen/AMDGPU/select-i1.ll | 30 +- test/CodeGen/AMDGPU/select-opt.ll | 5 +- test/CodeGen/AMDGPU/select-vectors.ll | 32 +- test/CodeGen/AMDGPU/select.f16.ll | 46 +- test/CodeGen/AMDGPU/setcc-opt.ll | 14 +- test/CodeGen/AMDGPU/setcc.ll | 4 +- test/CodeGen/AMDGPU/sext-in-reg.ll | 9 +- test/CodeGen/AMDGPU/sgpr-control-flow.ll | 24 +- test/CodeGen/AMDGPU/sgpr-copy.ll | 31 +- test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 97 + test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll | 104 + test/CodeGen/AMDGPU/shift-i128.ll | 1047 ++ test/CodeGen/AMDGPU/shl.ll | 8 +- test/CodeGen/AMDGPU/shl.v2i16.ll | 36 +- test/CodeGen/AMDGPU/shl_add_constant.ll | 20 +- test/CodeGen/AMDGPU/si-annotate-cf.ll | 34 +- test/CodeGen/AMDGPU/si-lod-bias.ll | 59 - test/CodeGen/AMDGPU/si-lower-control-flow-kill.ll | 10 +- test/CodeGen/AMDGPU/si-lower-control-flow.mir | 23 + test/CodeGen/AMDGPU/si-scheduler.ll | 9 +- test/CodeGen/AMDGPU/si-sgpr-spill.ll | 234 +- test/CodeGen/AMDGPU/sign_extend.ll | 18 +- test/CodeGen/AMDGPU/skip-if-dead.ll | 16 +- test/CodeGen/AMDGPU/smed3.ll | 4 +- test/CodeGen/AMDGPU/sminmax.ll | 2 +- test/CodeGen/AMDGPU/sminmax.v2i16.ll | 71 +- test/CodeGen/AMDGPU/smrd.ll | 5 +- test/CodeGen/AMDGPU/spill-m0.ll | 4 +- test/CodeGen/AMDGPU/spill-offset-calculation.ll | 213 + test/CodeGen/AMDGPU/split-smrd.ll | 4 +- test/CodeGen/AMDGPU/sra.ll | 14 +- test/CodeGen/AMDGPU/srl.ll | 8 +- test/CodeGen/AMDGPU/store-global.ll | 48 +- test/CodeGen/AMDGPU/store-hi16.ll | 267 +- test/CodeGen/AMDGPU/store-private.ll | 8 +- test/CodeGen/AMDGPU/store-v3i64.ll | 6 +- test/CodeGen/AMDGPU/store-weird-sizes.ll | 22 +- test/CodeGen/AMDGPU/stress-calls.ll | 2 +- test/CodeGen/AMDGPU/sub.ll | 6 +- test/CodeGen/AMDGPU/sub.v2i16.ll | 86 +- test/CodeGen/AMDGPU/subreg-coalescer-crash.ll | 4 +- test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 25 +- test/CodeGen/AMDGPU/subreg-split-live-in-error.mir | 273 + test/CodeGen/AMDGPU/trap.ll | 40 +- test/CodeGen/AMDGPU/trunc-bitcast-vector.ll | 53 +- test/CodeGen/AMDGPU/trunc-combine.ll | 82 + test/CodeGen/AMDGPU/trunc-store-i1.ll | 31 +- test/CodeGen/AMDGPU/trunc.ll | 16 +- test/CodeGen/AMDGPU/twoaddr-mad.mir | 4 +- test/CodeGen/AMDGPU/udiv.ll | 6 +- test/CodeGen/AMDGPU/udivrem.ll | 34 +- test/CodeGen/AMDGPU/udivrem24.ll | 14 +- test/CodeGen/AMDGPU/uint_to_fp.ll | 6 +- test/CodeGen/AMDGPU/umed3.ll | 4 +- test/CodeGen/AMDGPU/unaligned-load-store.ll | 2 +- .../AMDGPU/undefined-physreg-sgpr-spill.mir | 6 +- test/CodeGen/AMDGPU/undefined-subreg-liverange.ll | 7 +- test/CodeGen/AMDGPU/uniform-PHI.ll | 39 - test/CodeGen/AMDGPU/uniform-cfg.ll | 17 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 4 +- test/CodeGen/AMDGPU/unigine-liveness-crash.ll | 30 +- test/CodeGen/AMDGPU/unsupported-calls.ll | 7 + test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll | 79 +- test/CodeGen/AMDGPU/v_cndmask.ll | 25 +- test/CodeGen/AMDGPU/v_mac_f16.ll | 18 +- test/CodeGen/AMDGPU/v_madak_f16.ll | 6 +- test/CodeGen/AMDGPU/valu-i1.ll | 11 +- .../CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | 12 +- test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll | 27 + test/CodeGen/AMDGPU/vector-alloca-atomic.ll | 65 + test/CodeGen/AMDGPU/vector-legalizer-divergence.ll | 30 + test/CodeGen/AMDGPU/vop-shrink-frame-index.mir | 24 +- test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir | 34 + test/CodeGen/AMDGPU/waitcnt-debug.mir | 41 + test/CodeGen/AMDGPU/waitcnt-permute.mir | 2 +- test/CodeGen/AMDGPU/waitcnt.mir | 22 +- test/CodeGen/AMDGPU/widen-smrd-loads.ll | 169 + .../CodeGen/AMDGPU/widen_extending_scalar_loads.ll | 76 + test/CodeGen/AMDGPU/wqm.ll | 158 +- test/CodeGen/AMDGPU/xnor.ll | 6 +- test/CodeGen/AMDGPU/xor.ll | 40 +- test/CodeGen/AMDGPU/zero_extend.ll | 44 +- test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll | 40 +- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 10 +- test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 10 +- .../ARM/2013-05-13-DAGCombiner-undef-mask.ll | 17 +- .../CodeGen/ARM/2016-08-24-ARM-LDST-dbginfo-bug.ll | 2 +- test/CodeGen/ARM/ARMLoadStoreDBG.mir | 2 +- .../ARM/GlobalISel/arm-instruction-select-cmp.mir | 2 +- .../GlobalISel/arm-instruction-select-combos.mir | 2 +- .../ARM/GlobalISel/arm-instruction-select.mir | 2 +- test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 11 +- .../CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 8 +- test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 6 +- test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir | 14 +- test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 2 +- test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll | 116 +- test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 2 +- .../ARM/GlobalISel/arm-select-globals-pic.mir | 8 +- .../GlobalISel/arm-select-globals-ropi-rwpi.mir | 12 +- .../ARM/GlobalISel/arm-select-globals-static.mir | 8 +- test/CodeGen/ARM/GlobalISel/select-pr35926.mir | 2 +- test/CodeGen/ARM/Windows/alloca.ll | 2 +- test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll | 2 +- test/CodeGen/ARM/Windows/vla.ll | 4 +- test/CodeGen/ARM/a15-SD-dep.ll | 26 +- test/CodeGen/ARM/add-like-or.ll | 41 + test/CodeGen/ARM/aggregate-padding.ll | 16 + test/CodeGen/ARM/alias_align.ll | 25 + test/CodeGen/ARM/and-cmpz.ll | 38 + test/CodeGen/ARM/arm-cgp-calls.ll | 184 + test/CodeGen/ARM/arm-cgp-icmps.ll | 281 + test/CodeGen/ARM/arm-cgp-overflow.ll | 49 + test/CodeGen/ARM/arm-cgp-phis-ret.ll | 174 + test/CodeGen/ARM/arm-cgp-pointers.ll | 135 + test/CodeGen/ARM/arm-cgp-signed-icmps.ll | 100 + test/CodeGen/ARM/arm-cgp-signed.ll | 45 + test/CodeGen/ARM/arm-cgp-zext-truncs.ll | 297 + test/CodeGen/ARM/arm-shrink-wrapping-linux.ll | 6 +- test/CodeGen/ARM/arm-vld1.ll | 242 + test/CodeGen/ARM/arm-vlddup-update.ll | 43 + test/CodeGen/ARM/arm-vlddup.ll | 234 + test/CodeGen/ARM/arm-vst1.ll | 363 + .../CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll | 1285 ++ test/CodeGen/ARM/atomic-op.ll | 4 +- test/CodeGen/ARM/build-attributes.ll | 47 +- test/CodeGen/ARM/cmn.ll | 51 +- test/CodeGen/ARM/coalesce-dbgvalue.ll | 2 +- test/CodeGen/ARM/constantpool-promote-dbg.ll | 4 +- test/CodeGen/ARM/cortexr52-misched-basic.ll | 2 +- test/CodeGen/ARM/darwin-eabi.ll | 2 +- test/CodeGen/ARM/dbg-range-extension.mir | 2 +- test/CodeGen/ARM/debug-frame-large-stack.ll | 1 + test/CodeGen/ARM/debug-frame-vararg.ll | 2 +- test/CodeGen/ARM/debug-frame.ll | 2 +- test/CodeGen/ARM/debug-info-arg.ll | 2 +- test/CodeGen/ARM/debug-info-branch-folding.ll | 14 +- test/CodeGen/ARM/debug-info-d16-reg.ll | 6 +- test/CodeGen/ARM/debug-info-no-frame.ll | 2 +- test/CodeGen/ARM/debug-info-qreg.ll | 10 +- test/CodeGen/ARM/debug-info-s16-reg.ll | 6 +- test/CodeGen/ARM/debug-info-sreg2.ll | 2 +- test/CodeGen/ARM/debug-segmented-stacks.ll | 2 +- test/CodeGen/ARM/early-cfi-sections.ll | 2 +- test/CodeGen/ARM/float-helpers.s | 8 +- test/CodeGen/ARM/fnmul.ll | 12 +- test/CodeGen/ARM/fold-sext-sextload.ll | 38 + test/CodeGen/ARM/fold-zext-zextload.ll | 38 + test/CodeGen/ARM/fp16-instructions.ll | 2 +- test/CodeGen/ARM/fp16-litpool2-arm.mir | 3 +- test/CodeGen/ARM/fp16-litpool3-arm.mir | 3 +- test/CodeGen/ARM/fp16-promote.ll | 6 +- test/CodeGen/ARM/fp16-vminmaxnm-vector.ll | 302 + test/CodeGen/ARM/fp16.ll | 2 +- test/CodeGen/ARM/func-argpassing-endian.ll | 270 +- test/CodeGen/ARM/global-merge-1.ll | 6 +- test/CodeGen/ARM/global-merge-alignment.ll | 24 + test/CodeGen/ARM/global-merge.ll | 8 +- test/CodeGen/ARM/ifcvt10.ll | 19 +- test/CodeGen/ARM/illegal-bitfield-loadstore.ll | 4 +- test/CodeGen/ARM/indirectbr.ll | 2 +- test/CodeGen/ARM/inlineasm-64bit.ll | 8 + .../CodeGen/ARM/inlineasm-operand-implicit-cast.ll | 307 + test/CodeGen/ARM/invalid-target.ll | 16 +- test/CodeGen/ARM/large-vector.ll | 47 + test/CodeGen/ARM/ldrd.ll | 52 + test/CodeGen/ARM/load_i1_select.ll | 2 +- test/CodeGen/ARM/machine-cse-cmp.ll | 4 +- test/CodeGen/ARM/macho-embedded-float.ll | 37 + test/CodeGen/ARM/memcpy-inline.ll | 7 +- test/CodeGen/ARM/misched-fusion-lit.ll | 39 + test/CodeGen/ARM/neon-dot-product.ll | 82 + .../ARM/overflow-intrinsic-optimizations.ll | 5 + test/CodeGen/ARM/reg_sequence.ll | 24 +- test/CodeGen/ARM/relax-per-target-feature.ll | 34 + test/CodeGen/ARM/sched-it-debug-nodes.mir | 2 +- test/CodeGen/ARM/segmented-stacks.ll | 18 + test/CodeGen/ARM/select_const.ll | 5 +- test/CodeGen/ARM/shift-combine.ll | 4 +- test/CodeGen/ARM/smlad0.ll | 132 + test/CodeGen/ARM/smlad1.ll | 95 + test/CodeGen/ARM/smlad10.ll | 47 + test/CodeGen/ARM/smlad11.ll | 76 + test/CodeGen/ARM/smlad12.ll | 48 + test/CodeGen/ARM/smlad2.ll | 51 + test/CodeGen/ARM/smlad3.ll | 50 + test/CodeGen/ARM/smlad4.ll | 48 + test/CodeGen/ARM/smlad5.ll | 44 + test/CodeGen/ARM/smlad6.ll | 50 + test/CodeGen/ARM/smlad7.ll | 53 + test/CodeGen/ARM/smlad8.ll | 59 + test/CodeGen/ARM/smlad9.ll | 45 + test/CodeGen/ARM/smml.ll | 14 +- test/CodeGen/ARM/spill-q.ll | 8 +- test/CodeGen/ARM/stack-size-section.ll | 4 +- test/CodeGen/ARM/sub-cmp-peephole.ll | 4 +- .../CodeGen/ARM/umulo-128-legalisation-lowering.ll | 210 + test/CodeGen/ARM/umulo-64-legalisation-lowering.ll | 69 + test/CodeGen/ARM/unaligned_load_store_vector.ll | 8 + test/CodeGen/ARM/useaa.ll | 26 + test/CodeGen/ARM/v8m-tail-call.ll | 167 +- test/CodeGen/ARM/vector-load.ll | 2 +- test/CodeGen/ARM/vfcmp.ll | 110 +- test/CodeGen/ARM/vfp-reg-stride.ll | 23 +- test/CodeGen/ARM/vfp-regs-dwarf.ll | 2 +- test/CodeGen/ARM/vtrn.ll | 200 +- test/CodeGen/ARM/vuzp.ll | 34 +- test/CodeGen/ARM/wide-compares.ll | 97 +- test/CodeGen/AVR/rust-avr-bug-99.ll | 336 + test/CodeGen/BPF/dwarfdump.ll | 2 +- test/CodeGen/BPF/memcpy-expand-in-order.ll | 116 + test/CodeGen/BPF/warn-call.ll | 4 +- test/CodeGen/BPF/warn-stack.ll | 4 +- test/CodeGen/Generic/cfi-sections.ll | 2 +- test/CodeGen/Generic/dwarf-md5.ll | 20 +- test/CodeGen/Generic/dwarf-source.ll | 16 +- test/CodeGen/Generic/intrinsics.ll | 14 +- test/CodeGen/Hexagon/BranchPredict.ll | 2 +- test/CodeGen/Hexagon/SUnit-boundary-prob.ll | 323 +- test/CodeGen/Hexagon/abs.ll | 83 + test/CodeGen/Hexagon/adde.ll | 27 - test/CodeGen/Hexagon/addsubcarry.ll | 25 + test/CodeGen/Hexagon/autohvx/align-128b.ll | 21 +- test/CodeGen/Hexagon/autohvx/align-64b.ll | 21 +- test/CodeGen/Hexagon/autohvx/align2-128b.ll | 21 +- test/CodeGen/Hexagon/autohvx/align2-64b.ll | 21 +- test/CodeGen/Hexagon/autohvx/bitcount-128b.ll | 124 + test/CodeGen/Hexagon/autohvx/bitcount-64b.ll | 125 + test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll | 95 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test/CodeGen/Hexagon/autohvx/isel-truncate.ll | 5 +- test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll | 12 +- test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll | 6 +- test/CodeGen/Hexagon/autohvx/shift-128b.ll | 320 +- test/CodeGen/Hexagon/autohvx/shift-64b.ll | 177 +- test/CodeGen/Hexagon/autohvx/vdd0.ll | 41 + .../CodeGen/Hexagon/autohvx/vector-compare-128b.ll | 297 + test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll | 298 + .../CodeGen/Hexagon/avoid-predspill-calleesaved.ll | 2 +- test/CodeGen/Hexagon/bit-bitsplit-at.ll | 10 +- test/CodeGen/Hexagon/bit-cmp0.mir | 154 + test/CodeGen/Hexagon/bit-extract-off.ll | 4 +- test/CodeGen/Hexagon/bit-has.ll | 2 +- test/CodeGen/Hexagon/bitconvert-vector.ll | 8 +- test/CodeGen/Hexagon/build-vector-shuffle.ll | 14 +- test/CodeGen/Hexagon/callR_noreturn.ll | 9 +- test/CodeGen/Hexagon/cext-check.ll | 2 +- test/CodeGen/Hexagon/cext-unnamed-global.mir | 38 + test/CodeGen/Hexagon/cfgopt-fall-through.ll | 2 +- .../Hexagon/cfi-late-and-regpressure-init.ll | 2 +- test/CodeGen/Hexagon/cfi-late.ll | 2 +- .../CodeGen/Hexagon/coalescing-hvx-across-calls.ll | 26 + test/CodeGen/Hexagon/convert_const_i1_to_i8.ll | 6 +- test/CodeGen/Hexagon/copy-to-combine-dbg.ll | 71 +- test/CodeGen/Hexagon/dealloc-store.ll | 2 +- test/CodeGen/Hexagon/debug-line_table_start.ll | 2 +- test/CodeGen/Hexagon/debug-prologue-loc.ll | 4 +- test/CodeGen/Hexagon/debug-prologue.ll | 2 +- test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll | 67 +- .../CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll | 26 - test/CodeGen/Hexagon/dwarf-discriminator.ll | 4 +- test/CodeGen/Hexagon/expand-condsets-dead-bad.ll | 2 +- test/CodeGen/Hexagon/expand-condsets-dead-pred.ll | 2 +- test/CodeGen/Hexagon/expand-condsets-impuse2.mir | 25 + test/CodeGen/Hexagon/expand-condsets-phys-reg.mir | 30 + test/CodeGen/Hexagon/expand-vselect-kill.ll | 53 - test/CodeGen/Hexagon/expand-vselect-kill.mir | 14 + test/CodeGen/Hexagon/expand-vstorerw-undef.ll | 2 +- test/CodeGen/Hexagon/feature-memops.ll | 23 + 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test/CodeGen/X86/avx512dqvl-intrinsics.ll | 888 +- test/CodeGen/X86/avx512er-intrinsics.ll | 201 +- .../CodeGen/X86/avx512ifma-intrinsics-fast-isel.ll | 108 + test/CodeGen/X86/avx512ifma-intrinsics-upgrade.ll | 437 + test/CodeGen/X86/avx512ifma-intrinsics.ll | 549 +- .../X86/avx512ifmavl-intrinsics-fast-isel.ll | 218 + .../CodeGen/X86/avx512ifmavl-intrinsics-upgrade.ll | 355 + test/CodeGen/X86/avx512ifmavl-intrinsics.ll | 555 +- .../CodeGen/X86/avx512vbmi-intrinsics-fast-isel.ll | 98 + test/CodeGen/X86/avx512vbmi-intrinsics-upgrade.ll | 119 + test/CodeGen/X86/avx512vbmi-intrinsics.ll | 204 +- .../X86/avx512vbmi2-intrinsics-fast-isel.ll | 985 + test/CodeGen/X86/avx512vbmi2-intrinsics-upgrade.ll | 421 + test/CodeGen/X86/avx512vbmi2-intrinsics.ll | 557 +- .../X86/avx512vbmi2vl-intrinsics-fast-isel.ll | 1975 ++ .../X86/avx512vbmi2vl-intrinsics-upgrade.ll | 668 + test/CodeGen/X86/avx512vbmi2vl-intrinsics.ll | 1323 +- .../X86/avx512vbmivl-intrinsics-fast-isel.ll | 178 + .../CodeGen/X86/avx512vbmivl-intrinsics-upgrade.ll | 235 + test/CodeGen/X86/avx512vbmivl-intrinsics.ll | 395 +- test/CodeGen/X86/avx512vl-intrinsics-canonical.ll | 1816 ++ test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll | 7198 ++++++-- test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 13477 +++++++++++--- test/CodeGen/X86/avx512vl-intrinsics.ll | 8747 ++++++--- test/CodeGen/X86/avx512vl-mov.ll | 8 +- test/CodeGen/X86/avx512vl-vec-masked-cmp.ll | 26 +- test/CodeGen/X86/avx512vl-vpclmulqdq.ll | 19 +- .../X86/avx512vl_vnni-intrinsics-upgrade.ll | 309 + test/CodeGen/X86/avx512vl_vnni-intrinsics.ll | 437 +- .../CodeGen/X86/avx512vlcd-intrinsics-fast-isel.ll | 45 +- test/CodeGen/X86/avx512vnni-intrinsics-upgrade.ll | 152 + test/CodeGen/X86/avx512vnni-intrinsics.ll | 212 +- test/CodeGen/X86/avx512vpopcntdq-intrinsics.ll | 54 +- test/CodeGen/X86/avx512vpopcntdq-schedule.ll | 72 +- test/CodeGen/X86/backpropmask.ll | 51 + test/CodeGen/X86/bit-piece-comment.ll | 2 +- test/CodeGen/X86/bitcast-and-setcc-128.ll | 40 +- test/CodeGen/X86/bitcast-setcc-128.ll | 20 +- test/CodeGen/X86/block-placement.ll | 5 +- test/CodeGen/X86/bmi-schedule.ll | 62 - test/CodeGen/X86/bmi-x86_64.ll | 86 + test/CodeGen/X86/bmi.ll | 1035 +- test/CodeGen/X86/bmi2-schedule.ll | 16 +- test/CodeGen/X86/bmi2-x86_64.ll | 102 + test/CodeGen/X86/bmi2.ll | 206 +- test/CodeGen/X86/bool-math.ll | 166 + test/CodeGen/X86/break-false-dep.ll | 25 +- test/CodeGen/X86/broadcastm-lowering.ll | 7 +- test/CodeGen/X86/btc_bts_btr.ll | 934 + test/CodeGen/X86/bug37521.ll | 29 + test/CodeGen/X86/build-vector-512.ll | 8 +- test/CodeGen/X86/buildvec-insertvec.ll | 10 +- test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir | 17 + .../cfi-inserter-verify-inconsistent-offset.mir | 26 + .../cfi-inserter-verify-inconsistent-register.mir | 26 + test/CodeGen/X86/cleanuppad-large-codemodel.ll | 2 +- test/CodeGen/X86/clear-highbits.ll | 970 + test/CodeGen/X86/clear-lowbits.ll | 1808 ++ test/CodeGen/X86/clzero-schedule.ll | 2 +- test/CodeGen/X86/cmov.ll | 5 +- test/CodeGen/X86/coalesce_commute_movsd.ll | 4 +- test/CodeGen/X86/code-model-elf-memset.ll | 91 + test/CodeGen/X86/code-model-elf.ll | 384 + test/CodeGen/X86/code-model-kernel.ll | 79 + test/CodeGen/X86/combine-abs.ll | 18 +- test/CodeGen/X86/combine-rotates.ll | 315 +- test/CodeGen/X86/combine-sdiv.ll | 2561 ++- test/CodeGen/X86/combine-select.ll | 127 + test/CodeGen/X86/combine-shl.ll | 519 +- test/CodeGen/X86/combine-sra.ll | 69 +- test/CodeGen/X86/combine-srem.ll | 335 + test/CodeGen/X86/combine-srl.ll | 28 +- test/CodeGen/X86/combine-udiv.ll | 352 +- test/CodeGen/X86/combine-urem.ll | 158 +- test/CodeGen/X86/conditional-tailcall-samedest.mir | 4 +- test/CodeGen/X86/copy-eflags.ll | 59 + test/CodeGen/X86/dagcombine-cse.ll | 7 +- test/CodeGen/X86/dagcombine-select.ll | 429 + test/CodeGen/X86/dagcombine-unsafe-math.ll | 58 +- test/CodeGen/X86/dbg-baseptr.ll | 6 +- .../X86/dbg-changes-codegen-branch-folding.ll | 6 +- .../X86/dbg-changes-codegen-branch-folding2.mir | 2 +- test/CodeGen/X86/dbg-combine.ll | 2 +- test/CodeGen/X86/dbg-line-0-no-discriminator.ll | 2 +- test/CodeGen/X86/debug-nodebug-crash.ll | 4 +- test/CodeGen/X86/debugloc-argsize.ll | 2 +- test/CodeGen/X86/debugloc-no-line-0.ll | 2 +- test/CodeGen/X86/deopt-intrinsic-cconv.ll | 1 + test/CodeGen/X86/divide-by-constant.ll | 110 + .../X86/domain-reassignment-implicit-def.ll | 24 + test/CodeGen/X86/domain-reassignment-test.ll | 37 + test/CodeGen/X86/domain-reassignment.mir | 8 +- test/CodeGen/X86/dwarf-headers.ll | 57 +- test/CodeGen/X86/dwarf-split-line-1.ll | 7 +- test/CodeGen/X86/dwarf-split-line-2.ll | 7 +- test/CodeGen/X86/dynamic-regmask.ll | 2 +- test/CodeGen/X86/early-cfi-sections.ll | 2 +- test/CodeGen/X86/eip-addressing-i386.ll | 13 + .../X86/element-wise-atomic-memory-intrinsics.ll | 75 +- test/CodeGen/X86/extend-set-cc-uses-dbg.ll | 48 + test/CodeGen/X86/extract-lowbits.ll | 2310 +++ test/CodeGen/X86/extract-store.ll | 4 +- test/CodeGen/X86/extractelement-load.ll | 8 +- test/CodeGen/X86/f16c-schedule.ll | 22 +- test/CodeGen/X86/fadd-combines.ll | 18 + test/CodeGen/X86/fast-isel-call-cleanup.ll | 4 +- test/CodeGen/X86/fast-isel-fold-mem.ll | 9 +- test/CodeGen/X86/fast-isel-fptrunc-fpext.ll | 6 +- .../X86/fast-isel-int-float-conversion-x86-64.ll | 7 +- test/CodeGen/X86/fast-isel-int-float-conversion.ll | 14 +- test/CodeGen/X86/fast-isel-select.ll | 19 +- test/CodeGen/X86/fast-isel-sext-zext.ll | 40 - .../X86/fast-isel-uint-float-conversion-x86-64.ll | 69 + .../CodeGen/X86/fast-isel-uint-float-conversion.ll | 160 + test/CodeGen/X86/fixed-stack-di-mir.ll | 32 + test/CodeGen/X86/fixup-bw-copy.ll | 2 +- test/CodeGen/X86/flags-copy-lowering.mir | 587 +- test/CodeGen/X86/fma-commute-x86.ll | 32 +- test/CodeGen/X86/fma-fneg-combine.ll | 89 +- test/CodeGen/X86/fma-intrinsics-canonical.ll | 901 + test/CodeGen/X86/fma-intrinsics-fast-isel.ll | 429 + test/CodeGen/X86/fma-intrinsics-x86-upgrade.ll | 1036 ++ test/CodeGen/X86/fma-intrinsics-x86.ll | 462 +- test/CodeGen/X86/fma-scalar-combine.ll | 544 + test/CodeGen/X86/fma-scalar-memfold.ll | 44 +- test/CodeGen/X86/fma-schedule.ll | 216 +- test/CodeGen/X86/fma.ll | 714 +- test/CodeGen/X86/fma4-commute-x86.ll | 12 +- test/CodeGen/X86/fma4-intrinsics-x86-upgrade.ll | 250 + test/CodeGen/X86/fma4-intrinsics-x86.ll | 165 +- test/CodeGen/X86/fma4-scalar-memfold.ll | 4 +- test/CodeGen/X86/fmaxnum.ll | 66 + test/CodeGen/X86/fmf-flags.ll | 54 +- test/CodeGen/X86/fmf-propagation.ll | 30 + test/CodeGen/X86/fminnum.ll | 67 + test/CodeGen/X86/fmsubadd-combine.ll | 22 +- test/CodeGen/X86/fmul-combines.ll | 171 +- test/CodeGen/X86/fold-load-unops.ll | 12 +- test/CodeGen/X86/fold-load-vec.ll | 22 +- test/CodeGen/X86/fold-sext-trunc.ll | 65 +- test/CodeGen/X86/fold-zext-trunc.ll | 57 +- test/CodeGen/X86/fp-fold.ll | 225 + test/CodeGen/X86/fp-intrinsics.ll | 4 +- test/CodeGen/X86/fp-undef.ll | 512 + test/CodeGen/X86/fp128-g.ll | 12 +- test/CodeGen/X86/fp128-i128.ll | 463 +- test/CodeGen/X86/fp128-select.ll | 2 +- test/CodeGen/X86/fpstack-debuginstr-kill.ll | 2 +- test/CodeGen/X86/frame-order.ll | 4 +- test/CodeGen/X86/fsgsbase-schedule.ll | 16 +- test/CodeGen/X86/ftrunc.ll | 28 +- test/CodeGen/X86/funnel-shift-rot.ll | 417 + test/CodeGen/X86/funnel-shift.ll | 456 + test/CodeGen/X86/gather-addresses.ll | 30 +- test/CodeGen/X86/getelementptr.ll | 11 + test/CodeGen/X86/h-registers-1.ll | 16 +- test/CodeGen/X86/haddsub-2.ll | 44 +- test/CodeGen/X86/haddsub-shuf.ll | 362 +- test/CodeGen/X86/half.ll | 98 +- test/CodeGen/X86/hipe-cc64.ll | 2 +- test/CodeGen/X86/hoist-spill.ll | 6 +- test/CodeGen/X86/iabs.ll | 2 +- test/CodeGen/X86/icmp-opt.ll | 27 + test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir | 49 + test/CodeGen/X86/imul.ll | 285 +- test/CodeGen/X86/indirect-branch-tracking.ll | 8 +- test/CodeGen/X86/ins_subreg_coalesce-1.ll | 15 +- test/CodeGen/X86/instr-symbols.mir | 74 + test/CodeGen/X86/invpcid-intrinsic.ll | 43 + test/CodeGen/X86/ipra-inline-asm.ll | 2 +- test/CodeGen/X86/ipra-reg-usage.ll | 2 +- test/CodeGen/X86/known-bits-vector.ll | 14 +- test/CodeGen/X86/known-signbits-vector.ll | 38 +- test/CodeGen/X86/label-annotation.ll | 2 +- .../CodeGen/X86/lack-of-signed-truncation-check.ll | 636 + test/CodeGen/X86/large-pic-string.ll | 21 + test/CodeGen/X86/late-address-taken.ll | 8 +- test/CodeGen/X86/late-remat-update.mir | 118 + test/CodeGen/X86/lea-opt-with-debug.mir | 2 +- test/CodeGen/X86/lea-opt.ll | 386 +- test/CodeGen/X86/lea32-schedule.ll | 16 +- test/CodeGen/X86/lea64-schedule.ll | 16 +- test/CodeGen/X86/legalize-shift-64.ll | 27 +- test/CodeGen/X86/legalize-types-remapid.ll | 16 + test/CodeGen/X86/licm-nested.ll | 2 +- test/CodeGen/X86/limit-split-cost.mir | 150 + test/CodeGen/X86/load-combine.ll | 8 +- test/CodeGen/X86/loadStore_vectorizer.ll | 18 +- test/CodeGen/X86/loc-remat.ll | 2 +- test/CodeGen/X86/lower-vec-shift.ll | 112 +- test/CodeGen/X86/lsr-crash-empty-uses.ll | 42 + test/CodeGen/X86/machine-cp-debug.mir | 23 + test/CodeGen/X86/machine-cp.ll | 104 +- test/CodeGen/X86/machine-outliner-debuginfo.ll | 2 +- test/CodeGen/X86/machine-outliner-disubprogram.ll | 20 +- test/CodeGen/X86/machine-outliner-tailcalls.ll | 2 +- test/CodeGen/X86/machinesink-merge-debuginfo.ll | 4 +- test/CodeGen/X86/machinesink-null-debuginfo.ll | 2 +- test/CodeGen/X86/madd.ll | 2142 ++- test/CodeGen/X86/masked_gather_scatter.ll | 83 +- test/CodeGen/X86/masked_memop.ll | 61 +- test/CodeGen/X86/memcmp-mergeexpand.ll | 4 +- test/CodeGen/X86/merge-consecutive-loads-128.ll | 6 +- test/CodeGen/X86/merge-consecutive-loads-256.ll | 8 +- test/CodeGen/X86/mingw-comdats-xdata.ll | 81 + test/CodeGen/X86/mingw-comdats.ll | 70 + .../X86/misched-code-difference-with-debug.ll | 2 +- test/CodeGen/X86/mmx-arith.ll | 36 +- test/CodeGen/X86/mmx-build-vector.ll | 4 +- test/CodeGen/X86/mmx-schedule.ll | 570 +- test/CodeGen/X86/movdir-intrinsic-x86.ll | 41 + test/CodeGen/X86/movdir-intrinsic-x86_64.ll | 14 + test/CodeGen/X86/movpc32-check.ll | 2 +- test/CodeGen/X86/movtopush.mir | 9 +- test/CodeGen/X86/mul-constant-i16.ll | 272 +- test/CodeGen/X86/mul-constant-i32.ll | 654 +- test/CodeGen/X86/mul-constant-i64.ll | 687 +- test/CodeGen/X86/mul-constant-result.ll | 60 +- test/CodeGen/X86/muloti.ll | 44 - test/CodeGen/X86/mulx32.ll | 2 +- test/CodeGen/X86/musttail-varargs.ll | 84 +- test/CodeGen/X86/mwaitx-schedule.ll | 4 +- test/CodeGen/X86/nocf_check.ll | 2 +- test/CodeGen/X86/nontemporal-2.ll | 48 +- test/CodeGen/X86/note-cet-property.ll | 32 + test/CodeGen/X86/oddshuffles.ll | 530 +- test/CodeGen/X86/packss.ll | 186 +- test/CodeGen/X86/parity.ll | 96 + test/CodeGen/X86/pku.ll | 16 +- test/CodeGen/X86/pmaddubsw.ll | 553 + test/CodeGen/X86/pmovsx-inreg.ll | 18 +- test/CodeGen/X86/pmul.ll | 129 +- test/CodeGen/X86/popcnt.ll | 2 +- test/CodeGen/X86/post-ra-sched-with-debug.mir | 2 +- test/CodeGen/X86/postra-ignore-dbg-instrs.mir | 88 + test/CodeGen/X86/pr14088.ll | 51 +- test/CodeGen/X86/pr23103.ll | 13 +- test/CodeGen/X86/pr23246.ll | 2 +- test/CodeGen/X86/pr29112.ll | 94 +- test/CodeGen/X86/pr30290.ll | 40 + test/CodeGen/X86/pr30430.ll | 88 +- test/CodeGen/X86/pr30821.mir | 202 + test/CodeGen/X86/pr31593.ll | 33 + test/CodeGen/X86/pr32108.ll | 2 +- test/CodeGen/X86/pr32282.ll | 41 +- test/CodeGen/X86/pr32284.ll | 54 +- test/CodeGen/X86/pr32345.ll | 32 +- test/CodeGen/X86/pr32420.ll | 18 +- test/CodeGen/X86/pr34137.ll | 3 +- test/CodeGen/X86/pr34149.ll | 8 +- test/CodeGen/X86/pr34177.ll | 61 +- test/CodeGen/X86/pr34592.ll | 24 +- test/CodeGen/X86/pr35918.ll | 3 +- test/CodeGen/X86/pr36199.ll | 4 +- test/CodeGen/X86/pr36602.ll | 30 + test/CodeGen/X86/pr37264.ll | 12 + test/CodeGen/X86/pr37359.ll | 17 + test/CodeGen/X86/pr37499.ll | 37 + test/CodeGen/X86/pr37820.ll | 25 + test/CodeGen/X86/pr37826.ll | 60 + test/CodeGen/X86/pr37879.ll | 21 + test/CodeGen/X86/pr37916.ll | 44 + test/CodeGen/X86/pr38038.ll | 10 + test/CodeGen/X86/pr38185.ll | 64 + test/CodeGen/X86/pr38533.ll | 65 + test/CodeGen/X86/pr38539.ll | 314 + test/CodeGen/X86/pr9517.ll | 140 + test/CodeGen/X86/prefer-avx256-mask-extend.ll | 2 +- test/CodeGen/X86/prefer-avx256-mask-shuffle.ll | 11 +- test/CodeGen/X86/promote-i16.ll | 8 +- test/CodeGen/X86/promote-vec3.ll | 16 +- test/CodeGen/X86/psubus.ll | 151 +- test/CodeGen/X86/ptwrite32-intrinsic.ll | 56 + test/CodeGen/X86/ptwrite64-intrinsic.ll | 25 + test/CodeGen/X86/push-cfi-debug.ll | 2 +- test/CodeGen/X86/rdrand-schedule.ll | 6 +- test/CodeGen/X86/rdseed-schedule.ll | 6 +- test/CodeGen/X86/recip-fastmath.ll | 444 +- test/CodeGen/X86/recip-fastmath2.ll | 720 +- test/CodeGen/X86/reduce-trunc-shl.ll | 48 +- test/CodeGen/X86/rem.ll | 8 +- test/CodeGen/X86/required-vector-width.ll | 31 +- test/CodeGen/X86/rotate-extract-vector.ll | 287 + test/CodeGen/X86/rotate-extract.ll | 267 + test/CodeGen/X86/rotate.ll | 826 +- test/CodeGen/X86/rotate2.ll | 31 +- test/CodeGen/X86/rotate4.ll | 532 +- test/CodeGen/X86/rounding-ops.ll | 46 +- test/CodeGen/X86/sad.ll | 119 +- test/CodeGen/X86/scalar-fp-to-i64.ll | 424 +- test/CodeGen/X86/scalar-int-to-fp.ll | 362 +- test/CodeGen/X86/scalar_widen_div.ll | 1 - test/CodeGen/X86/schedule-x86-64-shld.ll | 2 +- test/CodeGen/X86/schedule-x86_32.ll | 62 +- test/CodeGen/X86/schedule-x86_64.ll | 1162 +- test/CodeGen/X86/sdiv-exact.ll | 179 +- test/CodeGen/X86/segmented-stacks.ll | 46 + test/CodeGen/X86/select-mmx.ll | 4 +- test/CodeGen/X86/select.ll | 238 +- test/CodeGen/X86/select_const.ll | 6 +- test/CodeGen/X86/selectcc-to-shiftand.ll | 200 + test/CodeGen/X86/selectiondag-debug-loc.ll | 2 +- test/CodeGen/X86/setcc-lowering.ll | 4 +- test/CodeGen/X86/sha-schedule.ll | 46 +- test/CodeGen/X86/sha.ll | 135 +- test/CodeGen/X86/shadow-stack.ll | 242 + test/CodeGen/X86/shrink_vmul.ll | 78 +- test/CodeGen/X86/shrink_wrap_dbg_value.mir | 2 +- test/CodeGen/X86/shuffle-vs-trunc-256.ll | 559 + test/CodeGen/X86/shuffle-vs-trunc-512.ll | 12 + test/CodeGen/X86/sibcall.ll | 109 + test/CodeGen/X86/signbit-shift.ll | 277 + test/CodeGen/X86/signed-truncation-check.ll | 635 + test/CodeGen/X86/sink-local-value.ll | 10 +- test/CodeGen/X86/sjlj-shadow-stack-liveness.mir | 35 + .../X86/speculative-load-hardening-gather.ll | 955 + .../X86/speculative-load-hardening-indirect.ll | 391 + test/CodeGen/X86/speculative-load-hardening.ll | 1027 ++ test/CodeGen/X86/split-store.ll | 4 +- test/CodeGen/X86/sqrt-fastmath-mir.ll | 16 +- test/CodeGen/X86/sqrt-fastmath.ll | 352 +- test/CodeGen/X86/sse-cvttp2si.ll | 233 + test/CodeGen/X86/sse-fcopysign.ll | 20 +- .../CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll | 43 +- test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 4079 ++-- test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll | 194 +- test/CodeGen/X86/sse-intrinsics-x86.ll | 722 +- test/CodeGen/X86/sse-intrinsics-x86_64-upgrade.ll | 24 + test/CodeGen/X86/sse-intrinsics-x86_64.ll | 71 +- test/CodeGen/X86/sse-scalar-fp-arith-unary.ll | 27 +- test/CodeGen/X86/sse-scalar-fp-arith.ll | 908 +- test/CodeGen/X86/sse-schedule.ll | 182 +- test/CodeGen/X86/sse1.ll | 224 +- test/CodeGen/X86/sse2-intrinsics-canonical.ll | 300 + .../X86/sse2-intrinsics-fast-isel-x86_64.ll | 90 +- test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 7310 +++++--- test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll | 912 +- test/CodeGen/X86/sse2-intrinsics-x86.ll | 1923 +- test/CodeGen/X86/sse2-intrinsics-x86_64-upgrade.ll | 24 + test/CodeGen/X86/sse2-intrinsics-x86_64.ll | 71 +- test/CodeGen/X86/sse2-schedule.ll | 392 +- test/CodeGen/X86/sse2.ll | 852 +- test/CodeGen/X86/sse3-avx-addsub-2.ll | 100 +- test/CodeGen/X86/sse3-intrinsics-fast-isel.ll | 210 +- test/CodeGen/X86/sse3-intrinsics-x86.ll | 141 +- test/CodeGen/X86/sse3-schedule.ll | 66 +- test/CodeGen/X86/sse41-intrinsics-fast-isel.ll | 1304 +- test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll | 545 +- test/CodeGen/X86/sse41-intrinsics-x86.ll | 739 +- test/CodeGen/X86/sse41-schedule.ll | 124 +- test/CodeGen/X86/sse41.ll | 2334 ++- .../X86/sse42-intrinsics-fast-isel-x86_64.ll | 24 +- test/CodeGen/X86/sse42-intrinsics-fast-isel.ll | 632 +- test/CodeGen/X86/sse42-intrinsics-x86.ll | 855 +- test/CodeGen/X86/sse42-intrinsics-x86_64.ll | 6 +- test/CodeGen/X86/sse42-schedule.ll | 40 +- test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll | 80 +- test/CodeGen/X86/sse4a-schedule.ll | 8 +- test/CodeGen/X86/sse4a-upgrade.ll | 36 +- test/CodeGen/X86/sse4a.ll | 236 +- test/CodeGen/X86/sse_partial_update.ll | 21 +- test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll | 292 +- test/CodeGen/X86/ssse3-intrinsics-x86.ll | 264 +- test/CodeGen/X86/ssse3-schedule.ll | 56 +- test/CodeGen/X86/stack-folding-fp-avx1.ll | 152 +- test/CodeGen/X86/stack-folding-fp-avx512.ll | 125 +- test/CodeGen/X86/stack-folding-fp-avx512vl.ll | 22 +- test/CodeGen/X86/stack-folding-fp-sse42.ll | 160 +- test/CodeGen/X86/stack-folding-int-avx1.ll | 115 +- test/CodeGen/X86/stack-folding-int-avx2.ll | 116 +- test/CodeGen/X86/stack-folding-int-avx512.ll | 233 +- test/CodeGen/X86/stack-folding-int-avx512vl.ll | 481 +- test/CodeGen/X86/stack-folding-int-sse42.ll | 116 +- test/CodeGen/X86/stack-folding-tbm.ll | 8 +- test/CodeGen/X86/stack-protector-dbginfo.ll | 10 +- .../X86/stack-size-section-function-sections.ll | 26 + test/CodeGen/X86/stack-size-section.ll | 21 +- test/CodeGen/X86/store-zero-and-minus-one.ll | 218 +- test/CodeGen/X86/sttni.ll | 1337 ++ test/CodeGen/X86/subcarry.ll | 59 +- test/CodeGen/X86/subvector-broadcast.ll | 120 +- test/CodeGen/X86/tail-call-conditional.mir | 6 +- test/CodeGen/X86/tail-dup-debugloc.ll | 2 +- test/CodeGen/X86/tail-dup-merge-loop-headers.ll | 2 +- test/CodeGen/X86/tail-opts.ll | 2 +- test/CodeGen/X86/tailcall-64.ll | 192 +- .../X86/tailjmp_gotpcrel_relax_relocation.ll | 15 + .../CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll | 4 +- test/CodeGen/X86/tbm-intrinsics-fast-isel.ll | 6 +- test/CodeGen/X86/tbm-intrinsics-x86_64.ll | 60 +- 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test/MC/AArch64/SVE/fcmla-diagnostics.s | 62 + test/MC/AArch64/SVE/fcmla.s | 144 + test/MC/AArch64/SVE/fcmle-diagnostics.s | 39 + test/MC/AArch64/SVE/fcmle.s | 44 + test/MC/AArch64/SVE/fcmlt-diagnostics.s | 39 + test/MC/AArch64/SVE/fcmlt.s | 44 + test/MC/AArch64/SVE/fcmne-diagnostics.s | 39 + test/MC/AArch64/SVE/fcmne.s | 44 + test/MC/AArch64/SVE/fcmuo-diagnostics.s | 27 + test/MC/AArch64/SVE/fcmuo.s | 27 + test/MC/AArch64/SVE/fcpy-diagnostics.s | 83 + test/MC/AArch64/SVE/fcpy.s | 1584 ++ test/MC/AArch64/SVE/fcvt-diagnostics.s | 25 + test/MC/AArch64/SVE/fcvt.s | 72 + test/MC/AArch64/SVE/fcvtzs-diagnostics.s | 20 + test/MC/AArch64/SVE/fcvtzs.s | 78 + test/MC/AArch64/SVE/fcvtzu-diagnostics.s | 20 + test/MC/AArch64/SVE/fcvtzu.s | 78 + test/MC/AArch64/SVE/fdiv-diagnostics.s | 33 + test/MC/AArch64/SVE/fdiv.s | 54 + test/MC/AArch64/SVE/fdivr-diagnostics.s | 33 + test/MC/AArch64/SVE/fdivr.s | 54 + test/MC/AArch64/SVE/fdup-diagnostics.s | 80 + test/MC/AArch64/SVE/fdup.s | 1556 ++ test/MC/AArch64/SVE/fexpa-diagnostics.s | 30 + test/MC/AArch64/SVE/fexpa.s | 26 + test/MC/AArch64/SVE/fmad-diagnostics.s | 33 + test/MC/AArch64/SVE/fmad.s | 54 + test/MC/AArch64/SVE/fmax-diagnostics.s | 61 + test/MC/AArch64/SVE/fmax.s | 120 + test/MC/AArch64/SVE/fmaxnm-diagnostics.s | 61 + test/MC/AArch64/SVE/fmaxnm.s | 126 + test/MC/AArch64/SVE/fmaxnmv-diagnostics.s | 35 + test/MC/AArch64/SVE/fmaxnmv.s | 26 + test/MC/AArch64/SVE/fmaxv-diagnostics.s | 35 + test/MC/AArch64/SVE/fmaxv.s | 26 + test/MC/AArch64/SVE/fmin-diagnostics.s | 61 + test/MC/AArch64/SVE/fmin.s | 126 + test/MC/AArch64/SVE/fminnm-diagnostics.s | 61 + test/MC/AArch64/SVE/fminnm.s | 126 + test/MC/AArch64/SVE/fminnmv-diagnostics.s | 35 + test/MC/AArch64/SVE/fminnmv.s | 26 + test/MC/AArch64/SVE/fminv-diagnostics.s | 35 + test/MC/AArch64/SVE/fminv.s | 26 + test/MC/AArch64/SVE/fmla-diagnostics.s | 82 + test/MC/AArch64/SVE/fmla.s | 84 + test/MC/AArch64/SVE/fmls-diagnostics.s | 82 + test/MC/AArch64/SVE/fmls.s | 84 + test/MC/AArch64/SVE/fmov-diagnostics.s | 158 + test/MC/AArch64/SVE/fmov.s | 1626 ++ test/MC/AArch64/SVE/fmsb-diagnostics.s | 33 + test/MC/AArch64/SVE/fmsb.s | 54 + test/MC/AArch64/SVE/fmul-diagnostics.s | 162 + test/MC/AArch64/SVE/fmul.s | 174 + test/MC/AArch64/SVE/fmulx-diagnostics.s | 33 + test/MC/AArch64/SVE/fmulx.s | 54 + test/MC/AArch64/SVE/fneg-diagnostics.s | 23 + test/MC/AArch64/SVE/fneg.s | 54 + test/MC/AArch64/SVE/fnmad-diagnostics.s | 33 + test/MC/AArch64/SVE/fnmad.s | 54 + test/MC/AArch64/SVE/fnmla-diagnostics.s | 28 + test/MC/AArch64/SVE/fnmla.s | 54 + test/MC/AArch64/SVE/fnmls-diagnostics.s | 28 + test/MC/AArch64/SVE/fnmls.s | 54 + test/MC/AArch64/SVE/fnmsb-diagnostics.s | 33 + test/MC/AArch64/SVE/fnmsb.s | 54 + test/MC/AArch64/SVE/frecpe-diagnostics.s | 21 + test/MC/AArch64/SVE/frecpe.s | 26 + test/MC/AArch64/SVE/frecps-diagnostics.s | 31 + test/MC/AArch64/SVE/frecps.s | 26 + test/MC/AArch64/SVE/frecpx-diagnostics.s | 16 + test/MC/AArch64/SVE/frecpx.s | 54 + test/MC/AArch64/SVE/frinta-diagnostics.s | 16 + test/MC/AArch64/SVE/frinta.s | 54 + test/MC/AArch64/SVE/frinti-diagnostics.s | 16 + test/MC/AArch64/SVE/frinti.s | 54 + test/MC/AArch64/SVE/frintm-diagnostics.s | 16 + test/MC/AArch64/SVE/frintm.s | 54 + test/MC/AArch64/SVE/frintn-diagnostics.s | 16 + test/MC/AArch64/SVE/frintn.s | 54 + test/MC/AArch64/SVE/frintp-diagnostics.s | 16 + test/MC/AArch64/SVE/frintp.s | 54 + test/MC/AArch64/SVE/frintx-diagnostics.s | 16 + test/MC/AArch64/SVE/frintx.s | 54 + test/MC/AArch64/SVE/frintz-diagnostics.s | 16 + test/MC/AArch64/SVE/frintz.s | 54 + test/MC/AArch64/SVE/frsqrte-diagnostics.s | 21 + test/MC/AArch64/SVE/frsqrte.s | 26 + test/MC/AArch64/SVE/frsqrts-diagnostics.s | 31 + test/MC/AArch64/SVE/frsqrts.s | 26 + test/MC/AArch64/SVE/fscale-diagnostics.s | 33 + test/MC/AArch64/SVE/fscale.s | 54 + test/MC/AArch64/SVE/fsqrt-diagnostics.s | 16 + test/MC/AArch64/SVE/fsqrt.s | 54 + test/MC/AArch64/SVE/fsub-diagnostics.s | 86 + test/MC/AArch64/SVE/fsub.s | 144 + test/MC/AArch64/SVE/fsubr-diagnostics.s | 61 + test/MC/AArch64/SVE/fsubr.s | 126 + test/MC/AArch64/SVE/ftmad-diagnostics.s | 48 + test/MC/AArch64/SVE/ftmad.s | 42 + test/MC/AArch64/SVE/ftsmul-diagnostics.s | 31 + test/MC/AArch64/SVE/ftsmul.s | 26 + test/MC/AArch64/SVE/ftssel-diagnostics.s | 21 + test/MC/AArch64/SVE/ftssel.s | 26 + test/MC/AArch64/SVE/incb-diagnostics.s | 63 + test/MC/AArch64/SVE/incb.s | 206 + test/MC/AArch64/SVE/incd-diagnostics.s | 85 + test/MC/AArch64/SVE/incd.s | 206 + test/MC/AArch64/SVE/inch-diagnostics.s | 85 + test/MC/AArch64/SVE/inch.s | 206 + test/MC/AArch64/SVE/incp-diagnostics.s | 48 + test/MC/AArch64/SVE/incp.s | 90 + test/MC/AArch64/SVE/incw-diagnostics.s | 85 + test/MC/AArch64/SVE/incw.s | 207 + test/MC/AArch64/SVE/index-diagnostics.s | 40 + test/MC/AArch64/SVE/insr-diagnostics.s | 61 + test/MC/AArch64/SVE/insr.s | 108 + test/MC/AArch64/SVE/lasta-diagnostics.s | 82 + test/MC/AArch64/SVE/lasta.s | 56 + test/MC/AArch64/SVE/lastb-diagnostics.s | 82 + test/MC/AArch64/SVE/lastb.s | 56 + test/MC/AArch64/SVE/ld1b-diagnostics.s | 92 +- test/MC/AArch64/SVE/ld1b.s | 54 + test/MC/AArch64/SVE/ld1d-diagnostics.s | 89 +- test/MC/AArch64/SVE/ld1d.s | 48 + test/MC/AArch64/SVE/ld1h-diagnostics.s | 119 +- test/MC/AArch64/SVE/ld1h.s | 84 + test/MC/AArch64/SVE/ld1rb-diagnostics.s | 39 + test/MC/AArch64/SVE/ld1rb.s | 56 + test/MC/AArch64/SVE/ld1rd-diagnostics.s | 73 + test/MC/AArch64/SVE/ld1rd.s | 20 + test/MC/AArch64/SVE/ld1rh-diagnostics.s | 63 + test/MC/AArch64/SVE/ld1rh.s | 44 + test/MC/AArch64/SVE/ld1rqb-diagnostics.s | 97 + test/MC/AArch64/SVE/ld1rqb.s | 38 + test/MC/AArch64/SVE/ld1rqd-diagnostics.s | 97 + test/MC/AArch64/SVE/ld1rqd.s | 38 + test/MC/AArch64/SVE/ld1rqh-diagnostics.s | 97 + test/MC/AArch64/SVE/ld1rqh.s | 38 + test/MC/AArch64/SVE/ld1rqw-diagnostics.s | 97 + test/MC/AArch64/SVE/ld1rqw.s | 38 + test/MC/AArch64/SVE/ld1rsb-diagnostics.s | 48 + test/MC/AArch64/SVE/ld1rsb.s | 44 + test/MC/AArch64/SVE/ld1rsh-diagnostics.s | 58 + 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[llvm] branch master updated (59c0c36fc16 -> bb4f57ce91e)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 59c0c36fc16 Prevent DILocation::getMergedLocation() from creating inval [...] new bb4f57ce91e [RISCV] Fixed Assertion`Kind == Immediate && "Invalid type [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 18 ++++++++++++++++++ test/MC/RISCV/rv32c-fuzzed-invalid.s | 17 +++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 test/MC/RISCV/rv32c-fuzzed-invalid.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[libcxxabi] branch master updated (29ffb8f -> 5f74259)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository libcxxabi. from 29ffb8f Port LLVM r340203 (and r340205) to libcxxabi. new 5f74259 Port my recent changes from LLVM copy of the demangler: The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: src/demangle/ItaniumDemangle.h | 98 +++++++++++++++++++++++++++++++----------- 1 file changed, 74 insertions(+), 24 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[llvm] branch master updated (fc721a89bb4 -> 59c0c36fc16)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from fc721a89bb4 Allow demangler's node allocator to fail, and bail out of t [...] new 59c0c36fc16 Prevent DILocation::getMergedLocation() from creating inval [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/IR/DebugInfoMetadata.cpp | 5 +++ unittests/IR/MetadataTest.cpp | 78 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 2feea286729 [RISCV] Fix std::advance slowness new fc721a89bb4 Allow demangler's node allocator to fail, and bail out of t [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/Demangle/ItaniumDemangle.h | 66 +++++++++++++++------- .../llvm/Support/ItaniumManglingCanonicalizer.h | 6 ++ lib/Support/ItaniumManglingCanonicalizer.cpp | 26 +++++++-- .../Support/ItaniumManglingCanonicalizerTest.cpp | 39 +++++++++++-- 4 files changed, 109 insertions(+), 28 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[llvm] branch master updated (52479366fca -> 2feea286729)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 52479366fca [llvm-mca] Move ResourceManager from Scheduler into its own [...] new 2feea286729 [RISCV] Fix std::advance slowness The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/RISCV/RISCVFrameLowering.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[llvm] branch master updated (8d280d4a1ee -> 52479366fca)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 8d280d4a1ee Fix ExpandedSpecialSubstitution demangling for Sa and Sb. new 52479366fca [llvm-mca] Move ResourceManager from Scheduler into its own [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tools/llvm-mca/CMakeLists.txt | 1 + .../{Scheduler.cpp => ResourceManager.cpp} | 239 +-------------- tools/llvm-mca/{Scheduler.h => ResourceManager.h} | 201 +----------- tools/llvm-mca/Scheduler.cpp | 284 ----------------- tools/llvm-mca/Scheduler.h | 339 +-------------------- 5 files changed, 20 insertions(+), 1044 deletions(-) copy tools/llvm-mca/{Scheduler.cpp => ResourceManager.cpp} (56%) copy tools/llvm-mca/{Scheduler.h => ResourceManager.h} (63%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[clang] branch master updated (a80ce5895a -> 905c589291)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from a80ce5895a Reland r340552, "Driver: Enable address-significance tables [...] new 905c589291 Revert r323281 "Adjust MaxAtomicInlineWidth for i386/i486 targets." The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Basic/Targets/X86.h | 8 ++--- test/CodeGenCXX/atomic-inline.cpp | 61 ++------------------------------------- 2 files changed, 5 insertions(+), 64 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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