Tcwg-commits August 2018

tcwg-commits@lists.linaro.org

5 participants
3637 discussions

[llvm] branch master updated (0cd45cda8dd -> 46fd9f609b6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 0cd45cda8dd [cmake] Prevent LLVMgold.so from being unloaded on Linux new 46fd9f609b6 [TableGen] Return ValueTypeByHwMode by const reference from [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: utils/TableGen/CodeGenRegisters.h | 2 +- utils/TableGen/DAGISelMatcherGen.cpp | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[toolchain/jenkins-scripts] branch llvm-kernel updated (47d6de6 -> 6590239)

by Maxim Kuvyrkov

This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch llvm-kernel in repository toolchain/jenkins-scripts. discards 47d6de6 tcwg-rr-llvm-kernel.sh: New job script. new 6590239 tcwg-rr-llvm-kernel.sh: New job script. This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (47d6de6) \ N -- N -- N refs/heads/llvm-kernel (6590239) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tcwg-rr-llvm-kernel.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[llvm] branch master updated (7edab834d4b -> 0cd45cda8dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 7edab834d4b [InstCombine] move vector compare before same-shuffled ops new 0cd45cda8dd [cmake] Prevent LLVMgold.so from being unloaded on Linux The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: cmake/modules/HandleLLVMOptions.cmake | 1 + 1 file changed, 1 insertion(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[toolchain/jenkins-scripts] branch llvm-kernel updated (1741bf3 -> 47d6de6)

by Maxim Kuvyrkov

This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch llvm-kernel in repository toolchain/jenkins-scripts. discards 1741bf3 tcwg-rr-llvm-kernel.sh: New job script. new 47d6de6 tcwg-rr-llvm-kernel.sh: New job script. This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (1741bf3) \ N -- N -- N refs/heads/llvm-kernel (47d6de6) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tcwg-rr-llvm-kernel.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[toolchain/llvm/clang] branch linaro-local/ci/llvm-kernel-aarch64-good created (now 293b7c5989)

by Maxim Kuvyrkov

This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch linaro-local/ci/llvm-kernel-aarch64-good in repository toolchain/llvm/clang. at 293b7c5989 Convert if/else to a switch. NFC. No new revisions were added by this update. -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[toolchain/llvm/llvm] branch linaro-local/ci/llvm-kernel-aarch64-tested updated (3ea7b0a0b1e -> 7edab834d4b)

by tcwg-buildslave

This is an automated email from the git hooks/post-receive script. "tcwg-buildslave pushed a change to branch linaro-local/ci/llvm-kernel-aarch64-tested in repository toolchain/llvm/llvm. from 3ea7b0a0b1e [BasicAA] Don't assume tail calls with byval don't alias allocas adds d64c9dd5388 [ThinLTO] Handle optional args in assembly format for ConstVCalls adds 78ac4b1f01c [CMake] Split -gx strip flag into -g -x adds d3b60bef640 [ThinLTO] Fix printing of WPD remarks adds a3a6a7d1b97 [NFC] Add comprehensive test of AliasSetTracker with guards adds b0ee0d322a6 [NFC] Modify comment to make it more precise adds 35b2115503a [ARM] ParallelDSP: add option to enable/disable the pass adds 8ec69ac247c [X86] Lowering addus/subus intrinsics to native IR adds 7525376ccf3 Test commit: fix punctuation adds 1fb2ad5ddc4 [RISCV] Fix incorrect use of MCInstBuilder adds 17454e67ca5 [X86] Constant folding of adds/subs intrinsics adds 922ac36549e Fix MSVC "compiler limit: blocks nested too deeply" error. NFCI. adds 62fcc622307 [TableGen] Pass string/vector types by const reference (PR3 [...] adds 0904155b95b [GlobalISel][IRTranslator] Fix a bug in handling repeating [...] adds cb8c5e417d5 [DebugInfo] Generate DWARF debug information for labels. (F [...] adds 08a2e24fdca [X86][SSE] Generalize lowerVectorShuffleAsBlendOfPSHUFBs to [...] adds 8bdeb675f27 [InstCombine] regenerate checks; NFC adds dd807ea799a [Inliner] add inliner stats to new pm version of inliner adds 0e18d0dcb9c [InstCombine] regenerate checks; NFC adds 76cf1f6a8b0 [X86][SSE] Add shuffle combine tests for OR(PSHUFB,PSHUFB) [...] adds 9c0c0a23efe [X86][SSE] Add shuffle combine support for OR(PSHUFB,PSHUFB [...] adds 2f6f2fb76a6 [DAG] Avoid redundant chain transversal in store merge cycl [...] adds f921d44a03e Expose CFG Update struct. Define GraphTraits to get childre [...] adds 1645076dc8e [NFC] Tests for select with binop fold - FP opcodes adds dd11fa16f91 [DomTree] Cleanup Update and LegalizeUpdate API moved to Su [...] adds a06c0f8edb7 [X86][SSE] Avoid duplicate shuffle input sources in combine [...] adds e747ac6d9aa [GraphDiff] Make InverseGraph a property of a GraphDiff. adds 8c444324e7b Revert "[DebugInfo] Generate DWARF debug information for la [...] adds 1464f16217a [LV] Teach about non header phis that have uses outside the loop adds e9759ddbdc5 [Tablegen][MCInstPredicate] Removed redundant template argu [...] adds 95688ee84cf [WebAssembly] SIMD extract_lane adds addd2704187 [MS Demangler] Fix some minor formatting bugs. adds 35b45c96579 [WebAssembly] Fix encoding of non-SIMD vector-typed instructions adds 18a9130c102 [InstCombine] add tests for pow->sqrt; NFC adds 35b8f4b065f [WebAssembly] SIMD encoding tests adds adcef01bd74 [InstCombine] fix typos in tests; NFC adds c4d19094354 [DebugInfoMetadata] Added DIFlags interface in DIBasicType. adds a3fdc1d2931 NFC: Clarify comment in loop vectorization legality adds 5c7c276dd6d Add proper headers in CFGUpdate.h and add CFGDiff.h in the [...] adds 3bd565f2797 Remove vestiges of configure buildsystem adds 4db82cd15b0 [SanitizerCoverage] Add associated metadata to PC guards. adds 1a5e05d0703 [ARM] Make PerformSHLSimplify add nodes to the DAG worklist [...] adds ca4f10703e3 [FPEnv] Scalarize StrictFP vector operations adds c35538fcabb [WebAssembly] Delete a specific push number from test expectations adds fc187011bee [SDAG] Remove the reliance on MI's allocation strategy for [...] adds 34c8f3ddbad [WebAssembly] SIMD Splats adds 6203c9bd082 [hwasan] Add a basic API. adds f464242872b [SDAG] Update the AVR backend for the SelectionDAG API chan [...] adds eb72488593a [X86] Change legacy SSE scalar fp to integer intrinsics to [...] adds 7caa753e199 [NFC][LICM] Make hoist method void adds a3bb636475f [NFC] Add sanitizing assertion to ICF tracker adds d823f47a683 [NFC] Refactoring of LoopSafetyInfo, step 1 adds 9e9c1c4ddd5 [AliasSetTracker] Do not treat experimental_guard intrinsic [...] adds 90048a82062 [ARM] Allow pointer values in ARMCodeGenPrepare adds 81654d23626 [ARM] Allow signed icmps in ARMCodeGenPrepare adds 7e6dd0cff77 [TargetLowering] Add support for non-uniform vectors to Bui [...] adds c60b833f830 [DagCombiner] Don't bother adding to the work list if TLI.B [...] adds 0f7eb9f5326 [TargetLowering] Minor refactor to TargetLowering::BuildUDI [...] adds 406608e1b08 [X86] Add sibling-call test cases adds da4cfd320c2 [X86][SSE] Add sdiv by nonuniform constant vector tests adds a5f4d299297 [UnJ] Rename hasInvariantIterationCount to hasIterationCoun [...] adds f965428b0ed [TargetLowering] Minor cleanup of TargetLowering::BuildSDIV. NFCI. adds 3ea0447ec7a [yaml2obj] - Teach tool to produce SHT_GROUP section with a [...] adds 8ae415fb86e Remove lambda default argument to fix gcc pedantic warning. adds 47bbfe3bd01 [llvm-mca] Fix PR38575: Avoid an invalid implicit truncatio [...] adds 7c82b970fb5 [PowerPC] Don't run BV DAG Combine before legalization if i [...] adds 3dd52420555 [ARM] TypeSize lower bound for ARMCodeGenPrepare adds 312924a2b1c [yaml2obj] - Teach yaml2obj to produce SHT_GROUP section wi [...] adds 0566eefef9c [SimplifyCFG] Remove pointer from SmallPtrSet before deletion adds d9e857fb583 [SystemZ] New CL option to enable subreg liveness adds 33a5d47e0f1 [GVN] Fix typo in IsValueFullyAvailableInBlock. NFC. adds 9f59a11e239 [SystemZ] Replace subreg_r with subreg_h adds 4df6ca02ff2 [PowerPC] Enhance the selection(ISD::VSELECT) of vector type adds 165c0cc4857 [SystemZ] Add testcase for r339778 adds d7a0236f295 [RegAlloc] Check that subreg liveness tracking applies to g [...] adds ffcf1047060 [WebAssembly] SIMD replace_lane adds 28f0c7ef0ac [RegisterCoalescer] Reset VNInfo def when copying segments over adds b581cf5c17b [x86] add tests for poor vector intrinsic lowering via lega [...] adds 6faab4de878 [x86] add fabs test for vector intrinsic to potential libca [...] adds 0d5de60cbee [RegisterCoalescer] Ensure that both registers have subrang [...] adds 8529a08ceb1 [AArch64] add tests for poor vector intrinsic lowering via [...] adds 41df26a4e56 [MemorySSA] Expose the verify as a debug option. adds 9dfeae47a7c [InstCombine] Fix IC trying to create a xor of pointer types. adds 8bb6fcb54b3 [WebAssembly] Test commit adds a2ac910471e llvm-readobj: Fix addend in relocations for android packed format adds e94c82ccbba [WebAssembly][NFC] Standardize SIMD multiclass format adds e0dc5c1ea20 [Support] Add a basic C API for llvm::Error. adds 30db32fcf12 Revert "[ARM] Allow signed icmps in ARMCodeGenPrepare" adds c2a24b87802 [MCJIT] Fix a case of Error::success() being passed to repo [...] adds e79e42e6c4d DAG: Try to custom lower when promoting float operands adds 1cdda230e96 [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeB [...] adds 982d395b2af DAG: Use getObjectOffset helper adds abf0ee059c4 AMDGPU: Address todo for handling 1/(2 pi) adds 6737250f979 AMDGPU: Stop producing icmp/fcmp intrinsics with invalid types adds ecc93786a13 [X86] Improve AVX1 shuffle lowering for v8f32 shuffles wher [...] adds 5f9b848ed3e AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16 adds 6030329f4bc AMDGPU: Improve extract_vector_elt reduction combine adds d82cfba790c AMDGPU: Fold fneg into fmed3 adds c4dcd354354 [CodeGenPrepare] Add BothExtension type to PromotedInsts adds 61d7ed20677 [llvm-mca] Minor style changes. NFC adds 8f94a553bfa [Metadata] Replace a SmallVector with an array; NFC adds 21f571c07cb [BFI] Use rounding while computing profile counts. adds d914c51df99 [x86] Actually initialize the SLH pass with the x86 backend [...] adds ec2710fb9b3 [X86] Correct some bad FileCheck prefixes in tests. Add tes [...] adds 58d47fbc549 [X86] Remove the unused masked 128 and 256-bit masked padds [...] adds 6914988dcf2 [X86] Remove masking from the 512-bit padds and psubs intri [...] adds 2a96c80ff2a [NFC] Add missing const modifier adds 83b908472d7 [NFC] Remove const modifier to allow further development in LICM adds 87ed975f8b5 [mips] Remove dead code from MipsPassConfig adds 7d16ffe5b76 [ARM] Allow signed icmps in ARMCodeGenPrepare adds 547d94c0203 [ADT] Replace APInt::WORD_MAX with APInt::WORDTYPE_MAX adds ff51b9f280e [RISCV][MC] Don't fold symbol differences if requiresDiffEx [...] adds fd2bee90f5b [ARM] Allow zext in ARMCodeGenPrepare adds d9d671112da [yaml2elf] - Simplify code, add a test. NFC. adds 3591e4cd934 [ARM] Ignore GEPs in ARMCodeGenPrepare adds 4b96e82fd27 [yaml2elf] - Use check-next in test. adds f23f849bd17 [yaml2obj] - Allow to use numeric sh_link (Link) value for [...] adds 7edab834d4b [InstCombine] move vector compare before same-shuffled ops No new revisions were added by this update. Summary of changes: CMakeLists.txt | 18 - cmake/modules/AddLLVM.cmake | 2 +- include/llvm-c/Error.h | 65 + include/llvm/ADT/APInt.h | 18 +- include/llvm/ADT/iterator.h | 28 + include/llvm/Analysis/MustExecute.h | 37 +- include/llvm/BinaryFormat/Dwarf.def | 13 +- include/llvm/BinaryFormat/Dwarf.h | 5 +- include/llvm/CodeGen/GlobalISel/IRTranslator.h | 1 + include/llvm/CodeGen/SelectionDAG.h | 5 + include/llvm/CodeGen/SelectionDAGNodes.h | 62 +- include/llvm/CodeGen/TargetLowering.h | 16 +- include/llvm/IR/CFGDiff.h | 285 ++++ include/llvm/IR/DIBuilder.h | 6 +- include/llvm/IR/DebugInfoFlags.def | 4 +- include/llvm/IR/DebugInfoMetadata.h | 27 +- include/llvm/IR/Dominators.h | 6 +- include/llvm/IR/IntrinsicsX86.td | 108 +- include/llvm/MC/MCObjectStreamer.h | 4 +- include/llvm/Support/CFGUpdate.h | 118 ++ include/llvm/Support/Debug.h | 4 + include/llvm/Support/Error.h | 17 +- include/llvm/Support/GenericDomTree.h | 49 +- include/llvm/Support/GenericDomTreeConstruction.h | 80 +- include/llvm/Target/TargetInstrPredicate.td | 19 +- include/llvm/Transforms/Utils/LoopUtils.h | 2 +- include/llvm/module.modulemap | 1 + lib/Analysis/AliasSetTracker.cpp | 8 +- lib/Analysis/BlockFrequencyInfoImpl.cpp | 4 +- lib/Analysis/MemorySSA.cpp | 12 +- lib/Analysis/MustExecute.cpp | 37 +- lib/AsmParser/LLParser.cpp | 22 +- lib/Bitcode/Reader/MetadataLoader.cpp | 7 +- lib/Bitcode/Writer/BitcodeWriter.cpp | 1 + lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 5 + lib/CodeGen/CodeGenPrepare.cpp | 56 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 + lib/CodeGen/RegisterCoalescer.cpp | 13 +- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 18 +- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 7 +- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 5 + lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 + lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 49 + lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 10 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 23 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 7 +- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 36 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 154 +- lib/CodeGen/StackColoring.cpp | 2 +- lib/CodeGen/VirtRegMap.cpp | 2 +- lib/Demangle/MicrosoftDemangle.cpp | 12 +- lib/ExecutionEngine/MCJIT/MCJIT.cpp | 3 +- lib/IR/AsmWriter.cpp | 3 + lib/IR/AutoUpgrade.cpp | 123 +- lib/IR/DIBuilder.cpp | 5 +- lib/IR/DebugInfoMetadata.cpp | 9 +- lib/IR/Dominators.cpp | 2 +- lib/IR/LLVMContextImpl.h | 10 +- lib/IR/MDBuilder.cpp | 7 +- lib/IR/Verifier.cpp | 2 + lib/MC/MCObjectStreamer.cpp | 11 +- lib/Object/ELF.cpp | 15 +- lib/Support/APInt.cpp | 18 +- lib/Support/Error.cpp | 20 + lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 37 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 18 +- lib/Target/AArch64/AArch64ISelLowering.h | 3 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 5 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 40 +- lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 + lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 2 +- lib/Target/AMDGPU/AMDGPUSubtarget.h | 9 +- lib/Target/AMDGPU/SIISelLowering.cpp | 119 +- lib/Target/AMDGPU/VOPCInstructions.td | 26 + lib/Target/ARM/ARMCodeGenPrepare.cpp | 129 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 53 +- lib/Target/ARM/ARMISelLowering.cpp | 29 +- lib/Target/ARM/ARMISelLowering.h | 3 + lib/Target/ARM/ARMParallelDSP.cpp | 6 + lib/Target/AVR/AVRISelDAGToDAG.cpp | 8 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 19 +- lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 10 +- lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 5 +- lib/Target/Mips/MipsTargetMachine.cpp | 4 - lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 35 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 18 +- lib/Target/PowerPC/PPCISelLowering.cpp | 23 +- lib/Target/PowerPC/PPCInstrAltivec.td | 4 + lib/Target/PowerPC/PPCInstrVSX.td | 3 +- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 14 +- .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 2 +- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 7 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 4 +- lib/Target/SystemZ/SystemZInstrFP.td | 10 +- lib/Target/SystemZ/SystemZInstrInfo.cpp | 8 +- lib/Target/SystemZ/SystemZInstrVector.td | 16 +- lib/Target/SystemZ/SystemZRegisterInfo.td | 7 +- lib/Target/SystemZ/SystemZSubtarget.cpp | 10 + lib/Target/SystemZ/SystemZSubtarget.h | 3 + lib/Target/WebAssembly/WebAssemblyInstrCall.td | 49 +- lib/Target/WebAssembly/WebAssemblyInstrControl.td | 12 +- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 106 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 23 +- lib/Target/X86/X86ISelLowering.cpp | 496 ++++-- lib/Target/X86/X86ISelLowering.h | 4 +- lib/Target/X86/X86InstrAVX512.td | 133 +- lib/Target/X86/X86InstrFragmentsSIMD.td | 10 +- lib/Target/X86/X86InstrInfo.cpp | 74 +- lib/Target/X86/X86InstrSSE.td | 55 +- lib/Target/X86/X86IntrinsicsInfo.h | 76 +- lib/Target/X86/X86SchedPredicates.td | 2 +- lib/Target/X86/X86SpeculativeLoadHardening.cpp | 6 +- lib/Target/X86/X86TargetMachine.cpp | 2 + lib/Target/XCore/XCoreISelDAGToDAG.cpp | 5 +- lib/Transforms/IPO/Inliner.cpp | 3 + lib/Transforms/IPO/WholeProgramDevirt.cpp | 6 +- lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 3 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 105 ++ lib/Transforms/InstCombine/InstCombineCompares.cpp | 28 + .../Instrumentation/HWAddressSanitizer.cpp | 11 +- .../Instrumentation/SanitizerCoverage.cpp | 3 + lib/Transforms/Scalar/GVN.cpp | 2 +- lib/Transforms/Scalar/LICM.cpp | 17 +- lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 4 +- lib/Transforms/Scalar/LoopUnswitch.cpp | 2 +- .../Utils/ImplicitControlFlowTracking.cpp | 4 +- lib/Transforms/Utils/LoopUnrollAndJam.cpp | 6 +- lib/Transforms/Utils/LoopUtils.cpp | 4 +- lib/Transforms/Utils/SimplifyCFG.cpp | 6 +- .../Vectorize/LoopVectorizationLegality.cpp | 21 +- lib/Transforms/Vectorize/LoopVectorize.cpp | 10 +- test/Analysis/AliasSet/guards.ll | 1550 +++++++++++++++++++ test/Analysis/AliasSet/intrinsics.ll | 46 + .../Analysis/BlockFrequencyInfo/irreducible_pgo.ll | 20 +- test/Assembler/debug-info.ll | 9 +- test/Assembler/thinlto-summary.ll | 8 +- test/Bitcode/thinlto-type-vcalls.ll | 8 +- .../irtranslator-duplicate-types-param.ll | 15 + test/CodeGen/AArch64/vec-libcalls.ll | 564 +++++++ test/CodeGen/AMDGPU/fcanonicalize-elimination.ll | 2 +- test/CodeGen/AMDGPU/fneg-combines.ll | 478 ++++-- test/CodeGen/AMDGPU/fneg-combines.si.ll | 28 + test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll | 190 ++- test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll | 86 +- test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll | 160 +- test/CodeGen/AMDGPU/reduction.ll | 151 +- ...{arm-cgp-phis-calls-ret.ll => arm-cgp-calls.ll} | 219 +-- test/CodeGen/ARM/arm-cgp-icmps.ll | 23 + test/CodeGen/ARM/arm-cgp-phis-ret.ll | 174 +++ test/CodeGen/ARM/arm-cgp-pointers.ll | 135 ++ test/CodeGen/ARM/arm-cgp-signed-icmps.ll | 100 ++ test/CodeGen/ARM/arm-cgp-zext-truncs.ll | 29 +- test/CodeGen/PowerPC/pr38087.ll | 55 + test/CodeGen/PowerPC/vec_select.ll | 103 +- test/CodeGen/RISCV/fixups-diff.ll | 46 + test/CodeGen/SystemZ/subregliveness-01.ll | 48 + test/CodeGen/SystemZ/subregliveness-02.ll | 22 + test/CodeGen/SystemZ/subregliveness-03.ll | 51 + test/CodeGen/SystemZ/subregliveness-04.ll | 41 + test/CodeGen/WebAssembly/exception.ll | 2 +- test/CodeGen/WebAssembly/simd-arith.ll | 92 +- test/CodeGen/WebAssembly/simd.ll | 289 ++++ test/CodeGen/X86/avx2-intrinsics-canonical.ll | 167 ++ test/CodeGen/X86/avx2-intrinsics-fast-isel.ll | 36 +- test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll | 104 ++ test/CodeGen/X86/avx2-intrinsics-x86.ll | 158 +- test/CodeGen/X86/avx512bw-intrinsics-canonical.ll | 308 ++++ test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll | 792 ++++++++++ test/CodeGen/X86/avx512bw-intrinsics.ll | 277 ++-- .../CodeGen/X86/avx512bwvl-intrinsics-canonical.ll | 669 ++++++++ test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll | 1601 ++++++++++++++++++++ test/CodeGen/X86/avx512bwvl-intrinsics.ll | 1412 +++-------------- test/CodeGen/X86/combine-sdiv.ll | 789 ++++++++++ test/CodeGen/X86/oddshuffles.ll | 90 +- test/CodeGen/X86/prefer-avx256-mask-shuffle.ll | 9 +- test/CodeGen/X86/sdiv-exact.ll | 174 +-- test/CodeGen/X86/sibcall.ll | 109 ++ test/CodeGen/X86/speculative-load-hardening.ll | 2 +- test/CodeGen/X86/sse2-intrinsics-canonical.ll | 274 ++++ test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 72 +- test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll | 84 + test/CodeGen/X86/sse2-intrinsics-x86.ll | 84 - test/CodeGen/X86/vec-libcalls.ll | 559 +++++++ .../X86/vector-constrained-fp-intrinsics.ll | 456 ++++++ test/CodeGen/X86/vector-shuffle-256-v16.ll | 440 +++--- test/CodeGen/X86/vector-shuffle-256-v32.ll | 30 +- test/CodeGen/X86/vector-shuffle-256-v4.ll | 97 +- test/CodeGen/X86/vector-shuffle-256-v8.ll | 113 +- test/CodeGen/X86/vector-shuffle-512-v64.ll | 61 +- test/CodeGen/X86/vector-shuffle-avx512.ll | 36 +- test/CodeGen/X86/vector-shuffle-combining-avx2.ll | 49 + test/CodeGen/X86/vector-shuffle-combining-ssse3.ll | 65 + test/CodeGen/X86/vector-shuffle-combining.ll | 25 +- test/Demangle/ms-back-references.test | 2 - test/Demangle/ms-mangle.test | 18 +- test/Demangle/ms-return-qualifiers.test | 6 +- test/Instrumentation/cgprofile.ll | 2 +- test/ThinLTO/X86/cfi-devirt.ll | 10 +- .../CodeGenPrepare/X86/multi-extension.ll | 25 + .../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 149 ++ test/Transforms/InstCombine/X86/x86-adds-subs.ll | 351 +++++ test/Transforms/InstCombine/icmp-vec.ll | 19 +- test/Transforms/InstCombine/pow-1.ll | 235 +-- test/Transforms/InstCombine/pow-2.ll | 6 +- test/Transforms/InstCombine/pow-exp-nofastmath.ll | 15 +- test/Transforms/InstCombine/pow-exp.ll | 40 +- test/Transforms/InstCombine/pow-sqrt.ll | 265 +++- test/Transforms/InstCombine/select-binop-cmp.ll | 37 +- test/Transforms/InstCombine/xor-icmps.ll | 13 + test/Transforms/LICM/hoist-mustexec.ll | 26 + test/Transforms/LoopVectorize/no_outside_user.ll | 237 ++- test/tools/llvm-mca/AArch64/Exynos/pr38575.s | 82 + test/tools/llvm-readobj/elf-packed-relocs.test | 42 + test/tools/yaml2obj/elf-comdat-broken-info.yaml | 27 + test/tools/yaml2obj/elf-comdat-broken.yaml | 34 + test/tools/yaml2obj/reloc-sec-info.yaml | 25 + test/tools/yaml2obj/section-link.yaml | 25 + tools/llvm-mca/DispatchStage.h | 8 +- tools/llvm-mca/ExecuteStage.h | 15 +- tools/llvm-mca/FetchStage.h | 15 +- tools/llvm-mca/RetireStage.h | 17 +- tools/llvm-mca/Scheduler.cpp | 2 +- tools/yaml2obj/yaml2elf.cpp | 17 +- unittests/Analysis/BlockFrequencyInfoTest.cpp | 6 +- unittests/IR/DominatorTreeBatchUpdatesTest.cpp | 8 +- unittests/IR/MetadataTest.cpp | 26 +- unittests/Support/ErrorTest.cpp | 32 + utils/TableGen/CodeGenDAGPatterns.cpp | 2 +- utils/TableGen/CodeGenSchedule.cpp | 27 + utils/TableGen/CodeGenSchedule.h | 2 + utils/TableGen/FastISelEmitter.cpp | 11 +- utils/TableGen/InstrInfoEmitter.cpp | 21 +- utils/TableGen/PredicateExpander.cpp | 10 +- utils/TableGen/PredicateExpander.h | 8 +- utils/TableGen/SubtargetEmitter.cpp | 2 +- 235 files changed, 15348 insertions(+), 4158 deletions(-) create mode 100644 include/llvm-c/Error.h create mode 100644 include/llvm/IR/CFGDiff.h create mode 100644 include/llvm/Support/CFGUpdate.h create mode 100644 test/Analysis/AliasSet/guards.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/irtranslator-duplicate-types-param.ll create mode 100644 test/CodeGen/AArch64/vec-libcalls.ll create mode 100644 test/CodeGen/AMDGPU/fneg-combines.si.ll rename test/CodeGen/ARM/{arm-cgp-phis-calls-ret.ll => arm-cgp-calls.ll} (64%) create mode 100644 test/CodeGen/ARM/arm-cgp-phis-ret.ll create mode 100644 test/CodeGen/ARM/arm-cgp-pointers.ll create mode 100644 test/CodeGen/ARM/arm-cgp-signed-icmps.ll create mode 100644 test/CodeGen/PowerPC/pr38087.ll create mode 100644 test/CodeGen/RISCV/fixups-diff.ll create mode 100644 test/CodeGen/SystemZ/subregliveness-01.ll create mode 100644 test/CodeGen/SystemZ/subregliveness-02.ll create mode 100644 test/CodeGen/SystemZ/subregliveness-03.ll create mode 100644 test/CodeGen/SystemZ/subregliveness-04.ll create mode 100644 test/CodeGen/WebAssembly/simd.ll create mode 100644 test/CodeGen/X86/avx2-intrinsics-canonical.ll create mode 100644 test/CodeGen/X86/avx512bw-intrinsics-canonical.ll create mode 100644 test/CodeGen/X86/avx512bwvl-intrinsics-canonical.ll create mode 100644 test/CodeGen/X86/sse2-intrinsics-canonical.ll create mode 100644 test/CodeGen/X86/vec-libcalls.ll create mode 100644 test/Transforms/CodeGenPrepare/X86/multi-extension.ll create mode 100644 test/Transforms/InstCombine/X86/x86-adds-subs.ll create mode 100644 test/tools/llvm-mca/AArch64/Exynos/pr38575.s create mode 100644 test/tools/yaml2obj/elf-comdat-broken-info.yaml create mode 100644 test/tools/yaml2obj/elf-comdat-broken.yaml create mode 100644 test/tools/yaml2obj/reloc-sec-info.yaml create mode 100644 test/tools/yaml2obj/section-link.yaml -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[gcc] branch gcc-8-branch updated (64cea2ece1c -> 5fbd3db8bee)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-8-branch in repository gcc. from 64cea2ece1c Backport r263248 new 5fbd3db8bee Backporting two Arm fixes from mainline fixing PR86640 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 9 +++++++++ gcc/config/arm/arm.c | 5 +---- gcc/testsuite/ChangeLog | 8 ++++++++ gcc/testsuite/gcc.target/arm/pr86640.c | 10 ++++++++++ 4 files changed, 28 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/pr86640.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[toolchain/jenkins-scripts] branch llvm-kernel updated (5ddfbe8 -> 1741bf3)

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This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch llvm-kernel in repository toolchain/jenkins-scripts. discards 5ddfbe8 tcwg-rr-llvm-kernel.sh: New job script. new 1741bf3 tcwg-rr-llvm-kernel.sh: New job script. This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5ddfbe8) \ N -- N -- N refs/heads/llvm-kernel (1741bf3) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tcwg-rr-llvm-kernel.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[toolchain/jenkins-scripts] branch llvm-kernel updated (d85617b -> 5ddfbe8)

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This is an automated email from the git hooks/post-receive script. "Maxim Kuvyrkov pushed a change to branch llvm-kernel in repository toolchain/jenkins-scripts. discards d85617b tcwg-rr-llvm-kernel.sh: New job script. new 5ddfbe8 tcwg-rr-llvm-kernel.sh: New job script. This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d85617b) \ N -- N -- N refs/heads/llvm-kernel (5ddfbe8) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tcwg-rr-llvm-kernel.sh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

[lld] branch master updated (ee6d63fc4 -> 93bfc9004)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from ee6d63fc4 [LLD][ELF] - Add a test case. new 93bfc9004 [LLD][ELF] - Add a test case for DT_SONAME entry reading. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/ELF/invalid/invalid-soname.test | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 test/ELF/invalid/invalid-soname.test -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 3 months

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