Tcwg-commits July 2018

tcwg-commits@lists.linaro.org

5 participants
3004 discussions

[openmp] branch master updated (1224791 -> b636038)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository openmp. from 1224791 Dropped non-supoorted "--no-as-needed" flag from OMPT tests f [...] new b636038 Define the __STDC_FORMAT_MACROS to avoid test failure on some [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: runtime/test/ompt/callback.h | 5 +++++ 1 file changed, 5 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[glibc] branch master updated (3a885c1f51 -> bce5911b67)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 3a885c1f51 Build csu/elf-init.c and csu/static-reloc.c with stack protector new bce5911b67 Use AVX_Fast_Unaligned_Load from Zen onwards. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 7 +++++++ sysdeps/x86/cpu-features.c | 18 +++++++++++++----- 2 files changed, 20 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[gcc] branch master updated (669d54f7dd1 -> 4e6aac30df5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 669d54f7dd1 Simplify linker script patterns for std::exception_ptr new 4e6aac30df5 PR libstdc++/84928 use std::move in <numeric> algorithms The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/ChangeLog | 10 ++ libstdc++-v3/include/bits/stl_numeric.h | 27 +++-- .../testsuite/26_numerics/accumulate/lwg2055.cc | 93 +++++++++++++++ .../26_numerics/adjacent_difference/lwg2055.cc | 126 +++++++++++++++++++++ .../testsuite/26_numerics/inner_product/lwg2055.cc | 107 +++++++++++++++++ .../testsuite/26_numerics/partial_sum/lwg2055.cc | 125 ++++++++++++++++++++ 6 files changed, 480 insertions(+), 8 deletions(-) create mode 100644 libstdc++-v3/testsuite/26_numerics/accumulate/lwg2055.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/adjacent_difference/lwg2055.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/inner_product/lwg2055.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/partial_sum/lwg2055.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[llvm] branch master updated (023b04f4507 -> 2d706a67e35)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 023b04f4507 [AArch64] Armv8.4-A: TLB support new 2d706a67e35 [llvm-mca] A write latency cannot be a negative value. NFC The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tools/llvm-mca/InstrBuilder.cpp | 6 ++++-- tools/llvm-mca/Instruction.cpp | 4 ++-- tools/llvm-mca/Instruction.h | 10 ++++------ 3 files changed, 10 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 4 months

[toolchain/llvm/llvm] branch linaro-local/thomas.preudhomme/tcwg-1428-rebase updated (d731a63e1ae -> d6228f957a6)

by Thomas Preudhomme

This is an automated email from the git hooks/post-receive script. Thomas Preudhomme pushed a change to branch linaro-local/thomas.preudhomme/tcwg-1428-rebase in repository toolchain/llvm/llvm. discards d731a63e1ae TOCLEAN: adds variable expression discards 96ef41ce8c2 Support inline asm with multiple 64bit output in 32bit GPR discards 215a0ebb31d Fix crash on inline asm with 64bit matching input in 32bit GPR discards 7e980c295bd Fix PR34170: Crash on inline asm with 64bit output in 32bit GPR adds 9f2ffce7cdc TableGen: Allow foreach in multiclass to depend on template args adds 3bd8feb970a AMDGPU: Turn D16 for MIMG instructions into a regular operand adds 6694c8fd847 AMDGPU: Add implicit def of SCC to kill and indirect pseudos adds f474189510d AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM) adds 2b1cd517a0e TableGen/SearchableTables: Support more generic enums and tables adds db5003ee85e AMDGPU: Use generic tables instead of SearchableTable adds f6113ec066b AMDGPU: Refactor MIMG instruction TableGen using generic tables adds d42a61b0d4f AMDGPU: Select MIMG instructions manually in SITargetLowering adds 330c65751e0 AMDGPU: Convert test cases to the dimension-aware intrinsics adds 7f7cea53068 InstCombine/AMDGPU: Add dimension-aware image intrinsics to [...] adds 4c3fa871b5a AMDGPU: Remove old-style image intrinsics adds ec3300aa1eb AMDGPU: Remove redundant MIMG instruction variants adds 21650449492 [CodeGen] Avoid handling DBG_VALUE in LiveRegUnits::stepBackward adds 11ef9aa12e6 [llvm-exegesis][NFC] Simplify LLVMState. adds 660c8bd9ccd [x86] Lower some trunc + shuffle patterns to vpmov[q|d][b|w] adds 016054315fd [RISCV] Tail calls don't need to save return address adds 34d9682fc55 [llvm-exegesis][NFC] Simplify BenchmarkRunner. adds a3ff01d1016 [NFC][ARM] ldrd/strd negative tests adds e43452878c7 [InstCombine] make div/rem vector constant utility function; NFCI adds 3cd5aad15cf [ARM] Enable useAA() for the in-order Cortex-R52 adds 8f072ac5b47 DAG combine "and|or (select c, -1, 0), x" -> "select c, x, 0|-1" adds 3080dcbe49e Revert "[AArch64] Coalesce Copy Zero during instruction selection" adds 22a1ef14bd6 [DWARF] Warn on and ignore ".file 0" for DWARF v4 and earlier. adds 2c7b1285044 [X86] Update fast-isel tests for clang r335253. adds baa9ccee642 [LoopVectorize] regenerate full checks; NFC adds 1a4304a1326 [InstCombine] simplify binops before trying other folds adds 7cf22ab2fa6 [InstCombine] add vector icmp tests with undefs; NFC adds 83601e52b86 [InstCombine] use constant pattern matchers with icmp+sext adds 50feec5fc15 [DebugInfo] Ignore DBG_VALUE instructions in PostRA Machine Sink adds e9f0bb45ca2 [InstCombine] add tests for shuffled cmps; NFC adds 3316883bba1 AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z and everythin [...] adds cbeaa8b0e2b [AMDGPU] Fix bug with tracking processed blocks in SIInsert [...] adds 8070954cd26 [mips] Modify comment to test new email address (NFC). adds 5119d140c56 Revert r335206 "Recommit r333268: [IPSCCP] Use PredicateInf [...] adds 43cbf8d92e1 [AMDGPU] Update assembler for HSA Code Object v3 adds d7f1ecfded0 [InstCombine] fold vector select of binops with constant op [...] adds 845b439bb4d [mingw] Fix GCC ABI compatibility for comdat things adds 13b063fc366 AMDGPU: Remove ability to reserve VGPRs for debugger adds 2c2fae3d83a [SCEV] Re-apply r335197 (with Polly fixes). adds 01b1faf66c2 [dsymutil] Force mmap'ing of binaries adds f257d99f7ac [GVN] Avoid casting a vector of size less than 8 bits to i8 adds 85adb3cc4d3 [X86] Implement more of x86-64 large and medium PIC code models adds 4f887057969 [X86] Commit some comments that weren't in the medium code [...] adds b3881872a5b Revert r335297 "[X86] Implement more of x86-64 large and me [...] adds e204dd61053 [IR] fix typo in comment; NFC adds 7bbbb631136 [AMDGPU] Fix lit failures introduced in r335281 adds ebb24b101d3 [gdb] Update llvm::Optional adds b9c0a17b9f2 [X86] Fix 32-bit mingw comdat names, only add one underscore adds 3499852bee2 [Instrumentation] Add Call Graph Profile pass adds 0225aa982fb AMDGPU/GlobalISel: Implement select() for G_IMPLICIT_DEF adds d8c64fc2479 [InstCombine] add test for shuffle-of-binops; NFC adds 7fe9364c8bd [InstCombine] fix shuffle-of-binops bug adds 56a5b2a5021 Fix test failures after r335306 due to the pipeline changing. adds b93460fa625 AMDGPU/GlobalISel: Implement select() for COPY adds 20f413f83a2 AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP adds 762b38dd8c7 [LegacyPM] Fix PR37888 by teaching the legacy loop pass man [...] adds 3e9055c7ee0 AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR adds fc57ceaf39a AMDGPU/GlobalISel: Default to using TableGen'd instruction [...] adds 8e0778c059f Revert r335306 (and r335314) - the Call Graph Profile pass. adds 516c1f140bf [X86] Changing the check for valid inputs in combineScalarToVector adds 71f8b0dc815 [Evaluator] Improve evaluation of call instruction adds ae175dfe4a8 AMDGPU: Add patterns for i32/i64 local atomic load/store adds 2ee51272b7b [ARM] ARMv6m and v8m.baseline strict align adds 5af2b9cbf51 Revert r335324 due to a builtbot failure adds 5f1676b4d69 Reverting r335326 while I look at the test failure adds 444b60212b3 [CostModel][AArch64] Add some initial costs for SK_Select a [...] adds 9104c92c0b2 Recommit of r335326, with the test fixed that I missed. adds 08d6b0d9f09 [MC] - Add .stack_size sections into groups and link them w [...] adds 51ddc3757af Revert r335332 "[MC] - Add .stack_size sections into groups [...] adds 0b0278f11bc [IR] Use Instruction::isBinaryOp helper instead of raw enum [...] adds af362952328 Recommit r335333 "[MC] - Add .stack_size sections into grou [...] adds 4578386457e [X86] Add notes to a few intrinsics adds dce4487f88e [X86] Regenerate tests to include fma comments adds bbfb91da0db [InstCombine] rearrange shuffle-of-binops logic; NFC adds a054f92cdc4 [InstCombine] add tests for shuffle-with-different-binops; NFC adds bcfb546743a [InstCombine] add shuffle+binops test from PR37806; NFC adds 1c5cdb19a65 [SLPVectorizer][X86] Add alternate opcode tests for simple [...] adds ae9a1a8ee73 [SLPVectorizer] Relax alternate opcodes to accept any Binar [...] adds fe16001dba2 [DWARFv5] Allow ".loc 0" to refer to the root file. adds ee3b840397f Fix test, nop is not always 1 byte adds 2b353500d1f Fix test again, try to keep all targets happy adds 6c358ea8178 [SLPVectorizer] reorderAltShuffleOperands should just take [...] adds 6299c235bdb [llvm-mca] Introduce a sequential container of Stages adds e0f992ea7d9 [llvm-mca] Set the operand ID for implicit register reads/w [...] adds 5a40cf86395 [SLPVectorizer] Support alternate opcodes in tryToVectorizeList adds d407e550d93 Initialize LiveRegs once in BranchFolder::mergeCommonTails adds 2191fc0b67c [X86] Add a test to show missed opportunity to generate vfnmadd adds 18c02e94e56 [llvm-mca] Remove redundant call. NFC adds 53f3ded93d2 [LoopUnswitch]Fix comparison for DomTree updates. adds 8a152c54c40 [X86] Don't allow ESP/RSP to be used as an index register i [...] adds b6b723f1bfa [X86][AsmParser] Check for invalid 16-bit base register in [...] adds be92ae330e4 [X86][SSE] Add sdiv by (nonuniform) minus one tests (PR37119) adds d6794f0ba70 AMDHSA: Put old assembler docs back adds 122aad957dc [X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encode [...] adds 528e0780e70 [X86] Don't accept (%si,%bp) 16-bit address expressions. adds aa1b399a8ef Re-land "[LTO] Enable module summary emission by default fo [...] adds c22e38d4bb9 [gdb] Use Latin-1 to decode StringRef adds d327d4b2a87 [GISel]: Add G_ADDRSPACE_CAST Opcode adds 3d48ff1d0ac [X86] Add test cases showing missed select simplifcation fo [...] adds 5fd79cfd40a [PowerPC] add tests for bit hacking opportunities with setcc; NFC adds 3a06bb23c20 [x86] add tests for bit hacking opportunities with setcc; NFC adds 5db13ccfe97 [llvm-mca] Remove unnecessary include and forward decl in R [...] adds 7259aa5c9bc [X86][AsmParser] In Intel syntax make sure we support ESP/R [...] adds 31d9a1568ae [PowerPC] add more tests for bit hacking opportunities with [...] adds 3d59bc03425 [x86] add more tests for bit hacking opportunities with setcc; NFC adds a64c3aa1f5d [llvm-size] Make global variables static adds 61a101317c7 [X86][AsmParser] Keep track of whether an explicit scale wa [...] adds 78cd292954d [MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFC adds ea67fb768b2 [LoopReroll] Rewrite induction variable rewriting. adds 10fa02975bc [RuntimeDyld] Implement the ELF PIC large code model relocations adds ba5eea78819 [X86][AsmParser] Rework that allows (%dx) to be used in pla [...] adds 98ae3708b44 [ELF] Change isSectionData to exclude SHF_EXECINSTR adds dc14c20b63e Avoid including intrin.h from MathExtras.h adds af7c445dfa1 [IR] Split Intrinsics.inc into enums and implementations adds adc5f0ab257 [ORC] Fix formatting and list pending queries in VSO::dump. adds 00f00bab006 [AMDGPU] Update includes for intrinsic changes :( adds 17957ec5e50 Fix invariant fdiv hoisting in LICM adds af8308f06ae [X86][AsmParser] Improve base/index register checks. adds 4fc14da1fc9 [X86] Teach disassembler to use %eip instead of %rip when 0 [...] adds b457430300d [X86] Make %eiz usage in 64-bit mode, force a 0x67 address [...] adds 9fa78621e77 [TableGen] Use WithColor for printing errors/warnings adds fb0b759b0a2 [llvm-mt] Use WithColor for printing errors. adds fc6fcece238 [llvm-config] Use WithColor for printing errors. adds 304292110d0 [llc] Use WithColor for printing errors/warnings adds d417685a32a ADT: Use EBO to shrink SmallVector size 1 adds 7cde7d986ff [llc] Fix sanitizer failure. adds 4a7b6910075 [CMake] Support building shared library for OpenBSD adds bd075060f18 [CMake] Do not use --gc-sections on OpenBSD adds e57f6fb05fc Add OpenBSD support to the Threading code adds 009107f3d68 Also forward declare BitScanReverse. adds d153721e94b [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction [...] adds 8fe400a66e7 [X86] Regroup some isel patterns. NFC adds af1e6f153f0 [DAGCombiner] eliminate setcc bool math when input is low-b [...] adds ad8f413c533 [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mip [...] adds 37b9e499fc4 [X86] Reduce the number of patterns needed for masked scala [...] adds 7b76b3ec917 [X86] Remove the changes to combineScalarToVector made in r335037. adds fb9ef323663 [X86] Simplify some code by using isOneConstant. NFC adds 6aa7ab2443d [WebAssembly] Add WebAssemblyLateEHPrepare pass adds ad04e25e240 [WebAssembly] Add WebAssemblyException information analysis adds 19eaf65da0f Add a TaskQueue that can serialize work on a ThreadPool. adds aec098b9245 Fix CRLF line endings. adds 1d3a8f2bbbc Try to fix build error on non MSVC compilers. adds 761de657153 One more build fix for non MSVC compilers. adds 5804675605b [MSSA] Add domination number verifier; NFC adds 9625701b0d4 [X86] Block commuting operand 1 of FMA*_Int instructions in [...] adds 47c8e1d5eb0 [llvm-exegesis][NFC] Fix `Operand` class comments. adds c846c8b55ed Fix -Wparentheses gcc warning. NFCI. adds 534c5d4317e [llvm-exegesis][NFC] clang-format adds 4e7cfd69f5c Use APInt[] bit access to avoid "32-bit shift implicitly co [...] adds 512d410a6b9 [llvm-exegesis][NFC] Simplify BenchmarkRunner ctor. adds a2181998a78 Use APInt[] bit access to avoid "32-bit shift implicitly co [...] adds a8f90c09916 Revert change 335091. adds 647fa5f2e68 Revert change 335077 "[InlineSpiller] Fix a crash due to la [...] adds 15fac97085c [llvm-exegesis] Generate snippet setup code. adds 4025e96cad4 [llvm-exegesis] Fix warning in r22752: Initialize IsSnippet [...] adds 0c43400bbd5 [IR] avoid -Wdocumentation spew about HTML tags adds 14a520d8321 [llvm-exegesis][NFC] Remove unnecessary member variables. adds ce1c8d90ff4 Improve handling of COPY instructions with identical value numbers adds c39bf69d806 SafepointIRVerifier should ignore dead blocks and dead edges adds d3d2228f8c6 AMDGPU: Respect align argument parameter adds 084d7ce7aa7 [DA] Delinearise AddRecs if we can prove they don't wrap adds ba791754878 [SampleFDO] Add an option to turn on/off warning about samp [...] adds c4c340a047c AMDGPU/GlobalISel: Fix G_IMPLICIT_DEF for pointers adds b34fc164bd8 AMDGPU: Remove commented out code adds a26c784064a StackSlotColoring: Decide colors per stack ID adds 529b26551c9 AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr adds e8508360bc0 Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFC adds d8c387b1dd3 [llvm-mca] Rename Backend to Pipeline. NFC. adds f1fc2a32d73 [SelectionDAG] Remove debug locations from ConstantSD(FP)Nodes adds 5ae690aaab8 [X86] Allow base and index for gather instructions to appea [...] adds 3dbf0c9ce7f [X86] Sort the static memory folding tables by reg opcode. [...] adds 6ff63714d1c [GISel]: Update the end of GISel Opcode namespace. adds 88313d288df [InstCombine] add tests for add-of-sext-bool; NFC adds 2d21bce8d98 Re-land r335297 "[X86] Implement more of x86-64 large and m [...] adds e51396c3aeb [InstSimplify] add tests for div/rem with bool divisor; NFC adds 993ef0ca960 Handle NetBSD specific path in findDebugBinary() adds df0d594dd00 [InstSimplify] fold div/rem of zexted bool adds c1803abd1bb [SCEVExp] Advance found insertion point until we find a non [...] adds d8832d436ca [PowerPC] Fix incorrectly encoded wait instruction adds 5223dab9bee [docs] Update doc after split of -gen-intrinsic in r335407 adds 8a3f60e9851 [X86] Add comment about the sorting of the memory folding t [...] adds c5dd80a9d0e [X86] Simplify intrinsic table binary search to not require [...] adds a972a2e1ff7 Force vector width for scev-expander-debug.ll test adds 92a88d2ee38 [LoopIdiomRecognize] Fix a couple places where it appears w [...] adds 26ac94ddde4 Revert r335513: [SCEVExp] Advance found insertion point adds fad81756be0 UBSan blacklist workaround for bot timeouts adds b191d76053e [InstCombine] add tests for sdiv with sext bool divisor; NFC adds 9aa6823d820 [InstCombine] fold sdiv with sext bool divisor adds 5c3069979f1 [Instrumentation] Remove unused include adds aff0591efb5 [InstCombine] add/move tests for udiv; NFC adds d3b9487abb7 [InstCombine] cleanup udiv folds; NFCI adds 6eef3c63b25 Fix unsigned/signed comparison failure in unittest. adds cde39cece92 [OrcMCJIT] Fix test after r335508 causing it to fail on gre [...] adds 560c9c479f7 [X86] Update fpclass intrinsic tests to chain their calls t [...] adds 224904bf2c5 [PM/LoopUnswitch] Teach the new unswitch to handle nontrivi [...] adds 649e247b1c5 [gdb] Add pretty printer for Expected adds 5e785b9abda [APInt] Add helpers for rounding u/sdivs. adds 39add80ac56 Add a warning if someone attempts to add extra section flag [...] adds 4c45b898f09 [ThinLTO] Compute GUID directly from GV when building per-m [...] adds d411816d5c3 [gdb] Escape unprintable bytes in SmallString and StringRef adds 60f122c15f7 foo adds 0b6ddca1f37 [X86] Redefine avx512 packed fpclass intrinsics to return a [...] adds 7ca1126ca83 [ORC] Add a symbolAliases function to the Core APIs. adds 00cc8d0f099 Revert r335562 and 335563 "[X86] Redefine avx512 packed fpc [...] adds 633b851c9ab [ThinLTO] Add per-module indexes to combined index consistently adds d1d8627cf4c [X86] Redefine avx512 packed fpclass intrinsics to return a [...] adds 1cc13e5ad13 [ThinLTO] Add string saver onto index for value names adds 0135f2ae728 [WebAssembly] Fix a typo in a comment. adds 682da16f995 [X86] Use XOR for SUB (C, X) during isel if will help fold [...] adds 2da9f1a84d0 [WebAssembly] Fix lowering of varargs functions with non-le [...] adds 02ed557da0c [X86] Don't use getScalarShiftAmountTy to get the immediate [...] adds d7d68723b85 [InstCombine] (A + 1) + (B ^ -1) --> A - B adds 2079dc34cb0 Improve ConvertDebugDeclareToDebugValue adds 32a7d0f17dd [NFC] Prefer (void) to LLVM_ATTRIBUTE_UNUSED for unused var [...] adds d6bc0c7274d [llvm-exegesis] Get the BenchmarkRunner from the ExegesisTarget. adds 713ebb15587 Fix MSVC "not all control paths return a value" warnings. NFCI. adds 94a670b38e5 [AArch64] Clean up LSE directive tests adds 179cff63927 [AArch64] Tighten up directives tests adds be2419a2acf Fix MSVC "signed/unsigned mismatch" warning. NFCI. adds 1766212247a [IPSCCP] Change dead blocks to unreachable after visiting a [...] adds 2f2d460c914 [llvm-mca] Remove unused header files and correctly guard s [...] adds 823657d43f9 [X86] Just use ArrayRef instead of SmallVectorImpl in a few [...] adds a34afb03345 [llvm-exegesis][NFC] Fix windows warning in rL335465. adds cf4a1ccdffc [llvm-mca] Removed wrong NDEBUG guards introduced by my las [...] adds 43f589a4df3 ARM: diagnose unpredictable IT instructions adds a32cfd263d6 ARM: correctly decode VFP instructions following unpredicta [...] adds 67ad29ab383 ARM: add binary file git swallowed. adds 86366d2a15d [InstCombine] fold udiv with sext bool divisor adds c6dda905a6c [ThinLTO] Parse module summary index from assembly adds 799df9565bf Fix spelling mistakes in comments. NFCI. adds 61f67f4637f [X86,ARM] Retain split-stack prolog check for sibling calls adds f2d90857daf [TargetLowering] isVectorClearMaskLegal - use ArrayRef<int> [...] adds 2c45bcb3993 Account for undef values from predecessors in extendSegmentsToUses adds 7b36ec6b5e1 Fix LLVM_ENABLE_THREADS=0 builds after r335440. adds a301ecd20b0 [InstSimplify] add tests for srem with sext bool divisor; NFC adds e873939bd3e Silence "unused variable" warning in LiveIntervals.cpp afte [...] adds 583ccd4384c [FileCheck] Add CHECK-EMPTY directive for checking for blank lines adds 3e90a9b8c8a Fix doc title underlining. adds 7706083ace4 [InstSimplify] fold srem with sext bool divisor adds 007404388ee [DAGCombiner] Pull out VT bitwidth in visitSDIV. NFCI. adds 0c1dedd8edc [InstCombine] add tests for urem with sext bool divisor; NFC adds 40be0055aea [SLPVectorizer] Recognise non uniform power of 2 constants adds e9e5731866d [InstCombine] fold urem with sext bool divisor adds 41f2034b16d [InstCombine] simplify code for urem fold; NFCI adds 5399eba9f5d [X86][SSE] Add another sdiv by (nonuniform) minus one test [...] adds 84f6f2281a5 [InstSimplify] add tests for shifts by sext bool; NFC adds 5f8dac19296 [InstSimplify] fold shifts by sext bool adds 0fde67787aa Move `REQUIRES:` line to the top adds 67cc73d7b24 [DAGCombiner] Don't accept -1 sdiv divisors in sdiv-by-pow2 [...] adds 6b3e4d2fb7a [Hexagon] Add a "generic" cpu adds 6a78ba2a8c2 [Local] Sink salvageDI's early exit into helper functions, NFC adds 99917384c89 [Local] Add a convenient insertReplacementDbgValues overload, NFC adds 93ae5a35afc LoopUnroll: Allow analyzing intrinsic call costs adds e64a8288ae1 [ConstantRange] Add support of mul in makeGuaranteedNoWrapRegion. adds 9253369f66e [Debugify] Don't treat missing dbg.values as an error (PR37942) adds 8d224a36c1c Use a variable to appease a no-asserts bot, NFC adds 737191dd296 ConstantFold: Don't fold global address vs. null for addrsp [...] adds a2ba13d7317 AMDGPU: Add pass to lower kernel arguments to loads adds 95b187a7ddf [DAGCombiner] use isBitwiseNot to simplify code; NFC adds aac117a9ba2 [AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic adds 34ffe04f30e [X86][AsmParser] Emit an error when RIP-relative instructio [...] adds daa6db3e25b Revert "[X86][AsmParser] Emit an error when RIP-relative in [...] adds fdc08234d7e [ORC] Fix a FIXME by moving MangleAndInterner to Core.h. adds 2338ba3e110 [ORC] Add a FIXME. adds 6ccd1b1e5be [ORC] Move the VSOList typedef out of VSO. adds b525a3a6390 [ORC] Reset AsynchronousSymbolQuery's NotifySymbolsResolved [...] adds 89e0af6b105 [ORC] Allow IRTransformLayer2's transform to be modified af [...] adds ab0a33b6a77 Rename skipDebugInfo -> skipDebugIntrinsics, NFC adds 9e1483fe741 [X86][AsmParser] Recommit r335658 adds 784d2a84999 AMDGPU: Silence unused warnings in waitcnt insertion pass i [...] adds 9f1c2395ce1 [ORC] Add LLJIT and LLLazyJIT, and replace OrcLazyJIT in LL [...] adds 0e00ed71fae [X86] Add test for SDIV by sign bit (minsigned) value adds ab8689e932e [ORC] Add a dependence on MC to LLVMBuild.txt adds d3c8f20a14b [JumpThreading] Don't try to rewrite a use if it's already valid. adds 1d0cbe2918c [ORC] Fix a missing return value. adds 1b30e51a073 [ORC] Don't call isa<> on a null value. adds 0ed99e80c71 Revert "[asan] Instrument comdat globals on COFF targets" adds acc979319bb [Debugify] Diagnose mis-sized dbg.values adds 06f46b29d52 [X86] Don't store register and memory FMA3 opcodes in the s [...] adds 3dbfeaffe7a [Debugify] Handle failure to get fragment size when checkin [...] adds bde65c4dd97 [InstCombine] Avoid creating mis-sized dbg.values in common [...] adds 0f220def93e [llvm-mca] Add a comment to Stage::execute and fix a spelli [...] adds 2051d2558e7 [ADT] Pass DerivedT from pointe{e,r}_iterator to iterator_a [...] adds c2fa8e709e9 [CMake] Use variables rather than ":" delimiters adds 70b7a2fd32c [CMake] Provide direct support for building sanitized runtimes adds 78d083b50fd AMDHSA/NFC: Address missed review feedback from https://rev [...] adds 80681820212 AMDHSA: Rename RESERVED -> RESERVED0, mark gfx9-specific field adds fe1e7736763 AMDGPU/NFC: Fix typo in comment adds 4187c135cfd [AArch64] Remove Duplicate FP16 Patterns with same encoding [...] adds 3a09592b608 Removing empty CodeGen dir in root adds 1f74921dd71 [DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by [...] adds 988e5b9752d [DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN [...] adds 8a57afce61d [DAGCombiner] visitSDIV - simplify pow2 handling. NFCI. adds a62a0a38355 [X86][SSE] Include MIN_SIGNED element in non-uniform SDIV p [...] adds 0093dbb5fc2 [llvm-mca] Avoid calling method update() on instructions th [...] adds 823c169bec7 Build TaskQueueTest in threads=on builds, fixes regression [...] adds 16742ac8e4b [DAGCombiner] visitSDIV - add special case handling for (sd [...] adds a0883e04578 [ValueLattice] Return false if value range did not change i [...] adds 212054e1a97 [NEON] Support vldNq intrinsics in AArch32 (LLVM part) adds 751c17bfa03 [AArch64] Add custom lowering for v4i8 trunc store adds b5a170b9c2e [AArch64] Reverting FP16 vcvth_n_s64_f16 to fix adds bc547571e75 [AMDGPU] Convert rcp to rcp_iflag adds 480d03dbeb9 [X86] Rename the autoupgraded of packed fp compare and fpcl [...] adds 966cfbb5c29 [X86][SSE] Add missing AVX512 rotation tests adds 90b999fed8f [llvm-mca] Register listeners with stages; remove Pipeline [...] adds 928fea20d30 [dsymutil] Move abstractions into separate files (NFC) adds bdacec9c4a9 [AliasSet] Fix UnknownInstructions printing adds aa5b675322e [X86] Add test cases for D48606. adds 52753df4e21 [X86] Use bts/btr/btc for single bit set/clear/complement o [...] adds c86651469ca [InstCombine] add more tests for shuffle with different bin [...] adds 43d4585d619 [MachineOutliner] Don't outline sequences where x16/x17/nzc [...] adds f602599e6b3 [Object] Allow iterating over an IRObjectFile's modules adds 752939e86ab [ThinLTO] Print names in function import debug messages whe [...] adds 3d6697fe50b [DAGCombiner] restrict (float)((int) f) --> ftrunc with no- [...] adds 4b6501ab453 [ThinLTO] Modify test to help diagnose bot failures adds a75001c8dbd [ThinLTO] Fix test adds 576283c1191 [globalisel][legalizer] Add AtomicOrdering to LegalityQuery [...] adds 65fb103bddb [X86] Teach the disassembler to use %eiz/%riz instead of No [...] adds df04b22195f [X86] Fix unmatched parenthesis in r335768 adds d7295192d1a [WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll adds 857aa39725c [ADT] drop_begin: use adl_begin/adl_end. NFC. adds f162464ba81 [DAGCombine] Disable TokenFactor simplifications when optnone. adds 4fc1c001a75 Document the git config for Windows to do line-endings correctly. adds 45f68e6a2eb [InstCombine] add tests for vector-select-of-binops with 2 [...] adds 84e5dbffd78 [llvm-objdump] Add -x --all-headers options adds 78e3c70281b [RISCV] Add machine function pass to merge base + offset adds 9f60a34c354 [X86] In X86DAGToDAGISel::PreprocessISelDAG, make sure we d [...] adds 4b0e4cbeb2f [X86] Make folding table checking threadsafe adds 6a89efb6b2d Move some code from PDBFileBuilder to MSFBuilder. adds 71b21d8fccb Add support for generating a call graph profile from Branch [...] adds 09b856ac453 [CGProfile] Fix unused variable warning. adds 5dc174cf3bf [cmake][xcode-toolchain] add support for major Xcode version >= 10 adds 7e0591f5b86 [X86] Change how we prefer shift by immediate over folding [...] adds f5d15403005 [X86] Use PatFrag with hardcoded numbers for FROUND_NO_EXC/ [...] adds d9df72a18eb Support for multiarch runtimes layout adds e1714df0ef0 [DwarfDebug] Remove unused argument (NFC) adds ff524783991 [llvm-exegesis] Add partial X87 support. adds 3eb8221ad97 [IndVarSimplify] Ignore unreachable users of truncs adds 5016671ee05 [DAGCombiner] Remove unused variable. NFCI. adds e6a8acefb8f [SCCP] Mark CFG as preserved. adds 5796a8d8718 [DAGCombiner] Ensure we use the correct CC result type in v [...] adds d241bc3accb Unify sorted asserts to use the existing atomic pattern adds 5f4316253c2 AMDGPU: Fix assert on aggregate type kernel arguments adds 2f8e5b3099f AMDGPU: Fix AMDGPUCodeGenPrepare using uninitialized AMDGPU [...] adds fe32d1437e3 AMDGPU: Error on calls from graphics shaders adds 90f8cc80db5 AMDGPU: Remove MFI::ABIArgOffset adds 8f542571d7b s/TablesChecked/TableChecked/ after r335823 adds 9d41c557cbe Comment change to verify commit rights. NFC. adds 5652271db1a [llvm-mca] Refactor method RegisterFile::collectWrites(). NFCI adds d5b753a85d9 ADT: Move ArrayRef comparison operators into the class adds 3d172cd8f95 Revert "ADT: Move ArrayRef comparison operators into the class" adds ee2becd7045 [ARM] Parallel DSP Pass adds 1bbef2cc89f Revert "Add support for generating a call graph profile fro [...] adds 106ffb91691 Add a PhiValuesAnalysis pass to calculate the underlying va [...] adds ea63d873c8a [dsymutil] Use UnitListTy consistently (NFC) adds 6859f8aaa97 [DEBUG_INFO, NVPTX] Add test for .debug_loc section, NFC. adds 97e3954d2a0 [PhiValues] Adjust unit test to invalidate instructions bef [...] adds 8746f255cda [AMDGPU] Overload llvm.amdgcn.fmad.ftz to support f16 adds a2237ff0e5a [llvm-mca] Use a WriteRef to describe register writes in cl [...] adds 0e7f42b6394 [AMDGPU] Early expansion of 32 bit udiv/urem adds 4f08eb3e6db [llvm-mca][x86] Add 3dnow! resource tests adds 8e2dac622af [llvm-mca][x86] Add FMA4 resource tests adds 5ed53954fb6 Revert "[DAGCombiner] Ensure we use the correct CC result t [...] adds bd0a2a58e5b [MachineOutliner] Add always and never options to -enable-m [...] adds 294ff667fed SelectionDAGBuilder, mach-o: Skip trap after noreturn call [...] adds 9c7c10e4073 [MachineOutliner] Never add the outliner in -O0 adds be2cdf90a35 Revert "[MachineOutliner] Never add the outliner in -O0" adds 9bc4099b799 Revert "[MachineOutliner] Add always and never options to - [...] adds abd5dd61fc9 [WebAssembly] Add getSetCCResultType placeholder override t [...] adds 39d2c2868cb [llvm-mca] Delete Pipeline's copy ctor and assignement operator. adds 93aa3932e77 [DAGCombiner] Ensure we use the correct CC result type in v [...] adds d6b8d8c07b4 [MachineOutliner] Define MachineOutliner support in TargetOptions adds 25be6bdd6fc [InstCombine] allow shl+mul combos with shuffle (select) fo [...] adds e7de33fcf27 Set line ending style of llvm.natvis to CRLF. adds a924a78e8a4 2 VS natvis improvements. adds 3e2aa5b2f64 Revert "[OrcMCJIT] Fix test after r335508 causing it to fai [...] adds 3695b5379bf Revert "Re-land r335297 "[X86] Implement more of x86-64 lar [...] adds b2408daddbd [X86] Suppress load folding into and/or/xor if it will prev [...] adds 3d7cc9ef304 [Debugify] Do not report line 0 locations as errors adds a71c03687f3 [CMake] Respect CMAKE_STRIP and CMAKE_DSYMUTIL on apple platforms adds be8c3633e05 Remove unnecessary semicolon. NFCI. adds 822461008d3 Add a flag to FileOutputBuffer that allows modification. adds 3605e121fbd Handle absolute symbols as branch targets in disassembly. adds fbc17042e9c [SROA] Preserve DebugLoc when rewriting alloca partitions adds 7540b28963a Some targets don't have lld built, so just use a binary cop [...] adds 8f59c35cfad [ARM] Add missing Thumb2 assembler diagnostics. adds f104e589ce8 [NVPTX] Delete dead code adds 1dc0b96afda [ThinLTO] Port InlinerFunctionImportStats handling to new PM adds c8bdc2e0339 Fix padding with custom character in formatv. adds d628d72dc94 [COFF] Fix constant sharing regression for MinGW adds 83bc27f0aaa [InstCombine] fix opcode check in shuffle fold adds 540a311718e [SupportTests] Silence -Wsign-compare warnings adds eefdbb43aab [llvm-readobj] Add experimental support for SHT_RELR sections adds 87b704f790d [InstCombine] adjust shuffle tests; NFC adds 519acca3343 [MachineOutliner] Never add the outliner in -O0 adds 5ff4fbf6b8b [ARM] Assert that ARMDAGToDAGISel creates valid UBFX/SBFX nodes. adds c1d6c4ab99f Require x86 for this test. adds cba2181e776 AMDGPU: Separate R600 and GCN TableGen files adds a233e5b07ac [X86] Remove masking from the avx512 packed sqrt intrinsics [...] adds 4d942d9e7ec Make email options of find_interesting_reviews more flexible. adds 998f8604339 SCEVExpander::expandAddRecExprLiterally(): check before cas [...] adds 663484452ec [ARM][AArch64] Armv8.4-A Enablement adds ab4b844b3e6 [X86][SSE] Support v16i8/v32i8 vector rotations adds 886c551da5c [cmake] Change WIN32 test to CMAKE_HOST_WIN32 adds 548039bed15 [AArch64] Armv8.4-A: Virtualization system registers adds ecdc1aafd0c Fix overconfident assert in ScalarEvolution::isImpliedViaMe [...] adds ce6e09c7405 [InstCombine] enhance shuffle-of-binops to allow different [...] adds 3b81d99e576 [Hexagon] Remove unused instruction itineraties, NFC adds 6882f03fec6 [DEBUG_INFO, NVPTX] Do not emit .debug_loc section. adds 4e9529bf924 [llvm-mca] Remove field HasReadAdvanceEntries from class Re [...] adds 6e44255b70d [InstCombine] add more tests for shuffle-binop folds; NFC adds d1bf1e83362 [MachineOutliner] Add always and never options to -enable-m [...] adds 0e1a98e2552 [AMDGPU] Enable LICM in the BE pipeline adds ada03192b6d [mips] Support shrink-wrapping adds 4d3e6c13b68 [dsymutil] Introduce a new CachedBinaryHolder adds 9f33bbfea84 [dsymutil] Make the CachedBinaryHolder the default adds 03cec5cbaf0 [X86] Use a std::vector for the memory unfolding table. adds d36457d104a [dsymutil] Rename conflicting declaration adds 8b6f52ae8e8 Extend CFGPrinter and CallPrinter with Heat Colors adds bb9abb7e0d9 [X86] Limit the number of target specific nodes emitted in [...] adds eac8acfa949 AMDGPU: Don't use struct type for argument layout adds 551913f7e3a Revert "Extend CFGPrinter and CallPrinter with Heat Colors" adds 459351c7056 Pass DWARFUnit to verifier by reference not by value. I am [...] adds c55ef4741ac [LLVMContext] Detecting leaked instructions with metadata adds 1c3bbb46642 [HWASan] Do not retag allocas before return from the function. adds d1ed9d650dd [MemorySSA] Add APIs to MemoryPhis to delete incoming block [...] adds d2312611412 [WebAssembly] Comment out a switch block in ISelDAGToDAG adds a70dcefd9a5 [WebAssembly] Update comments for non-splat pow2 vector test case adds 7ce035b5346 [CodeView] Correctly compute the name of S_PROCREF symbols. adds b2b950d7b11 [instsimplify] Move the instsimplify pass to use more obvio [...] adds 8c0bb2f0365 [X86] Remove masking from avx512 rotate intrinsics. Use sel [...] adds c549767db5a [MachineOutliner] Add support for target-default outlining. adds 8eb696d509e AMDGPU/GlobalISel: Make IMPLICIT_DEF of all sizes < 512 legal. adds 1242dda03b7 [X86] Remove test cases from avx512vl-intrinsics-fast-isel. [...] adds 81f95d68a1f [X86] Change some chec-prefixes from X32 to X86 to match th [...] adds 6451a6d6f65 [X86] Update some avx512 fast-isel tests to match their rea [...] adds 985808d7ef5 [DAGCombiner] Handle correctly non-splat power of 2 -1 divi [...] adds 59222a5ca60 Fix Wdocumentation compiler warning. NFCI. adds 4d00d7aadb6 [InstCombine] add tests for negate vector with undef elts; NFC adds 04292f96693 [X86] When combining load to BZHI, make sure we create the [...] adds bfb044eaa54 [X86] Use MVT::i8 for scalar shift amounts since that is wh [...] adds 8dc6c5c5dae [X86] Remove the AsmName from the HAX,HDX,HCX,HBX,HSI,HDI,H [...] adds 16815e99bba [X86] Move the X86InstrFMA3Info class into the cpp file. Ex [...] adds ed5068fcf14 [X86] Move the memory unfolding table creation into its own [...] adds bae31892274 [X86] Remove unnecessary include. NFC adds 0de2000b2d0 [llvm-readobj] Fix printing format adds eaabebdbe00 [Evaluator] Improve evaluation of call instruction adds 243c2fa15c2 [SLPVectorizer][X86] Add some alternate tests for cast operators adds 2d07720488b Revert "[llvm-readobj] Fix printing format" adds e101271f213 [UnrollAndJam] New Unroll and Jam pass adds 4c7a6ba2a43 [SLPVectorizer] Use InstructionsState Op/Alt opcodes direct [...] adds 6fed3d80700 [PatternMatch] allow undef elements in vectors with m_Neg adds 77442a72e04 [InstCombine] add abs tests with undef elts; NFC adds 23d1e8ab600 [X86][Disassembler] Remove TYPE_BNDR from translateImmediate. adds b1dbeaa9ce7 [SLPVectorizer] Replace sameOpcodeOrAlt with InstructionsSt [...] adds a634a07771b [SLPVectorizer] Call InstructionsState.isOpcodeOrAlt with I [...] adds a7fba40f43e [X86] Remove the places that return nullptr from X86InstrIn [...] adds 260d013aef7 [X86] Fix a few test names in avx512-intrinsics-fast-isel.l [...] adds 49451db6ac0 Add an entry for rodata constant merge sections to the defa [...] adds c2f24d9ea87 Implement strip.invariant.group adds 38051ae89ad [PowerPC] Don't make it as pre-inc candidate if displacemen [...] adds ef235be85a9 [X86] Remove FMA3Info DenseMap. Break into sorted tables th [...] adds 33274bcdebb [llvm-exegesis][NFC] Cleanup useless braces. adds 25c9ed7633b [X86] Put some cases in switch statements back on one line [...] adds e52381764a9 [NFC] Test that shows unprofitability of instcombine with b [...] adds 529d7338b8c Reapply r334980 and r334983. adds 16f18201f6c [AArch64][SVE] Asm: Support for vector element compares (im [...] adds 783ea2aeedd [Mips][FastISel] Do not duplicate condition while lowering [...] adds f71bd1f42bb [X86][BtVer2] Added Jaguar FPU Pipe0/1 uop counters to perm [...] adds fe476f5b59e [AArch64][SVE] Asm: Support for (saturating) vector INC/DEC [...] adds 868f51c186b [AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector) adds a43dcd4394d [SLPVectorizer] Only Alternate opcodes use ShuffleVector ca [...] adds 386f15c93a2 [SLPVectorizer] Fix alternate opcode + shuffle cost functio [...] adds d9fdb860571 [InstCombine] add tests for shuffle-binop; NFC adds 2a87571b088 Recommit r328307: [IPSCCP] Use constant range information f [...] adds 3fc11a82d18 [llvm-exegesis] Delegate the decision of cycle counter name [...] adds 18de41c4564 [X86] Use addAliasForDirective to support the .word directive adds 736ca3f1beb [InstCombine] adjust shuffle tests with IR flags; NFC adds a40b37f909c [SLPVectorizer] Remove nullptr early-outs from Instruction: [...] adds f1f3f984f72 Revert r336100 adds eca25385a80 [X86] Use addAliasForDirective to support the .word directi [...] adds 752e14ccebb [llvm-exegesis] Change how the native architecture is determined adds bf14300d4c6 [X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104 adds f123cb818a1 [CodeGen] Make block removal order deterministic in CodeGenPrepare adds 6b77c4bc5ff Disable failing test on x86_64-pc-windows-gnu, see PR38006. adds cdbffdd9b54 [ValueTracking] allow undef elements when matching vector abs adds 3e5a75b28df [X86][SSE] Add v8i16 shift test for 2 shift values that doe [...] adds 273949e71bf [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values adds bf4ec2b466c [Dominators] Add the DomTreeUpdater class adds f56a57c59e9 Follow up of r335953 - [ARM][AArch64] Armv8.4-A Enablement adds 20c17e173fa [WebAssembly] Convert remaining tests from elf to wasm outp [...] adds 6e76b4eeb53 Revert "[Dominators] Add the DomTreeUpdater class" adds 636e853b421 [AArch64][GlobalISel] Any-extend vararg parameters to stack [...] adds e5e07035165 [X86] Don't use aligned load/store instructions for fp128 i [...] adds 15962f647bd [CostModel][X86] Add cost tests for fp rounding intrinsics adds eb37a3e6fa5 Tighten up a test for -check-debugify, NFC adds 198bcb65d99 [SLPVectorizer][X86] Begin adding alternate tests for call [...] adds 629c9d30eb3 nm: Add -no-weak flag for hiding weak symbols adds a5d70d8749b [MC] Error on a .zerofill directive in a non-virtual section adds c9a157f7fd5 [InstCombine] reverse canonicalization of add --> or to all [...] adds 13f7859c206 [SLP] Recognize min/max pattern using instructions producin [...] adds 4cc22bda677 Replace unused output filenames with /dev/null in tests adds 89e8753d7bf Replace "Replacable" with "Replaceable". [NFC] adds 1c305da5144 [X86] Add phony registers for high halves of regs with low halves adds df015f19fc7 [WebAssembly] Fix fast-isel optimization of branch conditions. adds 7276550b78a [SCEV] Strengthen StrengthenNoWrapFlags (reapply r334428). adds 8636bd77426 [llvm-mca] Clear the content of map VariantDescriptors in I [...] adds 2546414701c [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m. adds bb8c53976bc [WebAssembly] Support for atomic stores adds 807ab9588cf [ThinLTO] Fix printing of module paths for distributed back [...] adds d7b828144f2 [ORC] Verify modules when running LLLazyJIT in LLI, and dea [...] adds 1a01e8944b7 Remove absolute path in test adds d0f9eaced9b [ADT] Add llvm::unique_function which is like std::function [...] adds 22e1f605703 [demangler] Fix a MSVC alignment warning. adds 3369ac0dd8c Some buildbots were choking on std::max_align_t, try using [...] adds 3aca69ca829 [ThinLTO] Fix printing of aliases for distributed backend indexes adds 52b38c4e9f9 [Support] Fix llvm::unique_function when building with GCC [...] adds 7b549ea6b60 Revert r336159, r336157. Some bots failed on qualified std: [...] adds 57fa5c9397b Reappl "[Dominators] Add the DomTreeUpdater class" adds 4bf5c9984c2 [ADT] Switch another place to `llvm::is_trivially_move_cons [...] adds 2ef7a1ca8c0 [X86] Add avx512vl command line to break-false-dep.ll adds aabbcb39787 [ADT] Try to work around a crash in MSVC. adds c978388e74b [llvm-exegesis] ExegisX86Target::setRegToConstant() should [...] adds 6ac04e25a3a [InstCombine] Delay foldICmpUsingKnownBits until simple tra [...] adds 344a827483e [Support] This sanity check in the test only works with cer [...] adds a9de7e5e9c7 [DebugInfo] Fix PR37395. adds 939e4c5a9cf [ADT] Disable the single callback optimization on Windows. adds 099ee454a70 [AArch64][SVE] Asm: Support for vector element FP compare. adds ba89ffcade7 [PM/LoopUnswitch] Fix PR37651 by correctly invalidating SCE [...] adds c95c8c872bc [MIPS GlobalISel] Lower arguments using stack adds 3095ea4ec7e [AArch64][SVE] Asm: Support for saturing ADD/SUB instructions. adds a5c6980ab7a [llvm-exegesis] Add an AArch64 target adds ed0d4dabbee [llvm-exegesis] Adjust AArch64 unit test adds d5d94ca3a7f Revert "[X86][SSE] Blend any v8i16/v4i32 shift with 2 shift [...] adds 13e9d31258a [DebugInfo] Corrections for salvageDebugInfo adds cfc7aea7ef8 build_llvm_package.bat: Re-try the build steps adds 5af2ac74a54 [AArch64] Armv8.4-A: system registers adds a1ff84e2e4e [IR] Strip trailing whitespace. NFC adds 26122d06c8b [ARM][NFC] Refactor sequential access for DSP adds c810b4e17d7 [InstCombine] fold shuffle-with-binop and common value adds 6a79620306e [DAGCombiner] visitSDIV - Permit MIN_SIGNED_VALUE in pow2 v [...] adds 4962aeccc93 [AArch64][SVE] Asm: Support for predicated unary operations. adds c0606b67ed2 [AArch64][SVE] Asm: Support for FMUL (indexed) adds a9961f34ed2 Rename lazy initialization functions to reflect behavior (NFC) adds 85678535ba7 [Reassociate] add test for missing FP constant analysis; NFC adds ebcc0927e37 [AArch64][GlobalISel] Fix fallbacks introduced in r336120 d [...] adds a06d966cffd [AArch64][SVE] Asm: Support for FP Complex ADD/MLA. adds ed7df98414e [Reassociate] regenerate checks; NFC adds ef3144ea385 [Reassociate] add tests for binop with identity constant; NFC adds d841b7b37d2 [Constants] add identity constants for fadd/fmul adds f438ac9e92f Fix typo in lib/Support/Path.cpp to test commit access adds 773b6e54313 [X86][AsmParser] Don't consider %eip as a valid register ou [...] adds f4212f0917f [X86][AsmParser] Rework the in/out (%dx) hack one more time. adds a5edfbd7f9a [InstCombine] add tests for shuffle+binop with constant op1; NFC adds 92dfb6e3244 [AArch64] Make function parameter names in declarations mat [...] adds e1d12229c21 [ARM] Fix inconsistent declaration parameter name in r336195 adds cfa89ea7f98 [X86] Add tests for low/high bit clearing with different at [...] adds dee3b3b081b [X86] Remove repeated 'the' from multiple comments that hav [...] adds 4bbb8b7d1f4 [NVPTX] Expand v2f16 INSERT_VECTOR_ELT adds 7ead4232dac [X86][AsmParser] Fix inconsistent declaration parameter nam [...] adds bdd6a09688e [lanai] Handle atomic load of i8 like regular load. adds 1eef495cdcc [Support] Remove SaveOr which is no longer used adds 2dfeba53c3d [ImplicitNullChecks] Check for rewrite of register used in [...] adds 71ab3ef1d76 [AArch64][SVE] Asm: Support for SVE condition code aliases adds 19a6aea02d4 [X86][SSE] Add reduced crash test case for r336113 - [X86][ [...] adds c8da7b28b97 [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique [...] adds baf68707d00 [DebugInfo][InstCombine] Preserve DI after combining zext adds fb31c6481f7 [DebugInfo][LoopVectorize] Preserve DL in generated phi ins [...] adds c7d6f7ca768 [NFC] Add test that shows that InstCombine can do better adds 3b4c054b7b9 [AArch64][SVE] Asm: Support for FP conversion instructions. adds d657fe7634b [llvm-exegesis] Remove dead comment. adds c8d61cbaa4c [AArch64][SVE] Asm: Support for instructions to set/read FFR. adds 0aae9148178 NFC - Various typo fixes in tests adds 6c03d59fdb6 [X86][SSE] Add SSE2 target to some shift tests adds 5a15e424fb4 [AArch64][SVE] Asm: Support for reversed subtract (SUBR) in [...] adds 645f3d0f000 [ThinLTO] Update ThinLTO cache file atimes when on Windows adds 4b43817e2b4 [X86][SSE] Add v16i16 shl x,c -> pmullw test adds d069a21e54f [llvm-objdump] Add --file-headers (-f) option adds 195a60c5f5f [MachineOutliner] Fix typo in getOutliningCandidateInfo fun [...] adds 851b4035374 [ARM] [Assembler] Support negative immediates: cover few mi [...] adds 6e5842a1e11 [InstCombine] add value names to test; NFC adds 79d7b5cd915 Fix some irregular whitespace/indentation. NFCI. adds 23aed9c64ab [X86][BtVer2][MCA][NFC] Add CMPEQ dependency-breaking one-i [...] adds b8f75399383 [InstCombine] allow narrowing of min/max/abs adds 96a3f3e4cdb [Dominators] Add DomTreeUpdater constructor from DT* and PDT* adds 1631efd1b8c [PowerPC] Replace the Post RA List Scheduler with the Machi [...] adds d04690c89ba [mips] Warn when crc, ginv, virt flags are used with too ol [...] adds 2dc5cd2beb8 Silence an MSVC C4189 warning about a local variable being [...] adds 4fcda06d85c [Power9]Legalize and emit code for round & convert quad-pre [...] adds 3d92cb5cddb [X86] Remove some of the packed FMA3 intrinsics since we no [...] adds 585ca3a7f51 [X86] Add support for combining FMSUB/FNMADD/FNMSUB ISD nod [...] adds 12fed3cda6e [X86] Remove some isel patterns for X86ISD::SELECTS that sp [...] adds b42f206bec4 [Power9] Implement float128 parameter passing and return values adds 1ae65deb249 [Power9]Legalize and emit code for quad-precision convert f [...] adds ddc48fa71f7 [Power9] Ensure float128 in non-homogenous aggregates are p [...] adds c7bc4c373ce [demangler] Avoid alignment warning adds d50e092736e [Power9] Add tests for passing float128 in VSX reg for non- [...] adds e5da5ca56a2 [Power9][NFC] add back-end tests for passing homogeneous fp [...] adds 5f1cfe90f3e [X86] Remove X86 specific scalar FMA intrinsics and upgrade [...] adds bd76e146be4 [Power9] Optimize codgen for conversions of int to float128 adds 0e87e9463a9 [AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD adds 802e5e3d9a8 [ARM] ParallelDSP: only support i16 loads for now adds 45a7a31f486 [AArch64][SVE] Asm: Support for predicated FP rounding inst [...] adds 53a066525e5 Partial revert of "NFC - Various typo fixes in tests" adds 797624f8264 Reverting r336322 for now, as it causes an assert failure i [...] adds e816e742162 [NEON] Fix combining of vldx_dup intrinsics with updating o [...] adds f9df18f4ce3 [mips] Fix atomic operations at O0, v3 adds a7eead2e395 Try to fix -Wimplicit-fallthrough warning. NFCI. adds 5ad902a628b [X86][SSE] Add extra v16i16 shl x,c -> pmullw test adds c13d59697a3 [TableGen] Increase the number of supported decoder fix-ups. adds 816b1d58d7b Partially revert r336268 in address-offsets.ll adds c7654d92173 [ADT] Switch to indirect even the trivial case through an o [...] adds e941c764421 [AMDGPU] Add VALU to V_INTERP Instructions adds 363d86f9595 [llvm-exegesis][NFC]clang-format adds 7029d5a52f0 [SLPVectorizer] Begin abstracting InstructionsState alterna [...] adds b06fd494977 [AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC adds ef431bb8ee8 Fix comment typo. NFCI. adds 1b3251f9f41 [llvm-exegesis] Add uop computation for more X87 instructio [...] adds fd46678873a [llvm-objdump] Add --archive-headers (-a) option adds a86a3c2c457 [X86][SSE] Add srem x, (1 << c) combine tests adds 37aa5135e52 [Power9] Add lib calls for float128 operations with no equi [...] adds 78a28ad3b83 [llvm-objcopy] Fix timezone dependant tests adds 92712655cf6 [llvm-mca] Fix RegisterFile debug prints. NFC adds 5ccd8badb18 [llvm-objdump] Removed archive-headers-disas test adds a46b1e54f3f [CostModel][X86] Add UDIV/UREM by pow2 costs adds e5d3d151346 AMDGPU/GlobalISel: Implement custom kernel arg lowering adds 5ad067fad46 AMDGPU: Don't use spir_kernel in a test adds 30ba76520af Fix asserts in AMDGCN fmed3 folding by handling more cases of NaN adds 6e0b82fc61c [X86] Add SHUF128 to target shuffle decoding. adds c9994c8acfb [X86] Remove the last of the 'x86.fma.' intrinsics and auto [...] adds d4298974bd1 Testing commit permision adds 318e807d171 [ORC] In CompileOnDemandLayer2, clone modules on to differe [...] adds c0500faed50 This is a recommit of r336322, previously reverted in r3363 [...] adds 1a979dc8f20 [ORC] Add BitReader/BitWriter to target_link_libraries adds 95e1a0c65c2 [WebAssembly] Add missing _S opcodes of atomic stores to In [...] adds bda51c282f6 Revert r332168: "Reapply "[PR16756] Use SSAUpdaterBulk in J [...] adds 8c4cc472e7a objdump: Support newer ObjC image info flags adds 861969844e0 [X86][Disassembler] Fix LOCK prefix disassembler support adds 39c82afe637 [OpenEmbedded] Add OpenEmbedded vendor adds d20537eca5c Revert "objdump: Support newer ObjC image info flags" adds 04d15315b2a [x86]Add a test case to show missed vfnmadd generation. adds 1ba3969024d [PDB] Sort globals symbols by name in GSI hash buckets. adds 0b9754cd9ab [Power9] Add __float128 library call for frem adds 7f08d4abd84 [llvm-pdbutil] Dump more info about globals. adds e12c938bca7 [X86] Cleanup some of the avx512 masked fma tests to prepar [...] adds 89a40a3e5c2 [X86] Remove all of the avx512 masked packed fma intrinsics [...] adds ed10960040a Revert "[InstCombine] Delay foldICmpUsingKnownBits until si [...] adds 145133c3486 Reapply: "objdump: Support newer ObjC image info flags" adds a2b35082b00 [Support] Make support types more easily printable. adds a4e191b3237 [X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic [...] adds fc2b3d0ed07 [AArch64][ARM] Armv8.4-A: Trace synchronization barrier ins [...] adds 2d76367f823 CallGraphSCCPass: iterate over all functions. adds 9e7cb445ca5 [llvm-mca] improve the instruction issue logic implemented [...] adds 6b3f49c77fb [AArch64] Armv8.4-A: Flag manipulation instructions adds 681dbd52d12 Revert [AArch64] Armv8.4-A: Flag manipulation instructions adds eaaa4f4cfc8 [SelectionDAG] https://reviews.llvm.org/D48278 adds 4ebe5514a93 Added missing semicolon adds d1a03350b87 Recommit: [AArch64] Armv8.4-A: Flag manipulation instructions adds 55b2eb047f3 [dsymutil] Emit label at the begin of a CU new 11143ead429 Fix PR34170: Crash on inline asm with 64bit output in 32bit GPR new b1366b5c435 Fix crash on inline asm with 64bit matching input in 32bit GPR new 5389807c6ae Support inline asm with multiple 64bit output in 32bit GPR new d6228f957a6 TOCLEAN: adds variable expression This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d731a63e1ae) \ N -- N -- N refs/heads/linaro-local/thomas.preudhomme/tcwg-1428-reba [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: CMakeLists.txt | 3 + cmake/modules/AddLLVM.cmake | 14 +- cmake/modules/LLVMExternalProjectUtils.cmake | 13 +- cmake/platforms/iOS.cmake | 27 + docs/AMDGPUUsage.rst | 316 +- docs/CommandGuide/FileCheck.rst | 19 + docs/CommandGuide/llvm-nm.rst | 4 + docs/CommandGuide/tblgen.rst | 8 +- docs/GettingStarted.rst | 12 +- docs/LangRef.rst | 48 +- docs/TableGen/BackEnds.rst | 16 + include/llvm-c/Transforms/Scalar.h | 3 + include/llvm/ADT/APInt.h | 17 +- include/llvm/ADT/FunctionExtras.h | 293 + include/llvm/ADT/SCCIterator.h | 24 +- include/llvm/ADT/SmallVector.h | 5 +- include/llvm/ADT/Triple.h | 19 +- include/llvm/ADT/iterator.h | 4 +- include/llvm/ADT/iterator_range.h | 7 +- include/llvm/Analysis/DependenceAnalysis.h | 5 + include/llvm/Analysis/MemorySSA.h | 41 + include/llvm/Analysis/MemorySSAUpdater.h | 9 + include/llvm/Analysis/PhiValues.h | 143 + include/llvm/Analysis/ScalarEvolution.h | 4 + include/llvm/Analysis/TargetTransformInfo.h | 7 + include/llvm/Analysis/ValueLattice.h | 2 + include/llvm/AsmParser/Parser.h | 76 +- include/llvm/BinaryFormat/DynamicTags.def | 12 + include/llvm/BinaryFormat/ELF.h | 12 + include/llvm/CodeGen/GlobalISel/IRTranslator.h | 2 +- include/llvm/CodeGen/GlobalISel/LegalizerInfo.h | 19 +- include/llvm/CodeGen/LiveIntervals.h | 4 + include/llvm/CodeGen/MachineDominanceFrontier.h | 4 +- include/llvm/CodeGen/MachineFrameInfo.h | 3 + include/llvm/CodeGen/MachineOutliner.h | 24 + include/llvm/CodeGen/Passes.h | 2 +- include/llvm/CodeGen/SelectionDAGNodes.h | 12 +- include/llvm/CodeGen/TargetInstrInfo.h | 10 +- include/llvm/CodeGen/TargetLowering.h | 8 +- include/llvm/DebugInfo/DWARF/DWARFVerifier.h | 2 +- include/llvm/DebugInfo/MSF/MSFBuilder.h | 7 +- include/llvm/DebugInfo/PDB/Native/PDBFileBuilder.h | 2 +- .../ExecutionEngine/Orc/CompileOnDemandLayer.h | 7 - include/llvm/ExecutionEngine/Orc/CompileUtils.h | 44 +- include/llvm/ExecutionEngine/Orc/Core.h | 85 +- include/llvm/ExecutionEngine/Orc/ExecutionUtils.h | 115 +- .../llvm/ExecutionEngine/Orc/IRTransformLayer.h | 13 +- include/llvm/ExecutionEngine/Orc/LLJIT.h | 153 + include/llvm/ExecutionEngine/Orc/Layer.h | 13 - include/llvm/IR/BasicBlock.h | 2 +- include/llvm/IR/CMakeLists.txt | 3 +- include/llvm/IR/DomTreeUpdater.h | 251 + include/llvm/IR/IRBuilder.h | 29 + include/llvm/IR/Instruction.h | 2 +- include/llvm/IR/Instructions.h | 20 +- include/llvm/IR/Intrinsics.h | 2 +- include/llvm/IR/Intrinsics.td | 5 + include/llvm/IR/IntrinsicsAMDGPU.td | 225 +- include/llvm/IR/IntrinsicsARM.td | 14 + include/llvm/IR/IntrinsicsX86.td | 535 +- include/llvm/IR/ModuleSummaryIndex.h | 39 +- include/llvm/IR/PatternMatch.h | 114 +- include/llvm/InitializePasses.h | 4 +- include/llvm/LinkAllPasses.h | 4 +- include/llvm/MC/MCAsmInfo.h | 6 + include/llvm/MC/MCDwarf.h | 3 + include/llvm/MC/MCELFStreamer.h | 3 +- include/llvm/MC/MCObjectFileInfo.h | 5 +- include/llvm/MC/MCStreamer.h | 3 +- include/llvm/MC/MCWasmStreamer.h | 3 +- include/llvm/MC/MCWinCOFFStreamer.h | 2 +- include/llvm/Object/COFF.h | 1 + include/llvm/Object/ELF.h | 15 + include/llvm/Object/ELFObjectFile.h | 11 +- include/llvm/Object/ELFTypes.h | 2 + include/llvm/Object/IRObjectFile.h | 11 + include/llvm/Object/ObjectFile.h | 3 + include/llvm/Support/AArch64TargetParser.def | 9 + include/llvm/Support/AMDHSAKernelDescriptor.h | 21 +- include/llvm/Support/ARMTargetParser.def | 7 + include/llvm/Support/BinaryByteStream.h | 12 + include/llvm/Support/Compiler.h | 45 + include/llvm/Support/Error.h | 8 + include/llvm/Support/FileOutputBuffer.h | 16 +- include/llvm/Support/FileSystem.h | 9 + include/llvm/Support/FormatVariadic.h | 11 +- include/llvm/Support/FormatVariadicDetails.h | 50 +- include/llvm/Support/KnownBits.h | 2 +- include/llvm/Support/MathExtras.h | 16 +- include/llvm/Support/PointerLikeTypeTraits.h | 34 + include/llvm/Support/SaveAndRestore.h | 12 - include/llvm/Support/TargetOpcodes.def | 5 +- include/llvm/Support/TargetParser.h | 8 +- include/llvm/Support/TaskQueue.h | 139 + include/llvm/Support/type_traits.h | 39 + include/llvm/TableGen/Record.h | 16 - include/llvm/TableGen/SearchableTable.td | 131 +- include/llvm/Target/GenericOpcodes.td | 5 + include/llvm/Target/TargetMachine.h | 6 + include/llvm/Target/TargetOptions.h | 14 +- include/llvm/Transforms/IPO/Inliner.h | 5 + include/llvm/Transforms/Scalar.h | 6 + include/llvm/Transforms/Scalar/InstSimplifyPass.h | 46 + .../llvm/Transforms/Scalar/LoopUnrollAndJamPass.h | 35 + include/llvm/Transforms/Scalar/SCCP.h | 6 +- .../llvm/Transforms/Scalar/SimpleLoopUnswitch.h | 31 +- include/llvm/Transforms/Utils.h | 7 - include/llvm/Transforms/Utils/Evaluator.h | 13 + include/llvm/Transforms/Utils/Local.h | 5 + .../llvm/Transforms/Utils/SimplifyInstructions.h | 31 - include/llvm/Transforms/Utils/UnrollLoop.h | 41 + include/llvm/module.modulemap | 2 + lib/Analysis/AliasSetTracker.cpp | 8 +- lib/Analysis/Analysis.cpp | 1 + lib/Analysis/BasicAliasAnalysis.cpp | 16 +- lib/Analysis/CMakeLists.txt | 1 + lib/Analysis/CallGraphSCCPass.cpp | 110 +- lib/Analysis/ConstantFolding.cpp | 9 +- lib/Analysis/DependenceAnalysis.cpp | 23 +- lib/Analysis/InstructionSimplify.cpp | 17 +- lib/Analysis/LoopPass.cpp | 11 +- lib/Analysis/MemorySSA.cpp | 59 +- lib/Analysis/MemorySSAUpdater.cpp | 33 + lib/Analysis/ModuleSummaryAnalysis.cpp | 16 +- lib/Analysis/PhiValues.cpp | 196 + lib/Analysis/ScalarEvolution.cpp | 84 +- lib/Analysis/ScalarEvolutionExpander.cpp | 5 +- lib/Analysis/TargetLibraryInfo.cpp | 3 +- lib/Analysis/ValueTracking.cpp | 80 +- lib/AsmParser/LLLexer.cpp | 77 +- lib/AsmParser/LLLexer.h | 7 + lib/AsmParser/LLParser.cpp | 1260 +++- lib/AsmParser/LLParser.h | 65 +- lib/AsmParser/LLToken.h | 68 + lib/AsmParser/Parser.cpp | 83 +- lib/Bitcode/Reader/BitcodeReader.cpp | 31 +- lib/Bitcode/Writer/BitcodeWriter.cpp | 8 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 3 +- lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 10 +- lib/CodeGen/AsmPrinter/DwarfDebug.h | 8 +- lib/CodeGen/BranchFolding.cpp | 3 +- lib/CodeGen/CodeGenPrepare.cpp | 9 +- lib/CodeGen/GlobalISel/LegalityPredicates.cpp | 15 +- lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 3 +- lib/CodeGen/ImplicitNullChecks.cpp | 28 +- lib/CodeGen/InlineSpiller.cpp | 26 - lib/CodeGen/LiveIntervals.cpp | 59 +- lib/CodeGen/LiveRangeCalc.cpp | 21 + lib/CodeGen/LiveRangeCalc.h | 9 + lib/CodeGen/LiveRegUnits.cpp | 4 +- lib/CodeGen/MachineOutliner.cpp | 39 +- lib/CodeGen/MachineSink.cpp | 61 +- lib/CodeGen/RegisterCoalescer.cpp | 154 +- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 268 +- lib/CodeGen/SelectionDAG/FastISel.cpp | 1 + lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 21 +- lib/CodeGen/StackSlotColoring.cpp | 72 +- lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 23 +- lib/CodeGen/TargetPassConfig.cpp | 23 +- lib/DebugInfo/CodeView/RecordName.cpp | 2 + lib/DebugInfo/DWARF/DWARFVerifier.cpp | 2 +- lib/DebugInfo/MSF/MSFBuilder.cpp | 78 +- lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp | 24 +- lib/DebugInfo/PDB/Native/PDBFileBuilder.cpp | 86 +- lib/DebugInfo/Symbolize/Symbolize.cpp | 5 + lib/Demangle/ItaniumDemangle.cpp | 10 +- lib/ExecutionEngine/Orc/CMakeLists.txt | 7 + lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp | 202 +- lib/ExecutionEngine/Orc/Core.cpp | 160 +- lib/ExecutionEngine/Orc/ExecutionUtils.cpp | 152 +- lib/ExecutionEngine/Orc/IndirectionUtils.cpp | 2 - lib/ExecutionEngine/Orc/LLJIT.cpp | 171 + lib/ExecutionEngine/Orc/LLVMBuild.txt | 4 +- lib/ExecutionEngine/Orc/Layer.cpp | 18 +- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 43 + lib/IR/AsmWriter.cpp | 90 +- lib/IR/AutoUpgrade.cpp | 487 +- lib/IR/BasicBlock.cpp | 2 +- lib/IR/CMakeLists.txt | 1 + lib/IR/ConstantFold.cpp | 9 +- lib/IR/ConstantRange.cpp | 72 +- lib/IR/Constants.cpp | 39 +- lib/IR/DebugInfo.cpp | 4 +- lib/IR/DebugInfoMetadata.cpp | 5 +- lib/IR/DomTreeUpdater.cpp | 512 ++ lib/IR/Function.cpp | 14 +- lib/IR/IRBuilder.cpp | 26 +- lib/IR/Instructions.cpp | 16 + lib/IR/IntrinsicInst.cpp | 5 +- lib/IR/LLVMContextImpl.cpp | 8 + lib/IR/LegacyPassManager.cpp | 2 +- lib/IR/SafepointIRVerifier.cpp | 217 +- lib/IR/Type.cpp | 24 +- lib/IR/Value.cpp | 3 +- lib/LTO/Caching.cpp | 31 +- lib/LTO/ThinLTOCodeGenerator.cpp | 19 +- lib/MC/MCAsmInfoCOFF.cpp | 11 +- lib/MC/MCAsmStreamer.cpp | 13 +- lib/MC/MCContext.cpp | 8 +- lib/MC/MCELFStreamer.cpp | 3 +- lib/MC/MCMachOStreamer.cpp | 18 +- lib/MC/MCNullStreamer.cpp | 3 +- lib/MC/MCObjectFileInfo.cpp | 24 +- lib/MC/MCParser/AsmParser.cpp | 8 +- lib/MC/MCParser/DarwinAsmParser.cpp | 10 +- lib/MC/MCParser/ELFAsmParser.cpp | 52 +- lib/MC/MCStreamer.cpp | 21 +- lib/MC/MCWasmStreamer.cpp | 3 +- lib/MC/MCWinCOFFStreamer.cpp | 3 +- lib/Object/COFFObjectFile.cpp | 6 + lib/Object/ELF.cpp | 127 + lib/Object/RecordStreamer.cpp | 3 +- lib/Object/RecordStreamer.h | 2 +- lib/Object/WasmObjectFile.cpp | 2 +- lib/ObjectYAML/ELFYAML.cpp | 2 + lib/Passes/PassBuilder.cpp | 19 +- lib/Passes/PassRegistry.def | 5 +- lib/Support/APInt.cpp | 48 + lib/Support/FileOutputBuffer.cpp | 37 +- lib/Support/Path.cpp | 45 +- lib/Support/SmallVector.cpp | 4 + lib/Support/TargetParser.cpp | 5 + lib/Support/Triple.cpp | 4 + lib/Support/Unix/Threading.inc | 8 +- lib/Support/Windows/Path.inc | 15 + lib/TableGen/Error.cpp | 9 +- lib/TableGen/Record.cpp | 25 - lib/TableGen/TGParser.cpp | 316 +- lib/TableGen/TGParser.h | 62 +- lib/Target/AArch64/AArch64.td | 29 +- lib/Target/AArch64/AArch64CallLowering.cpp | 6 + lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 30 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 66 + lib/Target/AArch64/AArch64ISelLowering.h | 2 + lib/Target/AArch64/AArch64InstrFormats.td | 73 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 67 +- lib/Target/AArch64/AArch64InstrInfo.h | 7 +- lib/Target/AArch64/AArch64InstrInfo.td | 68 +- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 8 +- lib/Target/AArch64/AArch64RegisterInfo.cpp | 13 + lib/Target/AArch64/AArch64RegisterInfo.h | 4 + lib/Target/AArch64/AArch64RegisterInfo.td | 44 +- lib/Target/AArch64/AArch64SVEInstrInfo.td | 200 +- lib/Target/AArch64/AArch64Subtarget.h | 14 + lib/Target/AArch64/AArch64SystemOperands.td | 141 +- lib/Target/AArch64/AArch64TargetMachine.cpp | 7 +- lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 73 +- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 200 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 34 +- .../AArch64/InstPrinter/AArch64InstPrinter.cpp | 17 + .../AArch64/InstPrinter/AArch64InstPrinter.h | 2 + lib/Target/AArch64/SVEInstrFormats.td | 577 ++ lib/Target/AArch64/Utils/AArch64BaseInfo.cpp | 8 + lib/Target/AArch64/Utils/AArch64BaseInfo.h | 8 + lib/Target/AMDGPU/AMDGPU.h | 4 + lib/Target/AMDGPU/AMDGPU.td | 156 +- lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp | 3 - lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 3 - lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 115 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 7 - lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 48 +- lib/Target/AMDGPU/AMDGPUCallLowering.h | 5 +- lib/Target/AMDGPU/AMDGPUCallingConv.td | 32 +- lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 323 +- lib/Target/AMDGPU/AMDGPUFeatures.td | 60 + lib/Target/AMDGPU/AMDGPUGISel.td | 38 + lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 108 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 175 +- lib/Target/AMDGPU/AMDGPUISelLowering.h | 95 +- lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 104 +- lib/Target/AMDGPU/AMDGPUInstrInfo.h | 33 +- lib/Target/AMDGPU/AMDGPUInstrInfo.td | 2 + lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 62 +- lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 8 + lib/Target/AMDGPU/AMDGPUInstructions.td | 91 +- lib/Target/AMDGPU/AMDGPUIntrinsicInfo.cpp | 6 +- lib/Target/AMDGPU/AMDGPUIntrinsicInfo.h | 2 +- lib/Target/AMDGPU/AMDGPUIntrinsics.td | 2 - lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 18 +- lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp | 3 +- lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp | 265 + lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | 3 +- lib/Target/AMDGPU/AMDGPUMachineFunction.h | 26 +- lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 17 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 7 +- lib/Target/AMDGPU/AMDGPURegisterInfo.td | 1 - lib/Target/AMDGPU/AMDGPUSearchableTables.td | 58 +- lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 149 +- lib/Target/AMDGPU/AMDGPUSubtarget.h | 629 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 12 + lib/Target/AMDGPU/AMDGPUTargetMachine.h | 14 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 2 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 18 +- lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 92 +- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 512 +- lib/Target/AMDGPU/BUFInstructions.td | 8 +- lib/Target/AMDGPU/CMakeLists.txt | 15 +- lib/Target/AMDGPU/DSInstructions.td | 21 + .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 27 +- lib/Target/AMDGPU/EvergreenInstructions.td | 7 +- .../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 100 +- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h | 13 +- .../MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp | 28 +- .../MCTargetDesc/AMDGPUHSAMetadataStreamer.h | 1 + .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 25 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 16 + .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 154 +- .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h | 25 +- lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt | 1 + .../AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 35 +- .../AMDGPU/MCTargetDesc/R600MCTargetDesc.cpp | 27 + lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 3 + lib/Target/AMDGPU/MIMGInstructions.td | 1421 ++-- lib/Target/AMDGPU/R600.td | 59 + lib/Target/AMDGPU/R600AsmPrinter.cpp | 2 +- lib/Target/AMDGPU/R600ClauseMergePass.cpp | 26 +- lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp | 106 +- lib/Target/AMDGPU/R600EmitClauseMarkers.cpp | 48 +- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 55 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 345 +- lib/Target/AMDGPU/R600ISelLowering.h | 3 + lib/Target/AMDGPU/R600InstrFormats.td | 2 +- lib/Target/AMDGPU/R600InstrInfo.cpp | 429 +- lib/Target/AMDGPU/R600InstrInfo.h | 9 +- lib/Target/AMDGPU/R600Instructions.td | 93 +- lib/Target/AMDGPU/R600MachineScheduler.cpp | 62 +- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 14 +- lib/Target/AMDGPU/R600Packetizer.cpp | 45 +- lib/Target/AMDGPU/R600Processors.td | 56 + lib/Target/AMDGPU/R600RegisterInfo.cpp | 58 +- lib/Target/AMDGPU/R600RegisterInfo.h | 7 +- lib/Target/AMDGPU/R600RegisterInfo.td | 2 +- lib/Target/AMDGPU/R700Instructions.td | 2 +- lib/Target/AMDGPU/SIDefines.h | 4 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 4 +- lib/Target/AMDGPU/SIISelLowering.cpp | 704 +- lib/Target/AMDGPU/SIISelLowering.h | 6 + lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 14 +- lib/Target/AMDGPU/SIInstrFormats.td | 23 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 105 +- lib/Target/AMDGPU/SIInstrInfo.h | 24 +- lib/Target/AMDGPU/SIInstrInfo.td | 218 +- lib/Target/AMDGPU/SIInstructions.td | 29 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 3 - lib/Target/AMDGPU/SIMachineFunctionInfo.h | 15 - lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 - lib/Target/AMDGPU/SIRegisterInfo.h | 1 + lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 169 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 67 +- lib/Target/AMDGPU/VOP1Instructions.td | 2 +- lib/Target/ARM/ARM.h | 5 + lib/Target/ARM/ARM.td | 42 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 18 + lib/Target/ARM/ARMExpandPseudoInsts.cpp | 89 +- lib/Target/ARM/ARMFrameLowering.cpp | 6 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 204 +- lib/Target/ARM/ARMISelLowering.cpp | 22 +- lib/Target/ARM/ARMInstrInfo.td | 22 + lib/Target/ARM/ARMInstrNEON.td | 23 +- lib/Target/ARM/ARMInstrThumb2.td | 24 + lib/Target/ARM/ARMParallelDSP.cpp | 619 ++ lib/Target/ARM/ARMSubtarget.h | 18 + lib/Target/ARM/ARMTargetMachine.cpp | 8 +- lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 + lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 251 +- lib/Target/ARM/CMakeLists.txt | 1 + lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 7 +- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 11 + lib/Target/ARM/InstPrinter/ARMInstPrinter.h | 2 + lib/Target/ARM/LLVMBuild.txt | 2 +- lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h | 14 + lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 2 + lib/Target/Hexagon/Hexagon.td | 4 + lib/Target/Hexagon/HexagonDepIICScalar.td | 680 -- lib/Target/Hexagon/HexagonSubtarget.cpp | 1 + .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 1 + .../Hexagon/TargetInfo/HexagonTargetInfo.cpp | 2 +- lib/Target/Lanai/LanaiInstrInfo.td | 4 + lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 6 +- lib/Target/Mips/CMakeLists.txt | 1 + lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 2 +- lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp | 14 +- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 2 +- lib/Target/Mips/Mips.h | 1 + lib/Target/Mips/Mips16FrameLowering.cpp | 8 +- lib/Target/Mips/Mips64InstrInfo.td | 11 + lib/Target/Mips/MipsCallLowering.cpp | 94 +- lib/Target/Mips/MipsCallLowering.h | 12 +- lib/Target/Mips/MipsExpandPseudo.cpp | 702 ++ lib/Target/Mips/MipsFastISel.cpp | 5 +- lib/Target/Mips/MipsFrameLowering.h | 4 + lib/Target/Mips/MipsISelLowering.cpp | 607 +- lib/Target/Mips/MipsISelLowering.h | 12 +- lib/Target/Mips/MipsInstrInfo.td | 54 + lib/Target/Mips/MipsSEFrameLowering.cpp | 10 +- lib/Target/Mips/MipsSubtarget.cpp | 35 +- lib/Target/Mips/MipsSubtarget.h | 9 + lib/Target/Mips/MipsTargetMachine.cpp | 9 + lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 6 - lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 3 - lib/Target/NVPTX/NVPTXISelLowering.cpp | 1 + lib/Target/NVPTX/NVPTXInstrInfo.cpp | 45 - lib/Target/NVPTX/NVPTXInstrInfo.h | 8 - lib/Target/NVPTX/NVPTXSubtarget.h | 1 - lib/Target/PowerPC/P9InstrResources.td | 3 +- lib/Target/PowerPC/PPCCallingConv.td | 19 +- lib/Target/PowerPC/PPCISelLowering.cpp | 60 +- lib/Target/PowerPC/PPCISelLowering.h | 4 + lib/Target/PowerPC/PPCInstrInfo.td | 9 +- lib/Target/PowerPC/PPCInstrVSX.td | 59 +- lib/Target/PowerPC/PPCLoopPreIncPrep.cpp | 13 + lib/Target/PowerPC/PPCTargetMachine.cpp | 8 +- lib/Target/RISCV/CMakeLists.txt | 1 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 8 +- lib/Target/RISCV/RISCV.h | 4 + lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 208 - lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 286 + lib/Target/RISCV/RISCVTargetMachine.cpp | 5 + lib/Target/WebAssembly/CMakeLists.txt | 3 +- .../MCTargetDesc/WebAssemblyMCTargetDesc.h | 14 + lib/Target/WebAssembly/WebAssembly.h | 5 +- .../WebAssembly/WebAssemblyExceptionInfo.cpp | 197 + lib/Target/WebAssembly/WebAssemblyExceptionInfo.h | 170 + .../WebAssembly/WebAssemblyExceptionPrepare.cpp | 88 - lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 2 +- lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 9 +- lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 14 +- lib/Target/WebAssembly/WebAssemblyISelLowering.h | 3 + lib/Target/WebAssembly/WebAssemblyInstrAtomics.td | 140 +- .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 383 + .../WebAssemblyOptimizeLiveIntervals.cpp | 2 +- .../WebAssembly/WebAssemblySetP2AlignOperands.cpp | 7 + .../WebAssembly/WebAssemblyTargetMachine.cpp | 5 +- lib/Target/X86/AsmParser/X86AsmParser.cpp | 191 +- lib/Target/X86/AsmParser/X86Operand.h | 11 +- lib/Target/X86/CMakeLists.txt | 1 + lib/Target/X86/Disassembler/X86Disassembler.cpp | 33 +- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 3 + .../X86/Disassembler/X86DisassemblerDecoder.h | 2 + lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 2 +- lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 4 +- lib/Target/X86/X86EvexToVex.cpp | 7 +- lib/Target/X86/X86FrameLowering.cpp | 6 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 43 + lib/Target/X86/X86ISelLowering.cpp | 661 +- lib/Target/X86/X86ISelLowering.h | 12 +- lib/Target/X86/X86InstrAVX512.td | 75 +- lib/Target/X86/X86InstrCompiler.td | 175 +- lib/Target/X86/X86InstrFMA.td | 89 +- lib/Target/X86/X86InstrFMA3Info.cpp | 353 +- lib/Target/X86/X86InstrFMA3Info.h | 133 +- lib/Target/X86/X86InstrFoldTables.cpp | 5410 +++++++++++++ lib/Target/X86/X86InstrFoldTables.h | 85 + lib/Target/X86/X86InstrFragmentsSIMD.td | 12 +- lib/Target/X86/X86InstrInfo.cpp | 5783 +------------- lib/Target/X86/X86InstrInfo.h | 62 +- lib/Target/X86/X86InstrInfo.td | 9 + lib/Target/X86/X86InstrSSE.td | 14 +- lib/Target/X86/X86InstrShiftRotate.td | 58 +- lib/Target/X86/X86IntrinsicsInfo.h | 209 +- lib/Target/X86/X86MCInstLower.cpp | 752 +- lib/Target/X86/X86PfmCounters.td | 2 + lib/Target/X86/X86RegisterInfo.cpp | 7 +- lib/Target/X86/X86RegisterInfo.td | 104 +- lib/Target/X86/X86SchedSkylakeServer.td | 8 +- lib/Target/X86/X86TargetMachine.cpp | 8 +- lib/Target/X86/X86TargetTransformInfo.cpp | 44 +- lib/Transforms/IPO/FunctionImport.cpp | 23 +- lib/Transforms/IPO/Inliner.cpp | 18 + lib/Transforms/IPO/PassManagerBuilder.cpp | 20 +- lib/Transforms/IPO/SCCP.cpp | 24 +- lib/Transforms/IPO/SampleProfile.cpp | 8 + lib/Transforms/InstCombine/CMakeLists.txt | 4 + lib/Transforms/InstCombine/InstCombineAddSub.cpp | 35 +- lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 21 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 39 +- lib/Transforms/InstCombine/InstCombineCasts.cpp | 75 +- lib/Transforms/InstCombine/InstCombineInternal.h | 21 + .../InstCombine/InstCombineMulDivRem.cpp | 130 +- lib/Transforms/InstCombine/InstCombineShifts.cpp | 22 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 241 +- lib/Transforms/InstCombine/InstCombineTables.td | 11 + .../InstCombine/InstCombineVectorOps.cpp | 192 + .../InstCombine/InstructionCombining.cpp | 20 +- .../Instrumentation/AddressSanitizer.cpp | 47 +- .../Instrumentation/DataFlowSanitizer.cpp | 3 +- .../Instrumentation/EfficiencySanitizer.cpp | 2 +- .../Instrumentation/HWAddressSanitizer.cpp | 10 + lib/Transforms/Instrumentation/MemorySanitizer.cpp | 3 +- .../Instrumentation/SanitizerCoverage.cpp | 1 - lib/Transforms/Scalar/CMakeLists.txt | 2 + lib/Transforms/Scalar/InstSimplifyPass.cpp | 144 + lib/Transforms/Scalar/JumpThreading.cpp | 46 +- lib/Transforms/Scalar/LICM.cpp | 54 +- lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 11 +- lib/Transforms/Scalar/LoopRerollPass.cpp | 236 +- lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp | 447 ++ lib/Transforms/Scalar/LoopUnrollPass.cpp | 28 +- lib/Transforms/Scalar/LoopUnswitch.cpp | 5 +- lib/Transforms/Scalar/SCCP.cpp | 328 +- lib/Transforms/Scalar/SROA.cpp | 2 + lib/Transforms/Scalar/Scalar.cpp | 6 + lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 458 +- lib/Transforms/Utils/CMakeLists.txt | 2 +- lib/Transforms/Utils/Evaluator.cpp | 69 +- lib/Transforms/Utils/Local.cpp | 69 +- lib/Transforms/Utils/LoopUnroll.cpp | 22 +- lib/Transforms/Utils/LoopUnrollAndJam.cpp | 774 ++ lib/Transforms/Utils/SimplifyCFG.cpp | 2 +- lib/Transforms/Utils/SimplifyIndVar.cpp | 4 + lib/Transforms/Utils/SimplifyInstructions.cpp | 152 - lib/Transforms/Utils/Utils.cpp | 1 - lib/Transforms/Utils/VNCoercion.cpp | 8 +- lib/Transforms/Vectorize/LoopVectorize.cpp | 2 + lib/Transforms/Vectorize/SLPVectorizer.cpp | 343 +- runtimes/CMakeLists.txt | 87 +- test/Analysis/CostModel/AArch64/shuffle-select.ll | 12 +- test/Analysis/CostModel/AArch64/store.ll | 2 +- test/Analysis/CostModel/X86/div.ll | 361 +- test/Analysis/CostModel/X86/fround.ll | 519 ++ test/Analysis/CostModel/X86/rem.ll | 234 +- test/Analysis/Delinearization/a.ll | 2 +- .../iv_times_constant_in_subscript.ll | 2 +- test/Analysis/DependenceAnalysis/DADelin.ll | 36 +- .../AMDGPU/llvm.amdgcn.image.atomic.ll | 78 +- test/Analysis/IVUsers/quadradic-exit-value.ll | 2 +- .../LoopAccessAnalysis/number-of-memchecks.ll | 4 +- .../wrapping-pointer-versioning.ll | 16 +- test/Analysis/PhiValues/basic.ll | 282 + test/Analysis/PhiValues/big_phi.ll | 78 + test/Analysis/PhiValues/long_phi_chain.ll | 142 + .../ScalarEvolution/different-loops-recs.ll | 2 +- .../extract-highbits-sameconstmask.ll | 8 +- .../ScalarEvolution/lshr-shl-differentconstmask.ll | 10 +- .../ScalarEvolution/merge-add-rec-many-inputs.ll | 127 + test/Analysis/ScalarEvolution/nsw-offset-assume.ll | 2 +- test/Analysis/ScalarEvolution/nsw-offset.ll | 2 +- test/Analysis/ScalarEvolution/nsw.ll | 4 +- .../ScalarEvolution/predicated-trip-count.ll | 2 +- test/Analysis/ScalarEvolution/sext-mul.ll | 4 +- .../ScalarEvolution/shl-lshr-differentconstmask.ll | 2 +- test/Analysis/ScalarEvolution/trip-count-pow2.ll | 2 +- test/Analysis/ScalarEvolution/zext-divrem.ll | 42 + test/Analysis/ScalarEvolution/zext-mul.ll | 16 +- test/Analysis/ValueTracking/invariant.group.ll | 21 +- test/Assembler/ConstantExprNoFold.ll | 11 + test/Assembler/return-column.s | 2 +- test/Assembler/thinlto-bad-summary1.ll | 4 +- test/Assembler/thinlto-bad-summary2.ll | 2 +- test/Assembler/thinlto-bad-summary3.ll | 2 +- test/Assembler/thinlto-summary.ll | 96 + test/Bitcode/thinlto-alias.ll | 6 +- ...o-function-summary-callgraph-profile-summary.ll | 12 +- .../thinlto-function-summary-callgraph-relbf.ll | 5 +- test/Bitcode/thinlto-function-summary-refgraph.ll | 4 +- test/Bitcode/thinlto-type-tests.ll | 6 +- test/Bitcode/thinlto-type-vcalls.ll | 6 +- .../CodeGen/AArch64/FoldRedundantShiftedMasking.ll | 95 + .../AArch64/GlobalISel/arm64-callingconv-ios.ll | 9 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 12 + .../AArch64/GlobalISel/irtranslator-exceptions.ll | 3 +- .../GlobalISel/legalizer-info-validation.mir | 24 +- test/CodeGen/AArch64/aarch64_tree_tests.ll | 2 + test/CodeGen/AArch64/andandshift.ll | 4 +- test/CodeGen/AArch64/arm64-addr-mode-folding.ll | 2 +- test/CodeGen/AArch64/arm64-addr-type-promotion.ll | 1 - test/CodeGen/AArch64/arm64-cse.ll | 2 +- test/CodeGen/AArch64/arm64-csel.ll | 1 + test/CodeGen/AArch64/cmpwithshort.ll | 6 +- test/CodeGen/AArch64/copy-zero-reg.ll | 47 - test/CodeGen/AArch64/fast-isel-gep.ll | 2 +- test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll | 67 +- test/CodeGen/AArch64/ftrunc.ll | 10 +- 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tools/llvm-exegesis/lib/X86.h delete mode 100644 tools/llvm-mca/Backend.cpp delete mode 100644 tools/llvm-mca/Backend.h delete mode 100644 tools/llvm-mca/BackendPrinter.cpp delete mode 100644 tools/llvm-mca/BackendPrinter.h create mode 100644 tools/llvm-mca/Pipeline.cpp create mode 100644 tools/llvm-mca/Pipeline.h create mode 100644 tools/llvm-mca/PipelinePrinter.cpp create mode 100644 tools/llvm-mca/PipelinePrinter.h create mode 100644 unittests/ADT/FunctionExtrasTest.cpp create mode 100644 unittests/Analysis/PhiValuesTest.cpp create mode 100644 unittests/IR/DomTreeUpdaterTest.cpp create mode 100644 unittests/Support/TaskQueueTest.cpp create mode 100644 unittests/Support/TypeTraitsTest.cpp create mode 100644 unittests/Target/WebAssembly/CMakeLists.txt create mode 100644 unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp create mode 100644 unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt create mode 100644 unittests/tools/llvm-exegesis/AArch64/TargetTest.cpp -- To stop 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[lld] branch master updated (487f25359 -> 29f781276)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 55b2eb047f3 [dsymutil] Emit label at the begin of a CU new 023b04f4507 [AArch64] Armv8.4-A: TLB support The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/AArch64/AArch64SystemOperands.td | 54 ++++++ lib/Target/AArch64/Utils/AArch64BaseInfo.h | 2 + test/MC/AArch64/armv8.4a-tlb.s | 263 ++++++++++++++++++++++++++ test/MC/Disassembler/AArch64/armv8.4a-tlb.txt | 151 +++++++++++++++ 4 files changed, 470 insertions(+) create mode 100644 test/MC/AArch64/armv8.4a-tlb.s create mode 100644 test/MC/Disassembler/AArch64/armv8.4a-tlb.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 8cffd3e3df4 P0935R0 Eradicating unnecessarily explicit default constructors new 669d54f7dd1 Simplify linker script patterns for std::exception_ptr The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libstdc++-v3/ChangeLog | 2 ++ libstdc++-v3/config/abi/pre/gnu.ver | 12 ++++-------- 2 files changed, 6 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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