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from 618f11e436b [RISCV] Lower the tail pseudoinstruction
new 3fd1c161ec4 Move a debug info test into the X86 directory
new c1e740501d9 [GlobalISel][InstructionSelect] Maximizing # of Group's com [...]
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Summary of changes:
test/DebugInfo/{ => X86}/sink-bitcast-di.ll | 5 ++---
test/TableGen/GlobalISelEmitter.td | 28 ++++++++++++++++------------
utils/TableGen/GlobalISelEmitter.cpp | 16 +++++++++++++---
3 files changed, 31 insertions(+), 18 deletions(-)
rename test/DebugInfo/{ => X86}/sink-bitcast-di.ll (77%)
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from 673840e6846 [GlobalISel][Tablegen] Assign small opcodes to pseudos
new 618f11e436b [RISCV] Lower the tail pseudoinstruction
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Summary of changes:
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 14 +-
lib/Target/RISCV/RISCVISelLowering.cpp | 125 +++++++++++++++--
lib/Target/RISCV/RISCVISelLowering.h | 7 +-
lib/Target/RISCV/RISCVInstrInfo.cpp | 1 +
lib/Target/RISCV/RISCVInstrInfo.td | 14 +-
lib/Target/RISCV/RISCVRegisterInfo.td | 13 ++
test/CodeGen/RISCV/disable-tail-calls.ll | 56 ++++++++
test/CodeGen/RISCV/musttail-call.ll | 20 +++
test/CodeGen/RISCV/tail-calls.ll | 148 +++++++++++++++++++++
9 files changed, 381 insertions(+), 17 deletions(-)
create mode 100644 test/CodeGen/RISCV/disable-tail-calls.ll
create mode 100644 test/CodeGen/RISCV/musttail-call.ll
create mode 100644 test/CodeGen/RISCV/tail-calls.ll
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unknown user pushed a change to branch master
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from d5e64ad16 [libFuzzer] change the output format for the DataFlow tracer
new 12c36256d [fuchsia] Add line buffering in RawWrite
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lib/sanitizer_common/sanitizer_fuchsia.cc | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
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unknown user pushed a change to branch master
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from 4e24f46cfd2 [DebugInfo] Maintain DI for sunken bitcasts
new 673840e6846 [GlobalISel][Tablegen] Assign small opcodes to pseudos
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utils/TableGen/CodeGenSchedule.cpp | 22 ++++++++++++++--------
utils/TableGen/CodeGenTarget.cpp | 19 ++++++++++++-------
utils/TableGen/CodeGenTarget.h | 12 ++++++++++++
3 files changed, 38 insertions(+), 15 deletions(-)
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from 1352bbd3ec2 [RISCV] Set CostPerUse for registers
new 4e24f46cfd2 [DebugInfo] Maintain DI for sunken bitcasts
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lib/CodeGen/CodeGenPrepare.cpp | 1 +
test/DebugInfo/sink-bitcast-di.ll | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 test/DebugInfo/sink-bitcast-di.ll
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unknown user pushed a change to branch master
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from efc838422 Fix PathMappingList tests on windows
new 439860210 Remove spurious dependency on Process/elf-core from Process/Utility.
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source/Plugins/Process/Utility/CMakeLists.txt | 1 -
source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp | 7 +------
source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp | 7 +------
source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp | 9 ++-------
source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.cpp | 7 +------
source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.cpp | 6 +-----
unittests/Symbol/CMakeLists.txt | 1 +
7 files changed, 7 insertions(+), 31 deletions(-)
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from cb64cbca1c4 [GlobalISel] NFCI, Getting GlobalISel ~5% faster
new 38a4af251f3 [LKH] Add a new IRCompileLayer.
new 499fe95f132 [LKH] Add ObjectTransformLayer2.
new 1d560c20ffb [LKH] Add a new IRTransformLayer.
new 60b28ca5a7e [RuntimeDyld][MachO] Add support for MachO::ARM64_RELOC_POI [...]
new 5f477b2b135 [GlobalISel][InstructionSelect] Sorting MatchTable's 2nd le [...]
new 1352bbd3ec2 [RISCV] Set CostPerUse for registers
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Summary of changes:
include/llvm/ExecutionEngine/Orc/IRCompileLayer.h | 26 ++++++++-
.../llvm/ExecutionEngine/Orc/IRTransformLayer.h | 20 ++++++-
.../ExecutionEngine/Orc/ObjectTransformLayer.h | 19 ++++++-
lib/ExecutionEngine/Orc/CMakeLists.txt | 3 +
lib/ExecutionEngine/Orc/IRCompileLayer.cpp | 44 +++++++++++++++
lib/ExecutionEngine/Orc/IRTransformLayer.cpp | 34 ++++++++++++
lib/ExecutionEngine/Orc/ObjectTransformLayer.cpp | 34 ++++++++++++
.../Orc/RTDyldObjectLinkingLayer.cpp | 2 +-
.../RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h | 56 ++++++++++++++++---
lib/Target/RISCV/RISCVRegisterInfo.td | 11 ++++
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 64 +++++++++++-----------
test/CodeGen/RISCV/calling-conv.ll | 24 ++++----
test/CodeGen/RISCV/double-mem.ll | 8 +--
test/CodeGen/RISCV/remat.ll | 18 +++---
.../RuntimeDyld/AArch64/MachO_ARM64_relocations.s | 12 +++-
utils/TableGen/GlobalISelEmitter.cpp | 32 +++++++++++
16 files changed, 337 insertions(+), 70 deletions(-)
create mode 100644 lib/ExecutionEngine/Orc/IRCompileLayer.cpp
create mode 100644 lib/ExecutionEngine/Orc/IRTransformLayer.cpp
create mode 100644 lib/ExecutionEngine/Orc/ObjectTransformLayer.cpp
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unknown user pushed a change to branch master
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from 54f3f9c02f [X86] Move the include of clzerointrin.h from immintrin.h ba [...]
new 02f3a0b412 Rework __builtin_classify_type support to better match GCC a [...]
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lib/AST/ExprConstant.cpp | 176 ++++++++++++++++++---------------
test/Sema/builtin-classify-type.c | 19 +++-
test/SemaCXX/builtin-classify-type.cpp | 25 ++++-
3 files changed, 134 insertions(+), 86 deletions(-)
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from c349f814879 [Tablegen] Tidying up InstRegexOp a little, NFC
new cb64cbca1c4 [GlobalISel] NFCI, Getting GlobalISel ~5% faster
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include/llvm/CodeGen/MachineRegisterInfo.h | 22 +++++++++------------
lib/CodeGen/GlobalISel/InstructionSelect.cpp | 29 ++++++++++++++--------------
lib/CodeGen/MachineRegisterInfo.cpp | 14 ++++----------
lib/CodeGen/ResetMachineFunctionPass.cpp | 2 +-
4 files changed, 29 insertions(+), 38 deletions(-)
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from 7eb6f679d1 [X86] Move all Intel defined intrinsic includes into immintrin.h
new 611c44748f [modules] Mark __wmmintrin_pclmul.h/__wmmintrin_aes.h as textual
new 54f3f9c02f [X86] Move the include of clzerointrin.h from immintrin.h ba [...]
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Summary of changes:
lib/Headers/immintrin.h | 4 ----
lib/Headers/module.modulemap | 11 +++--------
lib/Headers/x86intrin.h | 5 +++++
3 files changed, 8 insertions(+), 12 deletions(-)
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