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from 77d8d0a7e72 Pass Divergence Analysis data to Selection DAG to drive div [...]
new efff70ac28a TableGen: Introduce an abstract variable resolver interface
new d5cc0e077d6 TableGen: Reimplement !foreach using the resolving mechanism
new 73eed0f1afd TableGen: Resolve all template args simultaneously in AddSubClass
new 83f929b89a9 TableGen: Resolve all template args simultaneously in AddSu [...]
new 1e9feb80869 TableGen: Resolve all template args simultaneously in Resol [...]
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Summary of changes:
docs/TableGen/LangIntro.rst | 6 +-
include/llvm/TableGen/Record.h | 131 +++++++++++++--
lib/TableGen/Record.cpp | 280 +++++++++++++++++--------------
lib/TableGen/TGParser.cpp | 196 ++++++++++++++++------
test/TableGen/MultiPat.td | 20 +--
test/TableGen/TargetInstrSpec.td | 20 +--
test/TableGen/foreach-eval.td | 28 +---
test/TableGen/foreach-leak.td | 25 +++
test/TableGen/foreach.td | 26 +--
test/TableGen/template-arg-dependency.td | 16 ++
10 files changed, 497 insertions(+), 251 deletions(-)
create mode 100644 test/TableGen/foreach-leak.td
create mode 100644 test/TableGen/template-arg-dependency.td
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from 9355e1b3893 [Power9] Add more missing instructions to the Power 9 scheduler
new 77d8d0a7e72 Pass Divergence Analysis data to Selection DAG to drive div [...]
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Summary of changes:
include/llvm/Analysis/DivergenceAnalysis.h | 4 +
include/llvm/CodeGen/FunctionLoweringInfo.h | 11 +++
include/llvm/CodeGen/SelectionDAG.h | 33 ++++---
include/llvm/CodeGen/SelectionDAGNodes.h | 6 +-
include/llvm/CodeGen/TargetLowering.h | 11 +++
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 10 ++
lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 101 ++++++++++++++++++++-
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 2 +
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 27 +++++-
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +
lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 96 ++++++++++++++++++++
lib/Target/AMDGPU/AMDGPUISelLowering.h | 3 +
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 53 +----------
lib/Target/AMDGPU/SIISelLowering.cpp | 4 +-
lib/Target/AMDGPU/SMInstructions.td | 7 +-
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 51 +++++++++++
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 3 +
test/CodeGen/AMDGPU/callee-special-input-sgprs.ll | 50 +++++++---
test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll | 25 ++++-
19 files changed, 405 insertions(+), 94 deletions(-)
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unknown user pushed a change to branch master
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from b63b27b8ab7 [AArch64] PR84114: Avoid reassociating FMA
new 1822aaae3b4 2018-03-05 Richard Biener <rguenther(a)suse.de>
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Summary of changes:
gcc/ChangeLog | 7 +++++++
gcc/tree-ssa-pre.c | 25 +++++++++++++++++--------
2 files changed, 24 insertions(+), 8 deletions(-)
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from f3b54ef25c0 TableGen: Allow NAME in template arguments in defm in multiclass
new 9355e1b3893 [Power9] Add more missing instructions to the Power 9 scheduler
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lib/Target/PowerPC/P9InstrResources.td | 185 ++++++++++++++++++++++++++-------
lib/Target/PowerPC/PPCScheduleP9.td | 3 +
2 files changed, 150 insertions(+), 38 deletions(-)
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unknown user pushed a change to branch gcc-7-branch
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from d9a2ed009c9 Daily bump.
new ca9cb78a24a PR c++/84686 - missing volatile loads.
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gcc/cp/ChangeLog | 5 +++++
gcc/cp/cvt.c | 2 ++
gcc/testsuite/g++.dg/tree-ssa/volatile2.C | 20 ++++++++++++++++++++
3 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/tree-ssa/volatile2.C
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unknown user pushed a change to branch gcc-6-branch
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from 9c487c20585 Daily bump.
new ba229150f5c PR c++/84686 - missing volatile loads.
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gcc/cp/ChangeLog | 5 +++++
gcc/cp/cvt.c | 2 ++
gcc/testsuite/g++.dg/tree-ssa/volatile2.C | 20 ++++++++++++++++++++
3 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/g++.dg/tree-ssa/volatile2.C
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unknown user pushed a change to branch master
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from 984c8beef Cygwin: remove outdated comment
new 00e870783 Cygwin: accept4: Fix resource leak
new be6da7971 Cygwin: AF_UNIX: create pipes with file attribute R/W access
new df14d97ff Cygwin: AF_UNIX: drop try/except block in bind method
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winsup/cygwin/fhandler_socket_inet.cc | 2 ++
winsup/cygwin/fhandler_socket_local.cc | 2 ++
winsup/cygwin/fhandler_socket_unix.cc | 57 +++++++++++++++++-----------------
3 files changed, 32 insertions(+), 29 deletions(-)
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from ec1d1788ce5 [MergeICmp] We can discard initial blocks that do other work
new 8cb107dbb81 TableGen: Use DefInit::getDef() instead of the type's getRecord()
new f3b54ef25c0 TableGen: Allow NAME in template arguments in defm in multiclass
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Summary of changes:
lib/TableGen/TGParser.cpp | 3 ++
test/TableGen/MultiClass-defm-fail.td | 32 ++++++++++++++++++++
test/TableGen/MultiClass-defm.td | 50 +++++++++++++++++++++++++++++++
utils/TableGen/FixedLenDecoderEmitter.cpp | 25 +++++++---------
4 files changed, 96 insertions(+), 14 deletions(-)
create mode 100644 test/TableGen/MultiClass-defm-fail.td
create mode 100644 test/TableGen/MultiClass-defm.td
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from 3da0d341b24 2018-03-05 Richard Biener <rguenther(a)suse.de>
new fcae3eb4f84 [PR c++/84497] ref to undefined tls init
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gcc/cp/ChangeLog | 7 +++++++
gcc/cp/decl2.c | 3 ++-
gcc/testsuite/ChangeLog | 6 ++++++
gcc/testsuite/g++.dg/cpp0x/pr84497.C | 37 ++++++++++++++++++++++++++++++++++++
4 files changed, 52 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/g++.dg/cpp0x/pr84497.C
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