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unknown user pushed a change to branch gcc-7-branch
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from 7aeeadbd184 gcc/ Backport from mainline 2018-02-22 Vladimir Makarov [...]
new cdb6f782d01 2018-03-06 Steven G. Kargl <kargl(a)gcc.gnu.org>
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Summary of changes:
gcc/fortran/ChangeLog | 6 ++++++
gcc/fortran/primary.c | 18 ++++++++++++++++--
gcc/testsuite/ChangeLog | 6 ++++++
gcc/testsuite/gfortran.dg/coarray_8.f90 | 4 ++--
gcc/testsuite/gfortran.dg/implied_do_2.f90 | 7 +++++++
5 files changed, 37 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/implied_do_2.f90
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from 952ac72e5c5 * gcc-interface/trans.c (convert_with_check): Fix typo in [...]
new 3fdcd18ae74 2018-03-06 Steven G. Kargl <kargl(a)gcc.gnu.org>
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Summary of changes:
gcc/fortran/ChangeLog | 6 ++++++
gcc/fortran/primary.c | 18 ++++++++++++++++--
gcc/testsuite/ChangeLog | 6 ++++++
gcc/testsuite/gfortran.dg/coarray_8.f90 | 4 ++--
gcc/testsuite/gfortran.dg/implied_do_2.f90 | 7 +++++++
5 files changed, 37 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/implied_do_2.f90
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unknown user pushed a change to branch master
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from 7ea78b5973 btrace: Remove ui_out cleanups
new d74aff3d95 gdb/riscv: Remove use of pseudo registers
new c9486dfe27 gdb/riscv: Remove 'Contributed by....' comments
new 9add17f218 gdb/riscv: Remove partial target description support
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gdb/ChangeLog | 18 +++++++++++++++
gdb/riscv-tdep.c | 67 --------------------------------------------------------
gdb/riscv-tdep.h | 5 -----
3 files changed, 18 insertions(+), 72 deletions(-)
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unknown user pushed a change to branch master
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from c72b5190294 * gcc-interface/trans.c (convert_with_check): Fix typo in [...]
new 97891b71597 2018-03-06 Steven G. Kargl <kargl(a)gcc.gnu.org>
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gcc/fortran/ChangeLog | 6 ++++++
gcc/fortran/primary.c | 18 ++++++++++++++++--
gcc/testsuite/ChangeLog | 6 ++++++
gcc/testsuite/gfortran.dg/coarray_8.f90 | 4 ++--
gcc/testsuite/gfortran.dg/implied_do_2.f90 | 7 +++++++
5 files changed, 37 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/implied_do_2.f90
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unknown user pushed a change to branch master
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from 6a7d6881f0a [X86] Reject registers that require a REX prefix in inline [...]
new a05c22c9e81 [InstCombine] simplify min/max canonicalization; NFCI
new 195a164675a [Hexagon] Remove {{ *}} from testcases
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lib/Transforms/InstCombine/InstCombineSelect.cpp | 15 +-
test/CodeGen/Hexagon/absaddr-store.ll | 8 +-
test/CodeGen/Hexagon/absimm.ll | 4 +-
test/CodeGen/Hexagon/addr-calc-opt.ll | 2 +-
test/CodeGen/Hexagon/always-ext.ll | 2 +-
test/CodeGen/Hexagon/bit-loop.ll | 3 +-
test/CodeGen/Hexagon/builtin-prefetch-offset.ll | 4 +-
test/CodeGen/Hexagon/cext-check.ll | 16 +-
test/CodeGen/Hexagon/cext-valid-packet2.ll | 4 +-
test/CodeGen/Hexagon/cext.ll | 2 +-
test/CodeGen/Hexagon/cexti16.ll | 2 +-
test/CodeGen/Hexagon/cmp-to-genreg.ll | 8 +-
test/CodeGen/Hexagon/cmp-to-predreg.ll | 8 +-
test/CodeGen/Hexagon/gp-plus-offset-load.ll | 6 +-
test/CodeGen/Hexagon/gp-plus-offset-store.ll | 4 +-
test/CodeGen/Hexagon/gp-rel.ll | 6 +-
test/CodeGen/Hexagon/idxload-with-zero-offset.ll | 12 +-
test/CodeGen/Hexagon/memops.ll | 252 +++++++++++------------
test/CodeGen/Hexagon/memops1.ll | 4 +-
test/CodeGen/Hexagon/memops2.ll | 4 +-
test/CodeGen/Hexagon/memops3.ll | 4 +-
test/CodeGen/Hexagon/multi-cycle.ll | 6 +-
test/CodeGen/Hexagon/pic-jumptables.ll | 6 +-
test/CodeGen/Hexagon/pic-regusage.ll | 6 +-
test/CodeGen/Hexagon/postinc-load.ll | 2 +-
test/CodeGen/Hexagon/postinc-offset.ll | 4 +-
test/CodeGen/Hexagon/postinc-store.ll | 2 +-
test/CodeGen/Hexagon/pred-gp.ll | 4 +-
test/CodeGen/Hexagon/pred-instrs.ll | 4 +-
test/CodeGen/Hexagon/vec-pred-spill1.ll | 2 +-
test/CodeGen/Hexagon/vect/vect-truncate.ll | 4 +-
31 files changed, 202 insertions(+), 208 deletions(-)
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unknown user pushed a change to branch master
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from 5f97f24294 TableGen: Give up on exact fixits for diagnostic groups
new 860fc25e85 [OPENMP] Fix generation of the unique names for task reducti [...]
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lib/CodeGen/CGOpenMPRuntime.cpp | 43 +++++++++++++++---------
lib/CodeGen/CGOpenMPRuntime.h | 2 ++
test/OpenMP/taskgroup_task_reduction_codegen.cpp | 4 ++-
3 files changed, 32 insertions(+), 17 deletions(-)
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unknown user pushed a change to branch master
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from 0dc2b94c4e9 [AMDGPU] Add default ISA version targets
new 6a7d6881f0a [X86] Reject registers that require a REX prefix in inline [...]
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lib/Target/X86/X86ISelLowering.cpp | 10 ++++++++++
test/CodeGen/X86/asm-reject-rex.ll | 21 +++++++++++++++++++++
test/CodeGen/X86/asm-reject-xmm16.ll | 4 ++--
3 files changed, 33 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/X86/asm-reject-rex.ll
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unknown user pushed a change to branch master
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from 9ac1b3521a5 [CodeView] Emit UdtSourceLine information for enums
new 0dc2b94c4e9 [AMDGPU] Add default ISA version targets
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lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 6 ++++++
test/MC/AMDGPU/hsa_isa_version_attrs.s | 6 ++++++
2 files changed, 12 insertions(+)
create mode 100644 test/MC/AMDGPU/hsa_isa_version_attrs.s
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unknown user pushed a change to branch master
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from da57ded77c9 Refactor check for dllimport in the Verifier.
new c63c5c660f4 [PatternMatch] define m_Not using m_Xor and cst_pred_ty
new 9ac1b3521a5 [CodeView] Emit UdtSourceLine information for enums
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Summary of changes:
include/llvm/IR/PatternMatch.h | 32 +++++++------------------
lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 40 +++++++++++++++++++++----------
lib/CodeGen/AsmPrinter/CodeViewDebug.h | 2 ++
test/DebugInfo/COFF/enum.ll | 11 +++++++++
test/DebugInfo/COFF/nested-types.ll | 2 +-
test/Transforms/InstCombine/sub.ll | 5 +---
test/Transforms/InstCombine/vector-xor.ll | 16 +++++--------
7 files changed, 56 insertions(+), 52 deletions(-)
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