Tcwg-commits March 2018

tcwg-commits@lists.linaro.org

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3018 discussions

[lld] branch master updated (6c9fbd5a4 -> f78a80695)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 6c9fbd5a4 Make lld-link shout at me less. new f78a80695 [ELF] - Removed excessive lookup. NFC. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/ScriptParser.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[llvm] branch master updated (7f9dbc4419d -> c9946711cef)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 7f9dbc4419d AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|E [...] new c9946711cef [Hexagon] Add more lit tests The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll | 57 ++ test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll | 61 ++ test/CodeGen/Hexagon/M4_mpyri_addi_global.ll | 19 + test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll | 22 + test/CodeGen/Hexagon/P08214.ll | 224 +++++ test/CodeGen/Hexagon/V60-VDblNew.ll | 28 + test/CodeGen/Hexagon/add-use.ll | 27 + test/CodeGen/Hexagon/add_int_double.ll | 11 + test/CodeGen/Hexagon/add_mpi_RRR.ll | 29 + test/CodeGen/Hexagon/addasl-address.ll | 33 + test/CodeGen/Hexagon/addrmode-keepdeadphis.ll | 50 + test/CodeGen/Hexagon/addrmode-offset.ll | 66 ++ test/CodeGen/Hexagon/addrmode.ll | 107 ++ test/CodeGen/Hexagon/aggr-antidep-tied.ll | 55 ++ test/CodeGen/Hexagon/aggr-copy-order.ll | 32 + test/CodeGen/Hexagon/aggr-licm.ll | 226 +++++ test/CodeGen/Hexagon/aggressive_licm.ll | 68 ++ test/CodeGen/Hexagon/align_Os.ll | 19 + test/CodeGen/Hexagon/align_test.ll | 72 ++ test/CodeGen/Hexagon/asr-rnd.ll | 33 + test/CodeGen/Hexagon/asr-rnd64.ll | 30 + .../Hexagon/assert-postinc-ptr-not-value.ll | 256 +++++ test/CodeGen/Hexagon/avoidVectorLowering.ll | 19 + test/CodeGen/Hexagon/base-offset-stv4.ll | 31 + test/CodeGen/Hexagon/bkfir.ll | 104 ++ test/CodeGen/Hexagon/block-address.ll | 36 + test/CodeGen/Hexagon/blockaddr-fpic.ll | 157 +++ test/CodeGen/Hexagon/brcond-setne.ll | 85 ++ test/CodeGen/Hexagon/bss-local.ll | 24 + test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll | 42 + test/CodeGen/Hexagon/bug-allocframe-size.ll | 116 +++ test/CodeGen/Hexagon/bug-hcp-tied-kill.ll | 55 ++ test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll | 231 +++++ .../Hexagon/bug14859-split-const-block-addr.ll | 363 +++++++ test/CodeGen/Hexagon/bug15515-shuffle.ll | 45 + test/CodeGen/Hexagon/bug17276.ll | 104 ++ test/CodeGen/Hexagon/bug17386.ll | 89 ++ test/CodeGen/Hexagon/bug18008.ll | 94 ++ test/CodeGen/Hexagon/bug18491-optsize.ll | 37 + test/CodeGen/Hexagon/bug19076.ll | 226 +++++ test/CodeGen/Hexagon/bug19119.ll | 49 + test/CodeGen/Hexagon/bug19254-ifconv-vec.ll | 152 +++ test/CodeGen/Hexagon/bug27085.ll | 44 + test/CodeGen/Hexagon/bug31839.ll | 26 + test/CodeGen/Hexagon/bug6757-endloop.ll | 107 ++ test/CodeGen/Hexagon/bug9049.ll | 20 + test/CodeGen/Hexagon/bug9963.ll | 15 + test/CodeGen/Hexagon/call-long1.ll | 24 + test/CodeGen/Hexagon/call-v4.ll | 34 + test/CodeGen/Hexagon/callR_noreturn.ll | 22 + test/CodeGen/Hexagon/calling-conv.ll | 37 + test/CodeGen/Hexagon/cext-ice.ll | 300 ++++++ .../Hexagon/cfi-late-and-regpressure-init.ll | 62 ++ test/CodeGen/Hexagon/cfi_offset.ll | 78 ++ test/CodeGen/Hexagon/cfi_offset2.ll | 117 +++ test/CodeGen/Hexagon/check-dot-new.ll | 16 + test/CodeGen/Hexagon/circ_pcr_assert.ll | 35 + test/CodeGen/Hexagon/cmpb_gtu.ll | 123 +++ test/CodeGen/Hexagon/cmpbeq.ll | 27 + test/CodeGen/Hexagon/cmpy-round.ll | 47 + test/CodeGen/Hexagon/coalesce_tfri.ll | 124 +++ test/CodeGen/Hexagon/combine-imm-ext.ll | 16 + test/CodeGen/Hexagon/combine-imm-ext2.ll | 16 + test/CodeGen/Hexagon/combine_lh.ll | 14 + test/CodeGen/Hexagon/combiner-lts.ll | 66 ++ test/CodeGen/Hexagon/common-global-addr.ll | 17 + test/CodeGen/Hexagon/concat-vectors-legalize.ll | 828 ++++++++++++++++ test/CodeGen/Hexagon/const-combine.ll | 48 + test/CodeGen/Hexagon/constext-call.ll | 59 ++ test/CodeGen/Hexagon/constext-immstore.ll | 162 +++ test/CodeGen/Hexagon/constext-replace.ll | 151 +++ test/CodeGen/Hexagon/count_0s.ll | 52 + test/CodeGen/Hexagon/csr-stubs-spill-threshold.ll | 51 + .../Hexagon/csr_stub_calls_dwarf_frame_info.ll | 20 + test/CodeGen/Hexagon/dag-combine-select-or0.ll | 29 + test/CodeGen/Hexagon/dag-indexed.ll | 47 + test/CodeGen/Hexagon/dccleana.ll | 17 + test/CodeGen/Hexagon/dealloc-store.ll | 65 ++ test/CodeGen/Hexagon/dealloc_return.ll | 27 + test/CodeGen/Hexagon/debug-line_table_start.ll | 32 + test/CodeGen/Hexagon/debug-prologue-loc.ll | 71 ++ test/CodeGen/Hexagon/debug-prologue.ll | 74 ++ test/CodeGen/Hexagon/def-undef-deps.ll | 73 ++ test/CodeGen/Hexagon/default-align.ll | 53 + test/CodeGen/Hexagon/deflate.ll | 32 + test/CodeGen/Hexagon/dhry.ll | 39 + test/CodeGen/Hexagon/dhry_proc8.ll | 53 + test/CodeGen/Hexagon/dhry_stall.ll | 48 + test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll | 68 ++ test/CodeGen/Hexagon/dwarf-discriminator.ll | 54 + test/CodeGen/Hexagon/eh_return-r30.ll | 17 + test/CodeGen/Hexagon/eh_save_restore.ll | 96 ++ test/CodeGen/Hexagon/ehabi.ll | 81 ++ test/CodeGen/Hexagon/entryBB-isLoopHdr.ll | 40 + test/CodeGen/Hexagon/expand-condsets-copy-lis.ll | 37 + test/CodeGen/Hexagon/expand-condsets-dead.ll | 47 + .../CodeGen/Hexagon/expand-condsets-pred-undef2.ll | 14 + test/CodeGen/Hexagon/expand-condsets.ll | 116 +++ test/CodeGen/Hexagon/extlow.ll | 12 + test/CodeGen/Hexagon/extract_0bits.ll | 15 + test/CodeGen/Hexagon/extractu_0bits.ll | 15 + test/CodeGen/Hexagon/find-loop.ll | 64 ++ test/CodeGen/Hexagon/float-bitcast.ll | 41 + test/CodeGen/Hexagon/float-const64-G0.ll | 14 + test/CodeGen/Hexagon/float-gen-cmpop.ll | 72 ++ test/CodeGen/Hexagon/fltnvjump.ll | 216 ++++ test/CodeGen/Hexagon/fmadd.ll | 20 + test/CodeGen/Hexagon/getBlockAddress.ll | 19 + test/CodeGen/Hexagon/glob-align-volatile.ll | 23 + test/CodeGen/Hexagon/global-const-gep.ll | 17 + test/CodeGen/Hexagon/global-ctor-pcrel.ll | 51 + test/CodeGen/Hexagon/global64bitbug.ll | 9 + test/CodeGen/Hexagon/hello-world-v55.ll | 16 + test/CodeGen/Hexagon/hello-world-v60.ll | 16 + test/CodeGen/Hexagon/hexagon-tfr-add.ll | 175 ++++ .../CodeGen/Hexagon/hexagon-verify-implicit-use.ll | 46 + test/CodeGen/Hexagon/hexagon_cfi_offset.ll | 131 +++ test/CodeGen/Hexagon/hidden-relocation.ll | 24 + test/CodeGen/Hexagon/honor-optsize.ll | 43 + test/CodeGen/Hexagon/hrc-stack-coloring.ll | 741 ++++++++++++++ test/CodeGen/Hexagon/hvx-byte-store-double.ll | 57 ++ test/CodeGen/Hexagon/hvx-byte-store.ll | 57 ++ test/CodeGen/Hexagon/hvx-dbl-dual-output.ll | 34 + test/CodeGen/Hexagon/hvx-double-vzero.ll | 33 + test/CodeGen/Hexagon/hvx-dual-output.ll | 34 + test/CodeGen/Hexagon/hvx-loopidiom-memcpy.ll | 30 + test/CodeGen/Hexagon/hvx-vzero.ll | 34 + test/CodeGen/Hexagon/hwloop-ice.ll | 20 + test/CodeGen/Hexagon/hwloop-long.ll | 70 ++ test/CodeGen/Hexagon/hwloop-phi-subreg.ll | 67 ++ test/CodeGen/Hexagon/hwloop-swap.ll | 28 + test/CodeGen/Hexagon/hwloop-with-return-call.ll | 26 + test/CodeGen/Hexagon/hx_V6_lo_hi.ll | 65 ++ test/CodeGen/Hexagon/i128-bitop.ll | 103 ++ test/CodeGen/Hexagon/ignore-terminal-mbb.ll | 33 + test/CodeGen/Hexagon/initial-exec.ll | 15 + test/CodeGen/Hexagon/inline-asm-clobber-lr.ll | 19 + test/CodeGen/Hexagon/inline-asm-error.ll | 15 + test/CodeGen/Hexagon/insert.ll | 61 ++ test/CodeGen/Hexagon/integer_abs.ll | 14 + test/CodeGen/Hexagon/intrinsics-v60-alu.ll | 1034 ++++++++++++++++++++ test/CodeGen/Hexagon/intrinsics-v60-misc.ll | 587 +++++++++++ test/CodeGen/Hexagon/intrinsics-v60-permute.ll | 167 ++++ test/CodeGen/Hexagon/intrinsics-v60-shift.ll | 56 ++ test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll | 330 +++++++ .../Hexagon/intrinsics-v60-vmpy-acc-128B.ll | 432 ++++++++ test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc.ll | 447 +++++++++ test/CodeGen/Hexagon/intrinsics-v60-vmpy.ll | 517 ++++++++++ test/CodeGen/Hexagon/invalid-memrefs.ll | 103 ++ test/CodeGen/Hexagon/jump-table-g0.ll | 45 + test/CodeGen/Hexagon/jump-table-isel.ll | 97 ++ test/CodeGen/Hexagon/large-number-of-preds.ll | 245 +++++ test/CodeGen/Hexagon/lcomm.ll | 15 + test/CodeGen/Hexagon/load-abs.ll | 135 +++ test/CodeGen/Hexagon/local-exec.ll | 23 + test/CodeGen/Hexagon/loop-rotate-bug.ll | 79 ++ test/CodeGen/Hexagon/loop-rotate-liveins.ll | 98 ++ test/CodeGen/Hexagon/loop_correctness.ll | 123 +++ test/CodeGen/Hexagon/lower-i1.ll | 13 + test/CodeGen/Hexagon/machine-sink.ll | 76 ++ test/CodeGen/Hexagon/maddsubu.ll | 27 + test/CodeGen/Hexagon/mapped_intrinsics.ll | 113 +++ test/CodeGen/Hexagon/mem-load-circ.ll | 111 +++ test/CodeGen/Hexagon/mem-ops-sub.ll | 44 + test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll | 44 + test/CodeGen/Hexagon/memcmp.ll | 48 + test/CodeGen/Hexagon/memcpy-memmove-inline.ll | 50 + test/CodeGen/Hexagon/memop-bit18.ll | 20 + test/CodeGen/Hexagon/memops_global.ll | 810 +++++++++++++++ test/CodeGen/Hexagon/memset-inline.ll | 27 + test/CodeGen/Hexagon/mipi-double-small.ll | 27 + test/CodeGen/Hexagon/mpysin-imm.ll | 18 + test/CodeGen/Hexagon/mul64.ll | 292 ++++++ test/CodeGen/Hexagon/muxii-crash.ll | 21 + test/CodeGen/Hexagon/neg-op.ll | 14 + test/CodeGen/Hexagon/newvaluejump-postinc.ll | 111 +++ test/CodeGen/Hexagon/newvaluestore2.ll | 23 + .../CodeGen/Hexagon/no-falign-function-for-size.ll | 11 + test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll | 31 + test/CodeGen/Hexagon/no_struct_element.ll | 36 + test/CodeGen/Hexagon/noreturn-noepilog.ll | 32 + test/CodeGen/Hexagon/noreturn-notail.ll | 33 + test/CodeGen/Hexagon/not-op.ll | 13 + test/CodeGen/Hexagon/ntstbit.ll | 32 + test/CodeGen/Hexagon/nv_store_vec.ll | 21 + test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll | 196 ++++ test/CodeGen/Hexagon/opt-glob-addrs-000.ll | 180 ++++ test/CodeGen/Hexagon/opt-glob-addrs-001.ll | 194 ++++ test/CodeGen/Hexagon/opt-glob-addrs-003.ll | 496 ++++++++++ test/CodeGen/Hexagon/opt-sext-intrinsics.ll | 28 + test/CodeGen/Hexagon/packed-store.ll | 44 + test/CodeGen/Hexagon/packetize-allocframe.ll | 72 ++ test/CodeGen/Hexagon/packetize-call-r29.ll | 25 + test/CodeGen/Hexagon/packetize-impdef-1.ll | 158 +++ test/CodeGen/Hexagon/packetize-impdef.ll | 245 +++++ test/CodeGen/Hexagon/packetize-l2fetch.ll | 34 + test/CodeGen/Hexagon/packetize-volatiles.ll | 29 + test/CodeGen/Hexagon/peephole-move-phi.ll | 53 + test/CodeGen/Hexagon/phi-elim.ll | 25 + test/CodeGen/Hexagon/pic-jt-big.ll | 78 ++ test/CodeGen/Hexagon/pmpyw_acc.ll | 49 + test/CodeGen/Hexagon/postinc-aggr-dag-cycle.ll | 104 ++ test/CodeGen/Hexagon/pred-sched.ll | 41 + test/CodeGen/Hexagon/pred-simp.ll | 27 + test/CodeGen/Hexagon/pred-taken-jump.ll | 52 + test/CodeGen/Hexagon/predtfrs.ll | 62 ++ test/CodeGen/Hexagon/prefetch-intr.ll | 25 + test/CodeGen/Hexagon/prefetch-shuffler-ice.ll | 24 + test/CodeGen/Hexagon/prob-types.ll | 106 ++ test/CodeGen/Hexagon/ps_call_nr.ll | 46 + test/CodeGen/Hexagon/rdf-copy-undef.ll | 159 +++ test/CodeGen/Hexagon/rdf-kill-last-op.ll | 213 ++++ test/CodeGen/Hexagon/redundant-branching2.ll | 74 ++ test/CodeGen/Hexagon/reg-eq-cmp.ll | 44 + test/CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll | 286 ++++++ test/CodeGen/Hexagon/reg-scavengebug-2.ll | 122 +++ test/CodeGen/Hexagon/reg-scavengebug-4.ll | 204 ++++ test/CodeGen/Hexagon/reg-scavengebug-5.ll | 263 +++++ test/CodeGen/Hexagon/reg-scavengebug.ll | 190 ++++ test/CodeGen/Hexagon/reg_seq.ll | 109 +++ .../Hexagon/registerscav-missing-spill-slot.ll | 182 ++++ test/CodeGen/Hexagon/registerscavenger-fail1.ll | 296 ++++++ test/CodeGen/Hexagon/regp-underflow.ll | 102 ++ .../Hexagon/regscav-wrong-super-sub-regs.ll | 199 ++++ test/CodeGen/Hexagon/regscavenger_fail_hwloop.ll | 367 +++++++ test/CodeGen/Hexagon/regscavengerbug.ll | 357 +++++++ test/CodeGen/Hexagon/rotl-i64.ll | 32 + test/CodeGen/Hexagon/save-kill-csr.ll | 95 ++ test/CodeGen/Hexagon/save-regs-thresh.ll | 112 +++ test/CodeGen/Hexagon/sdata-expand-const.ll | 19 + test/CodeGen/Hexagon/sdata-opaque-type.ll | 17 + test/CodeGen/Hexagon/sdata-stack-guard.ll | 52 + test/CodeGen/Hexagon/setmemrefs.ll | 31 + test/CodeGen/Hexagon/sfmin_dce.ll | 18 + test/CodeGen/Hexagon/sfmpyacc_scale.ll | 28 + test/CodeGen/Hexagon/split-vecpred.ll | 106 ++ .../CodeGen/Hexagon/stack-guard-acceptable-type.ll | 33 + test/CodeGen/Hexagon/store-AbsSet.ll | 67 ++ test/CodeGen/Hexagon/store-abs.ll | 75 ++ test/CodeGen/Hexagon/store-constant.ll | 51 + test/CodeGen/Hexagon/store-imm-byte.ll | 13 + test/CodeGen/Hexagon/store-imm-halword.ll | 13 + test/CodeGen/Hexagon/store-imm-word.ll | 13 + test/CodeGen/Hexagon/store-widen-subreg.ll | 59 ++ test/CodeGen/Hexagon/store1.ll | 39 + test/CodeGen/Hexagon/store_abs.ll | 27 + test/CodeGen/Hexagon/struct-const.ll | 72 ++ test/CodeGen/Hexagon/struct_copy.ll | 82 ++ test/CodeGen/Hexagon/struct_copy_sched_r16.ll | 28 + test/CodeGen/Hexagon/sub-add.ll | 90 ++ test/CodeGen/Hexagon/subh-shifted.ll | 24 + test/CodeGen/Hexagon/subh.ll | 24 + test/CodeGen/Hexagon/swiz.ll | 51 + test/CodeGen/Hexagon/swp-badorder.ll | 38 + test/CodeGen/Hexagon/swp-chain-refs.ll | 65 ++ test/CodeGen/Hexagon/swp-change-dep-cycle.ll | 42 + test/CodeGen/Hexagon/swp-change-dep.ll | 64 ++ test/CodeGen/Hexagon/swp-const-tc2.ll | 36 + test/CodeGen/Hexagon/swp-const-tc3.ll | 107 ++ test/CodeGen/Hexagon/swp-cse-phi.ll | 52 + test/CodeGen/Hexagon/swp-dag-phi1.ll | 35 + test/CodeGen/Hexagon/swp-dead-regseq.ll | 41 + test/CodeGen/Hexagon/swp-disable-Os.ll | 130 +++ test/CodeGen/Hexagon/swp-epilog-phi4.ll | 41 + test/CodeGen/Hexagon/swp-epilog-phi5.ll | 184 ++++ test/CodeGen/Hexagon/swp-epilog-phi6.ll | 66 ++ test/CodeGen/Hexagon/swp-epilog-phi8.ll | 44 + test/CodeGen/Hexagon/swp-epilog-phis.ll | 54 + test/CodeGen/Hexagon/swp-epilog-reuse2.ll | 72 ++ test/CodeGen/Hexagon/swp-epilog-reuse3.ll | 90 ++ test/CodeGen/Hexagon/swp-epilog-reuse4.ll | 110 +++ test/CodeGen/Hexagon/swp-exit-fixup.ll | 73 ++ test/CodeGen/Hexagon/swp-fix-last-use.ll | 32 + test/CodeGen/Hexagon/swp-fix-last-use1.ll | 68 ++ test/CodeGen/Hexagon/swp-intreglow8.ll | 91 ++ test/CodeGen/Hexagon/swp-kernel-last-use.ll | 74 ++ test/CodeGen/Hexagon/swp-kernel-phi1.ll | 46 + test/CodeGen/Hexagon/swp-large-rec.ll | 66 ++ test/CodeGen/Hexagon/swp-loop-carried-crash.ll | 344 +++++++ test/CodeGen/Hexagon/swp-loop-carried.ll | 46 + test/CodeGen/Hexagon/swp-loopval.ll | 57 ++ test/CodeGen/Hexagon/swp-lots-deps.ll | 54 + test/CodeGen/Hexagon/swp-maxstart.ll | 38 + test/CodeGen/Hexagon/swp-more-phi.ll | 61 ++ test/CodeGen/Hexagon/swp-multi-phi-refs.ll | 61 ++ test/CodeGen/Hexagon/swp-new-phi.ll | 51 + test/CodeGen/Hexagon/swp-node-order.ll | 55 ++ test/CodeGen/Hexagon/swp-order-carried.ll | 86 ++ test/CodeGen/Hexagon/swp-order-deps1.ll | 48 + test/CodeGen/Hexagon/swp-order-deps3.ll | 30 + test/CodeGen/Hexagon/swp-order-deps4.ll | 68 ++ test/CodeGen/Hexagon/swp-order-deps6.ll | 29 + test/CodeGen/Hexagon/swp-order-prec.ll | 29 + test/CodeGen/Hexagon/swp-order.ll | 67 ++ test/CodeGen/Hexagon/swp-order1.ll | 35 + test/CodeGen/Hexagon/swp-phi-chains.ll | 134 +++ test/CodeGen/Hexagon/swp-phi-def-use.ll | 121 +++ test/CodeGen/Hexagon/swp-phi-dep.ll | 66 ++ test/CodeGen/Hexagon/swp-phi-dep1.ll | 123 +++ test/CodeGen/Hexagon/swp-phi-order.ll | 26 + test/CodeGen/Hexagon/swp-phi-ref1.ll | 72 ++ test/CodeGen/Hexagon/swp-phi.ll | 157 +++ test/CodeGen/Hexagon/swp-physreg.ll | 48 + test/CodeGen/Hexagon/swp-prolog-phi.ll | 55 ++ test/CodeGen/Hexagon/swp-regseq.ll | 24 + test/CodeGen/Hexagon/swp-remove-dep-ice.ll | 35 + test/CodeGen/Hexagon/swp-rename-dead-phi.ll | 68 ++ test/CodeGen/Hexagon/swp-replace-uses1.ll | 59 ++ test/CodeGen/Hexagon/swp-resmii.ll | 43 + test/CodeGen/Hexagon/swp-reuse-phi-1.ll | 44 + test/CodeGen/Hexagon/swp-reuse-phi-2.ll | 52 + test/CodeGen/Hexagon/swp-reuse-phi-4.ll | 169 ++++ test/CodeGen/Hexagon/swp-reuse-phi.ll | 34 + test/CodeGen/Hexagon/swp-stages.ll | 77 ++ test/CodeGen/Hexagon/swp-stages3.ll | 65 ++ test/CodeGen/Hexagon/swp-subreg.ll | 35 + test/CodeGen/Hexagon/swp-swap.ll | 50 + test/CodeGen/Hexagon/swp-tfri.ll | 52 + test/CodeGen/Hexagon/tcm-zext.ll | 25 + test/CodeGen/Hexagon/testbits.ll | 33 + test/CodeGen/Hexagon/tfr-mux-nvj.ll | 33 + test/CodeGen/Hexagon/tied_oper.ll | 49 + test/CodeGen/Hexagon/tls_gd.ll | 25 + test/CodeGen/Hexagon/trivialmemaliascheck.ll | 36 + test/CodeGen/Hexagon/trunc-mpy.ll | 88 ++ test/CodeGen/Hexagon/tstbit.ll | 14 + test/CodeGen/Hexagon/twoaddressbug.ll | 127 +++ test/CodeGen/Hexagon/undef-ret.ll | 19 + test/CodeGen/Hexagon/unordered-fcmp.ll | 61 ++ test/CodeGen/Hexagon/upper-mpy.ll | 87 ++ test/CodeGen/Hexagon/v5_insns.ll | 90 ++ test/CodeGen/Hexagon/v6-inlasm1.ll | 114 +++ test/CodeGen/Hexagon/v6-inlasm2.ll | 33 + test/CodeGen/Hexagon/v6-inlasm3.ll | 44 + test/CodeGen/Hexagon/v6-inlasm4.ll | 29 + test/CodeGen/Hexagon/v6-shuffl.ll | 54 + test/CodeGen/Hexagon/v6-spill1.ll | 267 +++++ test/CodeGen/Hexagon/v6-unaligned-spill.ll | 53 + test/CodeGen/Hexagon/v6-vecpred-copy.ll | 149 +++ test/CodeGen/Hexagon/v60-align.ll | 42 + test/CodeGen/Hexagon/v60-haar-postinc.ll | 120 +++ test/CodeGen/Hexagon/v60-halide-vcombinei8.ll | 51 + test/CodeGen/Hexagon/v60-vec-128b-1.ll | 43 + test/CodeGen/Hexagon/v60-vecpred-spill.ll | 191 ++++ test/CodeGen/Hexagon/v60-vsel2.ll | 99 ++ test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll | 28 + test/CodeGen/Hexagon/v60_sort16.ll | 104 ++ test/CodeGen/Hexagon/v60rol-instrs.ll | 53 + test/CodeGen/Hexagon/v62-CJAllSlots.ll | 63 ++ test/CodeGen/Hexagon/v62-inlasm4.ll | 27 + test/CodeGen/Hexagon/v6vassignp.ll | 30 + test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir | 20 + test/CodeGen/Hexagon/v6vec-vshuff.ll | 32 + test/CodeGen/Hexagon/v6vec_zero.ll | 21 + test/CodeGen/Hexagon/v6vect-dbl-fail1.ll | 45 + test/CodeGen/Hexagon/v6vect-dbl-spill.ll | 151 +++ test/CodeGen/Hexagon/v6vect-dbl.ll | 178 ++++ test/CodeGen/Hexagon/v6vect-dh1.ll | 163 +++ test/CodeGen/Hexagon/v6vect-locals1.ll | 41 + test/CodeGen/Hexagon/v6vect-no-sideeffects.ll | 132 +++ test/CodeGen/Hexagon/v6vect-pred2.ll | 39 + test/CodeGen/Hexagon/v6vect-spill-kill.ll | 137 +++ test/CodeGen/Hexagon/v6vect-vmem1.ll | 24 + test/CodeGen/Hexagon/v6vect-vsplat.ll | 64 ++ test/CodeGen/Hexagon/vadd1.ll | 28 + test/CodeGen/Hexagon/varargs-memv.ll | 32 + test/CodeGen/Hexagon/vasrh.select.ll | 33 + test/CodeGen/Hexagon/vcombine128_to_req_seq.ll | 81 ++ test/CodeGen/Hexagon/vcombine_subreg.ll | 28 + test/CodeGen/Hexagon/vcombine_to_req_seq.ll | 48 + test/CodeGen/Hexagon/vec-align.ll | 46 + test/CodeGen/Hexagon/vec-call-full1.ll | 19 + test/CodeGen/Hexagon/vecPred2Vec.ll | 34 + test/CodeGen/Hexagon/vect-any_extend.ll | 16 + test/CodeGen/Hexagon/vect-dbl-post-inc.ll | 40 + test/CodeGen/Hexagon/vect-set_cc_v2i32.ll | 179 ++++ test/CodeGen/Hexagon/vect-vd0.ll | 22 + test/CodeGen/Hexagon/vect-zero_extend.ll | 25 + test/CodeGen/Hexagon/vect_setcc.ll | 92 ++ test/CodeGen/Hexagon/vect_setcc_v2i16.ll | 106 ++ test/CodeGen/Hexagon/verify-sink-code.ll | 164 ++++ test/CodeGen/Hexagon/verify-undef.ll | 35 + test/CodeGen/Hexagon/vmemu-128.ll | 25 + test/CodeGen/Hexagon/vrcmpys.ll | 77 ++ test/CodeGen/Hexagon/vsplat-ext.ll | 30 + test/CodeGen/Hexagon/wcsrtomb.ll | 183 ++++ 386 files changed, 32789 insertions(+) create mode 100644 test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll create mode 100644 test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll create mode 100644 test/CodeGen/Hexagon/M4_mpyri_addi_global.ll create mode 100644 test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll create mode 100644 test/CodeGen/Hexagon/P08214.ll create mode 100644 test/CodeGen/Hexagon/V60-VDblNew.ll create mode 100644 test/CodeGen/Hexagon/add-use.ll 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test/CodeGen/Hexagon/upper-mpy.ll create mode 100644 test/CodeGen/Hexagon/v5_insns.ll create mode 100644 test/CodeGen/Hexagon/v6-inlasm1.ll create mode 100644 test/CodeGen/Hexagon/v6-inlasm2.ll create mode 100644 test/CodeGen/Hexagon/v6-inlasm3.ll create mode 100644 test/CodeGen/Hexagon/v6-inlasm4.ll create mode 100644 test/CodeGen/Hexagon/v6-shuffl.ll create mode 100644 test/CodeGen/Hexagon/v6-spill1.ll create mode 100644 test/CodeGen/Hexagon/v6-unaligned-spill.ll create mode 100644 test/CodeGen/Hexagon/v6-vecpred-copy.ll create mode 100644 test/CodeGen/Hexagon/v60-align.ll create mode 100644 test/CodeGen/Hexagon/v60-haar-postinc.ll create mode 100644 test/CodeGen/Hexagon/v60-halide-vcombinei8.ll create mode 100644 test/CodeGen/Hexagon/v60-vec-128b-1.ll create mode 100644 test/CodeGen/Hexagon/v60-vecpred-spill.ll create mode 100644 test/CodeGen/Hexagon/v60-vsel2.ll create mode 100644 test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll create mode 100644 test/CodeGen/Hexagon/v60_sort16.ll create mode 100644 test/CodeGen/Hexagon/v60rol-instrs.ll create mode 100644 test/CodeGen/Hexagon/v62-CJAllSlots.ll create mode 100644 test/CodeGen/Hexagon/v62-inlasm4.ll create mode 100644 test/CodeGen/Hexagon/v6vassignp.ll create mode 100644 test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir create mode 100644 test/CodeGen/Hexagon/v6vec-vshuff.ll create mode 100644 test/CodeGen/Hexagon/v6vec_zero.ll create mode 100644 test/CodeGen/Hexagon/v6vect-dbl-fail1.ll create mode 100644 test/CodeGen/Hexagon/v6vect-dbl-spill.ll create mode 100644 test/CodeGen/Hexagon/v6vect-dbl.ll create mode 100644 test/CodeGen/Hexagon/v6vect-dh1.ll create mode 100644 test/CodeGen/Hexagon/v6vect-locals1.ll create mode 100644 test/CodeGen/Hexagon/v6vect-no-sideeffects.ll create mode 100644 test/CodeGen/Hexagon/v6vect-pred2.ll create mode 100644 test/CodeGen/Hexagon/v6vect-spill-kill.ll create mode 100644 test/CodeGen/Hexagon/v6vect-vmem1.ll create mode 100644 test/CodeGen/Hexagon/v6vect-vsplat.ll create mode 100644 test/CodeGen/Hexagon/vadd1.ll create mode 100644 test/CodeGen/Hexagon/varargs-memv.ll create mode 100644 test/CodeGen/Hexagon/vasrh.select.ll create mode 100644 test/CodeGen/Hexagon/vcombine128_to_req_seq.ll create mode 100644 test/CodeGen/Hexagon/vcombine_subreg.ll create mode 100644 test/CodeGen/Hexagon/vcombine_to_req_seq.ll create mode 100644 test/CodeGen/Hexagon/vec-align.ll create mode 100644 test/CodeGen/Hexagon/vec-call-full1.ll create mode 100644 test/CodeGen/Hexagon/vecPred2Vec.ll create mode 100644 test/CodeGen/Hexagon/vect-any_extend.ll create mode 100644 test/CodeGen/Hexagon/vect-dbl-post-inc.ll create mode 100644 test/CodeGen/Hexagon/vect-set_cc_v2i32.ll create mode 100644 test/CodeGen/Hexagon/vect-vd0.ll create mode 100644 test/CodeGen/Hexagon/vect-zero_extend.ll create mode 100644 test/CodeGen/Hexagon/vect_setcc.ll create mode 100644 test/CodeGen/Hexagon/vect_setcc_v2i16.ll create mode 100644 test/CodeGen/Hexagon/verify-sink-code.ll create mode 100644 test/CodeGen/Hexagon/verify-undef.ll create mode 100644 test/CodeGen/Hexagon/vmemu-128.ll create mode 100644 test/CodeGen/Hexagon/vrcmpys.ll create mode 100644 test/CodeGen/Hexagon/vsplat-ext.ll create mode 100644 test/CodeGen/Hexagon/wcsrtomb.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[gcc] branch gcc-7-branch updated (3df36aed52f -> edb4755a7ff)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-7-branch in repository gcc. from 3df36aed52f Daily bump. new edb4755a7ff Don't vectorise zero-step rmw operations (PR 84485) The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 9 +++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/vect/pr84485.c | 34 ++++++++++++++++++++++++++++++++++ gcc/tree-vect-data-refs.c | 12 +++++++++++- 4 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/vect/pr84485.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[clang] branch master updated (1ba6078cca -> 4f1bb770ad)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 1ba6078cca Update the supported C language standards in the user manual. new 4f1bb770ad [analyzer] Trying to fix Windows buildbots after r327258 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/Analysis/scopes-cfg-output.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[gcc] branch master updated (a79f0f43310 -> ffcb61c8e69)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from a79f0f43310 Add a testcase for PR 84799 new ffcb61c8e69 Add a testcase for PR 84821 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/ChangeLog | 4 +++ gcc/testsuite/g++.dg/pr84821.C | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 gcc/testsuite/g++.dg/pr84821.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[llvm] branch master updated (2ee3b171474 -> 7f9dbc4419d)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 2ee3b171474 Revert r326710 "Fuzzer: remove temporary files after we're [...] new b3834e5d6b5 AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal new e0eff38b22d AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES new 7f9dbc4419d AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|E [...] The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 38 +++++ lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 71 ++++++++ .../GlobalISel/legalize-extract-vector-elt.mir | 180 +++++++++++++++++++++ .../GlobalISel/legalize-insert-vector-elt.mir | 21 +++ .../AMDGPU/GlobalISel/legalize-merge-values.mir | 114 +++++++++++++ .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 33 ++++ .../regbankselect-extract-vector-elt.mir | 39 +++++ .../GlobalISel/regbankselect-insert-vector-elt.mir | 152 +++++++++++++++++ .../GlobalISel/regbankselect-merge-values.mir | 44 +++++ 9 files changed, 692 insertions(+) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[gcc] branch master updated (33d103edb93 -> a79f0f43310)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 33d103edb93 PR c++/84802 - ICE capturing uninstantiated class. new a79f0f43310 Add a testcase for PR 84799 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/pr84799.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pr84799.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[llvm] branch master updated (59a0caa4c55 -> 2ee3b171474)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 59a0caa4c55 [mips] Split out ASEPredicate from InsnPredicates (NFC) new 2ee3b171474 Revert r326710 "Fuzzer: remove temporary files after we're [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/tools/llvm-isel-fuzzer/aarch64-execname-options.ll | 3 --- test/tools/llvm-isel-fuzzer/execname-options.ll | 3 --- test/tools/llvm-opt-fuzzer/exec-options.ll | 4 ---- 3 files changed, 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[newlib] branch master updated (a35273000 -> c8d96a96e)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository newlib. from a35273000 character data generation new c8d96a96e make target for explicit Unicode data tables generation The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: newlib/Makefile.am | 9 +++++++++ 1 file changed, 9 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

[llvm] branch master updated (a722fa24b2f -> 59a0caa4c55)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from a722fa24b2f MC intel asm parser: Allow @ at the start of function names. new 59a0caa4c55 [mips] Split out ASEPredicate from InsnPredicates (NFC) The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/Mips/MicroMipsDSPInstrFormats.td | 4 ++-- lib/Target/Mips/Mips.td | 5 +++- lib/Target/Mips/MipsDSPInstrFormats.td | 10 ++++---- lib/Target/Mips/MipsEVAInstrInfo.td | 36 ++++++++++++++--------------- lib/Target/Mips/MipsInstrInfo.td | 21 ++++++++--------- 5 files changed, 38 insertions(+), 38 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 8 months

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Tcwg-commits March 2018