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from e1d101a02d5 2018-03-15 Richard Biener <rguenther(a)suse.de>
new 617b572b0d4 rs6000: Fix for the previous abi_v4_pass_in_fpr change
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Summary of changes:
gcc/ChangeLog | 6 ++++++
gcc/config/rs6000/rs6000.c | 4 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
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from e7dd436d902 [X86][SSE] Introduce Float/Vector WriteMove, WriteLoad and [...]
new 353be84b744 [InstSimplify] add tests with NaN operand for fp binops; NFC
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test/Transforms/InstSimplify/fp-nan.ll | 185 +++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
create mode 100644 test/Transforms/InstSimplify/fp-nan.ll
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from dc55b3ba688 [X86] Regenerate schedule tests with zero latency comments
new e7dd436d902 [X86][SSE] Introduce Float/Vector WriteMove, WriteLoad and [...]
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lib/Target/X86/X86InstrSSE.td | 80 +++++++++++++++++----------------
lib/Target/X86/X86SchedBroadwell.td | 8 ++++
lib/Target/X86/X86SchedHaswell.td | 8 ++++
lib/Target/X86/X86SchedSandyBridge.td | 8 ++++
lib/Target/X86/X86SchedSkylakeClient.td | 8 ++++
lib/Target/X86/X86SchedSkylakeServer.td | 8 ++++
lib/Target/X86/X86Schedule.td | 6 +++
lib/Target/X86/X86ScheduleBtVer2.td | 9 +++-
lib/Target/X86/X86ScheduleSLM.td | 8 ++++
lib/Target/X86/X86ScheduleZnver1.td | 8 ++++
test/CodeGen/X86/avx-schedule.ll | 8 ++--
test/CodeGen/X86/avx2-schedule.ll | 10 ++---
test/CodeGen/X86/sha-schedule.ll | 12 ++---
test/CodeGen/X86/sse-schedule.ll | 6 +--
test/CodeGen/X86/sse2-schedule.ll | 8 ++--
test/CodeGen/X86/sse3-schedule.ll | 6 +--
test/CodeGen/X86/sse41-schedule.ll | 22 ++++-----
17 files changed, 148 insertions(+), 75 deletions(-)
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from 32a44d6e [clang-tidy] rename_check.py misc-unused-raii bugprone-unused [...]
new 414ad1eb [change-namespace] Don't match a function call/ref multiple times.
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change-namespace/ChangeNamespace.cpp | 14 ++++----
.../change-namespace/ChangeNamespaceTests.cpp | 40 ++++++++++++++++++++--
2 files changed, 45 insertions(+), 9 deletions(-)
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from 175ecc97981 [InstSimplify] remove 'nsz' requirement for frem 0, X
new e2ee2c948f5 [PatternMatch, InstSimplify] allow undef elements when matc [...]
new dc55b3ba688 [X86] Regenerate schedule tests with zero latency comments
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include/llvm/IR/PatternMatch.h | 22 ++---
lib/Analysis/InstructionSimplify.cpp | 16 ++--
test/CodeGen/X86/mmx-schedule.ll | 10 +--
test/CodeGen/X86/schedule-x86_32.ll | 2 +-
test/CodeGen/X86/schedule-x86_64.ll | 4 +-
test/CodeGen/X86/x87-schedule.ll | 140 +++++++++++++++---------------
test/Transforms/InstSimplify/fast-math.ll | 18 ++--
7 files changed, 100 insertions(+), 112 deletions(-)
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unknown user pushed a change to branch master
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from 0bb869733 [arm] Fix syscalls.c for newlib embedded syscalls builds
new 948db3e4b Correct prototypes of pthread_mutex_getprioceiling() and pthr [...]
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newlib/libc/include/pthread.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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from 94b082e3cc6 [AArch64] Codegen tests for the Armv8.2-A FP16 intrinsics
new 175ecc97981 [InstSimplify] remove 'nsz' requirement for frem 0, X
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lib/Analysis/InstructionSimplify.cpp | 16 +++++++++++-----
test/Transforms/InstSimplify/fast-math.ll | 9 +++------
2 files changed, 14 insertions(+), 11 deletions(-)
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from 170747ec42d [Debug] Retain both copies of debug intrinsics in HoistThen [...]
new 94b082e3cc6 [AArch64] Codegen tests for the Armv8.2-A FP16 intrinsics
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test/CodeGen/AArch64/fp16_intrinsic_lane.ll | 301 ++++++++++++++++++++
test/CodeGen/AArch64/fp16_intrinsic_scalar_1op.ll | 318 ++++++++++++++++++++++
test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll | 117 ++++++++
test/CodeGen/AArch64/fp16_intrinsic_scalar_3op.ll | 13 +
test/CodeGen/AArch64/fp16_intrinsic_vector_1op.ll | 42 +++
test/CodeGen/AArch64/fp16_intrinsic_vector_2op.ll | 80 ++++++
test/CodeGen/AArch64/fp16_intrinsic_vector_3op.ll | 22 ++
7 files changed, 893 insertions(+)
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_lane.ll
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_scalar_1op.ll
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_scalar_3op.ll
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_vector_1op.ll
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_vector_2op.ll
create mode 100644 test/CodeGen/AArch64/fp16_intrinsic_vector_3op.ll
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unknown user pushed a change to branch master
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from 7f76323e3 @skipUnlessDarwin TestTargetSourceMap
new 628a53e21 Next batch of test-tree-cleaning changes
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.../process_launch/TestProcessLaunch.py | 57 ++++-------------
.../TestSingleQuoteInFilename.py | 36 ++++-------
packages/Python/lldbsuite/test/lldbutil.py | 22 +++++--
.../Python/lldbsuite/test/settings/TestSettings.py | 74 ++++++----------------
.../test/terminal/TestSTTYBeforeAndAfter.py | 59 +++++++----------
.../lldbsuite/test/tools/lldb-mi/TestMiFile.py | 2 +-
.../test/tools/lldb-mi/lldbmi_testcase.py | 2 +-
.../startup_options/TestMiStartupOptions.py | 4 +-
.../test/tools/lldb-mi/syntax/TestMiSyntax.py | 2 +-
9 files changed, 87 insertions(+), 171 deletions(-)
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unknown user pushed a change to branch master
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from f51bd43cfa More warnings when double truncation to float: compound assi [...]
new 84c267252d [AAch64] Tests for ACLE FP16 macros
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test/Preprocessor/aarch64-target-features.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
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