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unknown user pushed a change to branch release/2.26/master
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from 989f59db39 tst-ttyname: skip the test when /dev/ptmx is not available
new 268bd5f053 ia64: Fix memchr for large input sizes (BZ #22603)
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Summary of changes:
ChangeLog | 7 +++++++
sysdeps/ia64/memchr.S | 4 ++++
2 files changed, 11 insertions(+)
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unknown user pushed a change to branch master
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from 19f4e05ad98 [RISCV] Add support for llvm.{frameaddress,returnaddress} i [...]
new c752a363cf7 [RISCV] Implement branch analysis
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lib/Target/RISCV/RISCVInstrInfo.cpp | 166 ++++++++++++++++++++
lib/Target/RISCV/RISCVInstrInfo.h | 16 ++
test/CodeGen/RISCV/analyze-branch.ll | 91 +++++++++++
test/CodeGen/RISCV/branch.ll | 33 ++--
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 228 ++++++++++++++--------------
test/CodeGen/RISCV/jumptable.ll | 45 +++---
test/CodeGen/RISCV/select-cc.ll | 2 +-
7 files changed, 422 insertions(+), 159 deletions(-)
create mode 100644 test/CodeGen/RISCV/analyze-branch.ll
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unknown user pushed a change to branch master
in repository gcc.
from 282b84c7673 2018-01-10 Paolo Carlini <paolo.carlini(a)oracle.com>
new 459a193b6f6 * config/rs6000/x86intrin.h: Change #warning to #error. Up [...]
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gcc/ChangeLog | 7 +++++++
gcc/config/rs6000/emmintrin.h | 2 +-
gcc/config/rs6000/mmintrin.h | 2 +-
gcc/config/rs6000/x86intrin.h | 2 +-
gcc/config/rs6000/xmmintrin.h | 2 +-
5 files changed, 11 insertions(+), 4 deletions(-)
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unknown user pushed a change to branch master
in repository clang.
from 680b3a8619 Revert "[Driver] Update default sanitizer blacklist location"
new f3d739418b [Driver] Test for correct '--version' suggestion
new 0d034354cd [MSan] Enable use-after-dtor instrumentation by default.
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include/clang/Driver/SanitizerArgs.h | 2 +-
test/CodeGenCXX/sanitize-no-dtor-callback.cpp | 6 ++++--
test/Driver/fsanitize.c | 2 +-
test/Driver/unknown-arg.c | 3 ++-
4 files changed, 8 insertions(+), 5 deletions(-)
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unknown user pushed a change to branch master
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from 6276041e3 [hwasan] An option to disable tag randomization.
new a099b7729 [MSan] Enable use-after-dtor instrumentation by default.
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test/msan/dtor-member.cc | 2 +-
test/msan/use-after-dtor.cc | 19 ++++++++++++-------
2 files changed, 13 insertions(+), 8 deletions(-)
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unknown user pushed a change to branch master
in repository llvm.
from 077409ff7e5 [RISCV] Add basic support for inline asm constraints
new 19f4e05ad98 [RISCV] Add support for llvm.{frameaddress,returnaddress} i [...]
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lib/Target/RISCV/RISCVISelLowering.cpp | 57 +++++++++++++++++
lib/Target/RISCV/RISCVISelLowering.h | 2 +
test/CodeGen/RISCV/frameaddr-returnaddr.ll | 99 ++++++++++++++++++++++++++++++
3 files changed, 158 insertions(+)
create mode 100644 test/CodeGen/RISCV/frameaddr-returnaddr.ll
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unknown user pushed a change to branch master
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from 46eef0bf1 [WebAssembly] Move relocation handling InputChunks.cpp
new dc094d7f9 [WebAssembly] Optimize Writer::lookupType
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wasm/Writer.cpp | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
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unknown user pushed a change to branch master
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from 58c4e96dc99 [RISCV] Support stack frames and offsets up to 32-bits
new 077409ff7e5 [RISCV] Add basic support for inline asm constraints
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lib/Target/RISCV/RISCVAsmPrinter.cpp | 55 ++++++++++++++++++++++
lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 19 ++++++++
lib/Target/RISCV/RISCVISelLowering.cpp | 18 ++++++++
lib/Target/RISCV/RISCVISelLowering.h | 4 ++
test/CodeGen/RISCV/{imm.ll => inline-asm.ll} | 69 ++++++++++++++--------------
5 files changed, 131 insertions(+), 34 deletions(-)
copy test/CodeGen/RISCV/{imm.ll => inline-asm.ll} (51%)
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unknown user pushed a change to branch master
in repository gcc.
from d76863c8a62 Preserving locations for variable-uses and constants (PR c+ [...]
new 31ca46e310e os, syscall: handle _st_timespec for AIX stat
new 282b84c7673 2018-01-10 Paolo Carlini <paolo.carlini(a)oracle.com>
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gcc/cp/ChangeLog | 7 +++++++
gcc/cp/parser.c | 10 ++--------
gcc/go/gofrontend/MERGE | 2 +-
libgo/go/os/{stat_atim.go => stat_aix.go} | 8 +++-----
libgo/go/os/stat_atim.go | 2 +-
libgo/go/syscall/syscall_aix.go | 8 ++++++++
libgo/mksysinfo.sh | 8 +++++++-
7 files changed, 29 insertions(+), 16 deletions(-)
copy libgo/go/os/{stat_atim.go => stat_aix.go} (84%)
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unknown user pushed a change to branch master
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from 2e927189047 [RISCV] Support for varargs
new 58c4e96dc99 [RISCV] Support stack frames and offsets up to 32-bits
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lib/Target/RISCV/RISCVFrameLowering.cpp | 30 ++++++++++++++++++++------
lib/Target/RISCV/RISCVInstrInfo.cpp | 20 +++++++++++++++++
lib/Target/RISCV/RISCVInstrInfo.h | 5 +++++
lib/Target/RISCV/RISCVRegisterInfo.cpp | 27 +++++++++++++++++++----
lib/Target/RISCV/RISCVRegisterInfo.h | 8 +++++++
test/CodeGen/RISCV/large-stack.ll | 38 +++++++++++++++++++++++++++++++++
6 files changed, 117 insertions(+), 11 deletions(-)
create mode 100644 test/CodeGen/RISCV/large-stack.ll
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