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from 1076969bfeb Followup on Proposal to move MIR physical register namespac [...]
new 48c8d1e7632 [llvm-cov] Fix incorrect usage of .precision specifier in f [...]
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tools/llvm-cov/SourceCoverageViewHTML.cpp | 2 +-
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from 54540bdd479 PR rtl-optimization/84123 * combine.c (change_zero_ext): [...]
new d3af137c241 PR c/81779 * c-parser.c (c_parser_compound_statement_nost [...]
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gcc/c/ChangeLog | 6 ++++++
gcc/c/c-parser.c | 1 +
gcc/testsuite/ChangeLog | 5 +++++
gcc/testsuite/gcc.dg/pr81779.c | 15 +++++++++++++++
4 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/gcc.dg/pr81779.c
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from 5762b182a1 [clang-format] Align preprocessor comments with #
new 253065ecad [PR32482] Fix bitfield layout for -mms-bitfield and pragma pack
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lib/AST/RecordLayoutBuilder.cpp | 7 ++++---
test/CodeGen/mms-bitfields.c | 43 +++++++++++++++++++++++++++++++++++++++++
test/Sema/mms-bitfields.c | 15 ++++++++++++++
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from 2fa4cfef [clangd] Add a test URI scheme for lit tests to unbreak platf [...]
new ceea3284 [clang-tidy] New argument --language to add_new_check.py
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clang-tidy/add_new_check.py | 49 ++++++++++++++++++++++++++++++---------------
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from 65c4c248c Add LWG3051
new 37e4c9b15 Implement LWG2870: Default value of parameter theta of polar [...]
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include/complex | 4 ++--
test/std/numerics/complex.number/complex.value.ops/polar.pass.cpp | 2 +-
www/cxx2a_status.html | 4 ++--
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from c0655a3ec04 PR fortran/84116 * openmp.c (gfc_match_omp_clauses): If a [...]
new 54540bdd479 PR rtl-optimization/84123 * combine.c (change_zero_ext): [...]
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gcc/ChangeLog | 6 ++++++
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from 750addfeb Fix TestMixedDwarfBinary.py
new 4360355fc replace os.mkdirs with lldbutil.mkdir_p (NFC)
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.../lldbsuite/test/functionalities/process_launch/TestProcessLaunch.py | 3 +--
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from e4eed790f89 [x86] Make the retpoline thunk insertion a machine function pass.
new 42b2a1d5ed9 [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC
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lib/Target/Hexagon/HexagonISelLowering.cpp | 42 ++++++++---------
lib/Target/Hexagon/HexagonISelLowering.h | 4 +-
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 66 +++++++++++++--------------
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from 8e8c64faa1f [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering
new 2bd04d66a7c [SeparateConstOffsetFromGEP] Fix up addrspace in the AMDGPU test
new f42f82fde05 [Hexagon] Implement HVX codegen for vector shifts
new e4eed790f89 [x86] Make the retpoline thunk insertion a machine function pass.
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lib/Target/Hexagon/HexagonISelLowering.cpp | 92 ++---
lib/Target/Hexagon/HexagonISelLowering.h | 1 +
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 6 +
lib/Target/Hexagon/HexagonPatterns.td | 22 +-
lib/Target/X86/X86.h | 2 +-
lib/Target/X86/X86RetpolineThunks.cpp | 135 +++++---
test/CodeGen/Hexagon/autohvx/isel-build-undef.ll | 2 +-
test/CodeGen/Hexagon/autohvx/shift-128b.ll | 376 +++++++++++++++++++++
test/CodeGen/Hexagon/autohvx/shift-64b.ll | 232 +++++++++++++
test/CodeGen/X86/O0-pipeline.ll | 3 +-
...split-gep-and-gvn-addrspace-addressing-modes.ll | 12 +-
11 files changed, 756 insertions(+), 127 deletions(-)
create mode 100644 test/CodeGen/Hexagon/autohvx/shift-128b.ll
create mode 100644 test/CodeGen/Hexagon/autohvx/shift-64b.ll
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