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from 930b5f8bfb Fix -fuse-ld option to accept string argument.
new 86d6a90c58 Fix scm-ports.exp regression
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gdb/testsuite/ChangeLog | 5 +++++
gdb/testsuite/gdb.guile/scm-ports.exp | 2 +-
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unknown user pushed a change to branch gdb-8.0-branch
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from ea3b3edea7 Automatic date update in version.in
new 92533dc55e Fix scm-ports.exp regression
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gdb/testsuite/ChangeLog | 5 +++++
gdb/testsuite/gdb.guile/scm-ports.exp | 2 +-
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from 68ee79b605b [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors
new b46f02d9e67 [Hexagon] Implement signed and unsigned multiply-high for vectors
new f20c58e01be [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
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lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 5 +-
.../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 5 +-
lib/Target/AMDGPU/SIDefines.h | 3 +-
lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 10 +-
lib/Target/Hexagon/HexagonISelLowering.cpp | 7 ++
lib/Target/Hexagon/HexagonISelLowering.h | 1 +
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 111 ++++++++++++++++++++-
lib/Target/Hexagon/HexagonPatterns.td | 50 ++++++++++
test/CodeGen/AMDGPU/addrspacecast.ll | 6 +-
test/MC/AMDGPU/sopk-err.s | 10 +-
test/MC/AMDGPU/sopk.s | 87 ++++++++++------
11 files changed, 251 insertions(+), 44 deletions(-)
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from df0e58eed1a [AMDGPU] Copy impdefs from pseudo to real instructions
new 68ee79b605b [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors
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lib/Target/Hexagon/HexagonISelLowering.cpp | 153 ++++++++++++++++++++++-------
test/CodeGen/Hexagon/vect/shuff-32.ll | 86 ++++++++++++++++
test/CodeGen/Hexagon/vect/shuff-64.ll | 66 +++++++++++++
3 files changed, 267 insertions(+), 38 deletions(-)
create mode 100644 test/CodeGen/Hexagon/vect/shuff-32.ll
create mode 100644 test/CodeGen/Hexagon/vect/shuff-64.ll
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from ad2c64f0 [clangd] Merge results from static/dynamic index.
new 718c5c60 [clang-tidy] Expand readability-redundant-smartptr-get to und [...]
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.../readability/RedundantSmartptrGetCheck.cpp | 19 +++++++++++-----
.../readability-redundant-smartptr-get.cpp | 26 ++++++++++++++++++----
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from cf3cf39d53 [ARM] Add new macro for Thumb-only opcodes
new 930b5f8bfb Fix -fuse-ld option to accept string argument.
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gold/ChangeLog | 5 +++++
gold/options.h | 2 +-
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from 94cb0130bcb [docs] Fix mention of GCC frontend
new 844c0ec2bb3 [X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt patt [...]
new df0e58eed1a [AMDGPU] Copy impdefs from pseudo to real instructions
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lib/Target/AMDGPU/VOP1Instructions.td | 1 +
lib/Target/AMDGPU/VOP2Instructions.td | 1 +
lib/Target/AMDGPU/VOPCInstructions.td | 1 +
lib/Target/AMDGPU/VOPInstructions.td | 1 +
lib/Target/X86/X86ScheduleBtVer2.td | 10 +++++-----
5 files changed, 9 insertions(+), 5 deletions(-)
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from a73a299e6b [clang-format] Adds a FormatStyleSet
new e0f57df6fa [RISCV] Implement RISCV ABI lowering
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lib/CodeGen/TargetInfo.cpp | 181 +++++++++++++++++
test/CodeGen/riscv32-abi.c | 426 ++++++++++++++++++++++++++++++++++++++++
test/CodeGen/riscv64-abi.c | 425 +++++++++++++++++++++++++++++++++++++++
test/Driver/riscv32-toolchain.c | 47 +++++
test/Driver/riscv64-toolchain.c | 47 +++++
5 files changed, 1126 insertions(+)
create mode 100644 test/CodeGen/riscv32-abi.c
create mode 100644 test/CodeGen/riscv64-abi.c
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