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from 2aa82e09308 Adding test cases for PR34629 & PR34634.
new 51972c12fda [X86] Remove isel patterns for movlpd/movlps with integer t [...]
new e87effbc352 [X86] Remove isel patterns for X86Movhlps and X86Movlhps wi [...]
new 41d51883a47 [X86] Remove patterns for X86Movddup with v4i64 type. Lower [...]
new fafcf424107 [X86] Colocate all of the X86VBroadcast patterns for v2i64 [...]
new 5cd36ff15cd [X86] Synchronize a pattern between SSE1 and AVX/AVX512.
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lib/Target/X86/X86InstrAVX512.td | 28 +----------------
lib/Target/X86/X86InstrSSE.td | 66 +++-------------------------------------
2 files changed, 6 insertions(+), 88 deletions(-)
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from a857498d9e Fix the second half of PR34266: Don't implicitly capture '* [...]
new dcd8d797b2 [X86] Move even more of our CPU to feature mapping switch to [...]
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lib/Basic/Targets/X86.cpp | 84 ++++++++++++++++++++++-------------------------
1 file changed, 40 insertions(+), 44 deletions(-)
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from 3546005 regression_views: Add some missing session parameters
new c30d6fa [lnt] Allow `lnt importreport` to import hash and profile metrics.
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lnt/lnttool/import_report.py | 5 ++++-
tests/lnttool/test_importreport.py | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
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from 61cfebc8aab Fix gccbrig documentation build
new dba5ed0deba 2017-09-17 Paul Thomas <pault(a)gcc.gnu.org>
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gcc/fortran/ChangeLog | 14 +++++++
gcc/fortran/decl.c | 4 +-
gcc/fortran/primary.c | 15 ++++++-
gcc/fortran/resolve.c | 63 +++++++++++++++++++++++++-----
gcc/testsuite/ChangeLog | 16 ++++++++
gcc/testsuite/gfortran.dg/associate_25.f90 | 32 +++++++++++++++
gcc/testsuite/gfortran.dg/associate_9.f03 | 5 +--
gcc/testsuite/gfortran.dg/pdt_1.f03 | 2 +-
gcc/testsuite/gfortran.dg/pdt_11.f03 | 52 ++++++++++++++++++++++++
gcc/testsuite/gfortran.dg/pdt_12.f03 | 42 ++++++++++++++++++++
gcc/testsuite/gfortran.dg/pdt_2.f03 | 3 +-
gcc/testsuite/gfortran.dg/pdt_3.f03 | 2 +-
gcc/testsuite/gfortran.dg/pdt_4.f03 | 22 ++++++++---
13 files changed, 246 insertions(+), 26 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/associate_25.f90
create mode 100644 gcc/testsuite/gfortran.dg/pdt_11.f03
create mode 100644 gcc/testsuite/gfortran.dg/pdt_12.f03
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from 6402565d2dc [ThinLTO] Avoid archive member collisions with old API
new 3de9cb6125d Revert "[ThinLTO] Avoid archive member collisions with old API"
new 2aa82e09308 Adding test cases for PR34629 & PR34634.
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lib/LTO/ThinLTOCodeGenerator.cpp | 4 +--
test/CodeGen/X86/pr34629.ll | 52 +++++++++++++++++++++++++++++++
test/CodeGen/X86/pr34634.ll | 67 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 120 insertions(+), 3 deletions(-)
create mode 100644 test/CodeGen/X86/pr34629.ll
create mode 100644 test/CodeGen/X86/pr34634.ll
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from a1c2bb91ad6 [RISCV] Add support for disassembly
new 6402565d2dc [ThinLTO] Avoid archive member collisions with old API
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lib/LTO/ThinLTOCodeGenerator.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
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from e7476fadc9 [X86] Remove unnecessary extra encodings from the CPU name e [...]
new a857498d9e Fix the second half of PR34266: Don't implicitly capture '* [...]
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lib/Sema/SemaExpr.cpp | 86 ++++++++++++++
lib/Sema/SemaExprMember.cpp | 48 +-------
test/SemaCXX/cxx1y-generic-lambdas-capturing.cpp | 142 +++++++++++++++++++++++
3 files changed, 229 insertions(+), 47 deletions(-)
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from 26132ea8ed7 [RISCV] Add support for all RV32I instructions
new a1c2bb91ad6 [RISCV] Add support for disassembly
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lib/Target/RISCV/CMakeLists.txt | 3 +
lib/Target/RISCV/Disassembler/CMakeLists.txt | 3 +
.../{InstPrinter => Disassembler}/LLVMBuild.txt | 7 +-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 135 +++++++++++++++++++++
lib/Target/RISCV/LLVMBuild.txt | 3 +-
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 20 +++
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 4 +
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h | 3 +
lib/Target/RISCV/RISCVInstrFormats.td | 5 +
lib/Target/RISCV/RISCVInstrInfo.td | 8 ++
test/MC/RISCV/rv32i-valid.s | 4 +
11 files changed, 191 insertions(+), 4 deletions(-)
create mode 100644 lib/Target/RISCV/Disassembler/CMakeLists.txt
copy lib/Target/RISCV/{InstPrinter => Disassembler}/LLVMBuild.txt (81%)
create mode 100644 lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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from 414ee511a79 [GlobalISel][X86] refactoring X86InstructionSelector.cpp .NFC.
new 26132ea8ed7 [RISCV] Add support for all RV32I instructions
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lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 156 +++++++++++++++++++--
lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 14 ++
lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h | 1 +
lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 54 +++++++
.../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 19 +++
lib/Target/RISCV/RISCVInstrInfo.td | 148 ++++++++++++++++++-
test/MC/RISCV/rv32i-invalid.s | 50 ++++++-
test/MC/RISCV/rv32i-valid.s | 150 ++++++++++++++++++++
8 files changed, 575 insertions(+), 17 deletions(-)
create mode 100644 lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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from 1183423ec59 [GlobalISel][X86] Legalize i1 G_ADD/G_SUB/G_MUL/G_XOR/G_OR/ [...]
new 414ee511a79 [GlobalISel][X86] refactoring X86InstructionSelector.cpp .NFC.
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lib/Target/X86/X86InstructionSelector.cpp | 145 ++++++++++++++++--------------
1 file changed, 76 insertions(+), 69 deletions(-)
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