Tcwg-commits July 2017

tcwg-commits@lists.linaro.org

7 participants
3338 discussions

[llvm] branch master updated (4a7d3a3e55a -> d519d29dbba)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 4a7d3a3e55a [X86][SSE4A] Add support for combining from non-v16i8 EXTRQ [...] new d519d29dbba [ARM][test] Added test/CodeGen/ARM/ror.ll test. NFC precomm [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/CodeGen/ARM/ror.ll | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 test/CodeGen/ARM/ror.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[clang] branch master updated (e20a5f4e97 -> 9ab24b50c1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from e20a5f4e97 clang-format: [JS] space between pseudo keywords and templat [...] new 2382d78024 Enable LLVM asan support for NetBSD/amd64 new 9ab24b50c1 [AMDGPU] Fix regressions on mesa/clover with libclc due to a [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Basic/Targets.cpp | 28 ++++++++++++++++++---------- lib/Driver/ToolChains/CommonArgs.cpp | 1 + lib/Driver/ToolChains/NetBSD.cpp | 13 +++++++++++++ lib/Driver/ToolChains/NetBSD.h | 1 + test/CodeGenOpenCL/address-spaces.cl | 2 ++ 5 files changed, 35 insertions(+), 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[lld] branch master updated (928add4d1 -> b3af1329c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 928add4d1 Move clearOutputSections earlier. NFC. new 2e86113a2 Move clearOutputSections earlier. NFC. new b3af1329c Move clearOutputSections earlier. NFC. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/Writer.cpp | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[gcc] branch master updated (bf3827ef178 -> c0ba65ffdef)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from bf3827ef178 [ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8 new c0ba65ffdef PR debug/81278 * tree-vrp.c (compare_assert_loc): Turn in [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 14 ++++++++++++++ gcc/tree-vrp.c | 54 +++++++++++++++++++++++++++++++++++++++++++++--------- 2 files changed, 59 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[lld] branch master updated (3c1f979e1 -> 928add4d1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 3c1f979e1 ELF: Only unlink regular files new 928add4d1 Move clearOutputSections earlier. NFC. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/Writer.cpp | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[llvm] branch master updated (aa47088124c -> 4a7d3a3e55a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from aa47088124c Fix signed/unsigned comparison warnings new 4a7d3a3e55a [X86][SSE4A] Add support for combining from non-v16i8 EXTRQ [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86ISelLowering.cpp | 6 +-- test/CodeGen/X86/vector-shuffle-combining-sse4a.ll | 29 +++++-------- test/CodeGen/X86/vector-shuffle-sse4a.ll | 48 ++++++++++++++-------- 3 files changed, 44 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[llvm] branch master updated (f9e9586c800 -> aa47088124c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from f9e9586c800 [AMDGPU] Switch scalarize global loads ON by default Differ [...] new aa47088124c Fix signed/unsigned comparison warnings The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/Utils/X86ShuffleDecode.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[binutils-gdb] branch master updated (40c7d50720 -> 4da3eb35ef)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 40c7d50720 [Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A new 4da3eb35ef Garbage collect TYPE_STATIC and several TYPE_FN_FIELD_x The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 11 +++++++++++ gdb/gdbtypes.c | 4 ---- gdb/gdbtypes.h | 21 +-------------------- 3 files changed, 12 insertions(+), 24 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[gcc] branch master updated (9901a973e51 -> bf3827ef178)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 9901a973e51 * ipa-utils.c (ipa_merge_profiles): Fix merging when dst i [...] new bf3827ef178 [ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 5 +++++ gcc/config/arm/driver-arm.c | 2 ++ 2 files changed, 7 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

[llvm] branch master updated (f7fcbf440d4 -> f9e9586c800)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from f7fcbf440d4 [LoopDeletion] NFC: Add loop being analyzed debug statement new f9e9586c800 [AMDGPU] Switch scalarize global loads ON by default Differ [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- test/CodeGen/AMDGPU/add.ll | 18 ++--- test/CodeGen/AMDGPU/add_i128.ll | 16 ++-- test/CodeGen/AMDGPU/add_i64.ll | 8 +- test/CodeGen/AMDGPU/alignbit-pat.ll | 2 +- test/CodeGen/AMDGPU/and-gcn.ll | 3 +- test/CodeGen/AMDGPU/and.ll | 55 ++++++++----- test/CodeGen/AMDGPU/any_extend_vector_inreg.ll | 6 +- test/CodeGen/AMDGPU/bitreverse.ll | 20 +++-- test/CodeGen/AMDGPU/bswap.ll | 2 +- test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll | 8 +- test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 6 +- test/CodeGen/AMDGPU/coalescer_remat.ll | 2 +- test/CodeGen/AMDGPU/copy-illegal-type.ll | 62 +++++++++------ test/CodeGen/AMDGPU/ctlz.ll | 48 ++++++++---- test/CodeGen/AMDGPU/ctlz_zero_undef.ll | 74 +++++++++++------- test/CodeGen/AMDGPU/ctpop.ll | 91 +++++++++++++++------- test/CodeGen/AMDGPU/ctpop64.ll | 29 +++++-- test/CodeGen/AMDGPU/cttz_zero_undef.ll | 19 +++-- test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 88 ++++++++++++++------- test/CodeGen/AMDGPU/early-if-convert-cost.ll | 2 +- test/CodeGen/AMDGPU/early-if-convert.ll | 2 +- .../AMDGPU/enable-no-signed-zeros-fp-math.ll | 9 ++- test/CodeGen/AMDGPU/extractelt-to-trunc.ll | 14 +++- test/CodeGen/AMDGPU/fabs.f16.ll | 4 +- test/CodeGen/AMDGPU/fadd.f16.ll | 40 ++++++---- test/CodeGen/AMDGPU/fadd64.ll | 12 ++- test/CodeGen/AMDGPU/fcanonicalize.f16.ll | 18 ++++- test/CodeGen/AMDGPU/fcanonicalize.ll | 2 +- test/CodeGen/AMDGPU/fcmp.f16.ll | 4 +- test/CodeGen/AMDGPU/fcmp64.ll | 12 +-- test/CodeGen/AMDGPU/fconst64.ll | 9 ++- test/CodeGen/AMDGPU/fcopysign.f16.ll | 91 ++++++++++++++-------- test/CodeGen/AMDGPU/fma-combine.ll | 6 +- test/CodeGen/AMDGPU/fma.f64.ll | 4 +- test/CodeGen/AMDGPU/fma.ll | 4 +- test/CodeGen/AMDGPU/fmul.f16.ll | 4 +- test/CodeGen/AMDGPU/fmul64.ll | 4 +- test/CodeGen/AMDGPU/fmuladd.f32.ll | 18 ++--- test/CodeGen/AMDGPU/fmuladd.f64.ll | 12 +-- test/CodeGen/AMDGPU/fmuladd.v2f16.ll | 18 ++--- test/CodeGen/AMDGPU/fneg-fabs.ll | 6 +- test/CodeGen/AMDGPU/fneg.f16.ll | 6 +- test/CodeGen/AMDGPU/fp32_to_fp16.ll | 6 +- test/CodeGen/AMDGPU/fpext.f16.ll | 6 +- test/CodeGen/AMDGPU/fptosi.f16.ll | 4 +- test/CodeGen/AMDGPU/fptoui.f16.ll | 4 +- test/CodeGen/AMDGPU/fptrunc.f16.ll | 6 +- test/CodeGen/AMDGPU/fract.f64.ll | 10 +-- test/CodeGen/AMDGPU/fract.ll | 10 +-- test/CodeGen/AMDGPU/frem.ll | 6 +- test/CodeGen/AMDGPU/fsqrt.f64.ll | 4 +- test/CodeGen/AMDGPU/fsqrt.ll | 6 +- test/CodeGen/AMDGPU/fsub.f16.ll | 6 +- test/CodeGen/AMDGPU/fsub.ll | 6 +- test/CodeGen/AMDGPU/fsub64.ll | 4 +- test/CodeGen/AMDGPU/ftrunc.f64.ll | 6 +- test/CodeGen/AMDGPU/global-extload-i16.ll | 4 +- test/CodeGen/AMDGPU/half.ll | 4 +- test/CodeGen/AMDGPU/imm.ll | 4 +- test/CodeGen/AMDGPU/immv216.ll | 6 +- test/CodeGen/AMDGPU/indirect-addressing-si.ll | 8 +- .../AMDGPU/invariant-load-no-alias-store.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.class.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll | 4 +- test/CodeGen/AMDGPU/llvm.ceil.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.cos.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.exp2.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.floor.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.fma.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll | 8 +- test/CodeGen/AMDGPU/llvm.log2.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.maxnum.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.minnum.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.rint.f16.ll | 6 +- test/CodeGen/AMDGPU/llvm.sin.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 4 +- test/CodeGen/AMDGPU/llvm.trunc.f16.ll | 4 +- test/CodeGen/AMDGPU/load-global-f32.ll | 10 +-- test/CodeGen/AMDGPU/load-global-f64.ll | 6 +- test/CodeGen/AMDGPU/load-global-i16.ll | 10 +-- test/CodeGen/AMDGPU/load-global-i32.ll | 8 +- test/CodeGen/AMDGPU/load-global-i64.ll | 10 +-- test/CodeGen/AMDGPU/load-global-i8.ll | 10 +-- test/CodeGen/AMDGPU/load-weird-sizes.ll | 10 +-- test/CodeGen/AMDGPU/max.ll | 4 +- test/CodeGen/AMDGPU/merge-stores.ll | 4 +- test/CodeGen/AMDGPU/mubuf.ll | 2 +- test/CodeGen/AMDGPU/mul.ll | 6 +- test/CodeGen/AMDGPU/no-shrink-extloads.ll | 2 +- test/CodeGen/AMDGPU/or.ll | 6 +- .../AMDGPU/promote-alloca-invariant-markers.ll | 2 +- test/CodeGen/AMDGPU/reduce-load-width-alignment.ll | 6 +- test/CodeGen/AMDGPU/reorder-stores.ll | 4 +- test/CodeGen/AMDGPU/rotl.i64.ll | 4 +- test/CodeGen/AMDGPU/rotr.i64.ll | 4 +- test/CodeGen/AMDGPU/rsq.ll | 4 +- test/CodeGen/AMDGPU/s_movk_i32.ll | 4 +- test/CodeGen/AMDGPU/saddo.ll | 6 +- test/CodeGen/AMDGPU/salu-to-valu.ll | 6 +- test/CodeGen/AMDGPU/scalar_to_vector.ll | 4 +- test/CodeGen/AMDGPU/schedule-global-loads.ll | 2 +- test/CodeGen/AMDGPU/scratch-buffer.ll | 4 +- test/CodeGen/AMDGPU/sdiv.ll | 6 +- test/CodeGen/AMDGPU/sdwa-peephole.ll | 6 +- test/CodeGen/AMDGPU/select-vectors.ll | 6 +- test/CodeGen/AMDGPU/select.f16.ll | 4 +- test/CodeGen/AMDGPU/sext-in-reg.ll | 8 +- test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll | 4 +- test/CodeGen/AMDGPU/sgpr-copy.ll | 4 +- test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll | 2 +- test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll | 2 +- test/CodeGen/AMDGPU/shift-i64-opts.ll | 4 +- test/CodeGen/AMDGPU/shl.ll | 4 +- test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll | 2 +- test/CodeGen/AMDGPU/sign_extend.ll | 4 +- test/CodeGen/AMDGPU/sitofp.f16.ll | 4 +- test/CodeGen/AMDGPU/sminmax.ll | 6 +- test/CodeGen/AMDGPU/sminmax.v2i16.ll | 6 +- test/CodeGen/AMDGPU/spill-cfg-position.ll | 2 +- test/CodeGen/AMDGPU/sra.ll | 6 +- test/CodeGen/AMDGPU/srem.ll | 6 +- test/CodeGen/AMDGPU/srl.ll | 4 +- test/CodeGen/AMDGPU/ssubo.ll | 6 +- test/CodeGen/AMDGPU/sub.ll | 4 +- test/CodeGen/AMDGPU/trunc-bitcast-vector.ll | 4 +- test/CodeGen/AMDGPU/trunc.ll | 6 +- test/CodeGen/AMDGPU/uaddo.ll | 6 +- test/CodeGen/AMDGPU/udiv.ll | 8 +- test/CodeGen/AMDGPU/uitofp.f16.ll | 4 +- test/CodeGen/AMDGPU/urem.ll | 6 +- test/CodeGen/AMDGPU/usubo.ll | 6 +- test/CodeGen/AMDGPU/v_mac.ll | 6 +- test/CodeGen/AMDGPU/v_mac_f16.ll | 4 +- test/CodeGen/AMDGPU/vectorize-global-local.ll | 2 +- test/CodeGen/AMDGPU/xor.ll | 6 +- 142 files changed, 790 insertions(+), 560 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 4 months

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Tcwg-commits July 2017