Tcwg-commits June 2017

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3431 discussions

[gcc] branch hjl/pr81217 created (now 40d0b53596c)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch hjl/pr81217 in repository gcc. at 40d0b53596c Fix 4-stage profiledbootstrap This branch includes the following new commits: new 40d0b53596c Fix 4-stage profiledbootstrap The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[clang] branch master updated (9e788cd10a -> f2468c5d9d)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 9e788cd10a When preprocessing with -frewrite-imports and -fmodule-file= [...] new f2468c5d9d Remove some redundant setup when preprocessing .pcm files. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Basic/SourceManager.cpp | 9 --------- lib/Frontend/FrontendAction.cpp | 1 - 2 files changed, 10 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[glibc] branch master updated (d54bb9b1d3 -> f819dbea0a)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from d54bb9b1d3 Prevent an implicit int promotion in malloc/tst-alloc_buffer.c new 4efe3ce400 powerpc64le: Check for compiler features for float128 new a27d2c1935 powerpc64le: Require at least POWER8 for powerpc64le new f819dbea0a powerpc64le: Enable float128 The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 36 ++ INSTALL | 5 + NEWS | 94 ++++ manual/install.texi | 4 + manual/math.texi | 3 +- sysdeps/powerpc/bits/floatn.h | 92 ++++ sysdeps/powerpc/fpu/libm-test-ulps | 578 +++++++++++++++++++++ sysdeps/powerpc/fpu/math_private.h | 10 + sysdeps/powerpc/powerpc64le/Implies-before | 1 + sysdeps/powerpc/powerpc64le/Makefile | 45 ++ sysdeps/powerpc/powerpc64le/configure | 75 +++ sysdeps/powerpc/powerpc64le/configure.ac | 48 ++ .../powerpc/powerpc64le/fpu/e_sqrtf128.c | 22 +- sysdeps/powerpc/powerpc64le/fpu/sfp-machine.h | 115 ++++ .../powerpc/powerpc64le/power9/fpu/e_sqrtf128.c | 27 +- .../sysv/linux/powerpc/powerpc64/libc-le.abilist | 7 + .../sysv/linux/powerpc/powerpc64/libm-le.abilist | 138 +++++ .../sysv/linux/powerpc/powerpc64le/float128-abi.h | 2 + 18 files changed, 1273 insertions(+), 29 deletions(-) create mode 100644 sysdeps/powerpc/bits/floatn.h create mode 100644 sysdeps/powerpc/powerpc64le/Implies-before create mode 100644 sysdeps/powerpc/powerpc64le/Makefile create mode 100644 sysdeps/powerpc/powerpc64le/configure create mode 100644 sysdeps/powerpc/powerpc64le/configure.ac copy soft-fp/sqrttf2.c => sysdeps/powerpc/powerpc64le/fpu/e_sqrtf128.c (81%) create mode 100644 sysdeps/powerpc/powerpc64le/fpu/sfp-machine.h copy soft-fp/fixhfti.c => sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c (77%) create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc64le/float128-abi.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[llvm] branch master updated (6649090b224 -> d2381bc76f0)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 6649090b224 AArch64: remove all kill flags when extending register liveness. new d2381bc76f0 [DWARF] NFC: Give DwarfFormat a 1-byte base type. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/BinaryFormat/Dwarf.h | 2 +- include/llvm/DebugInfo/DWARF/DWARFFormValue.h | 6 +++--- lib/DebugInfo/DWARF/DWARFFormValue.cpp | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[lld] branch master updated (fc3bbfcfe -> 497b15cbe)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from fc3bbfcfe Add trap instructions for ARM and MIPS. new 497b15cbe Fix -Wpessimizing-move. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: COFF/DriverUtils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[glibc] branch hjl/pr14995 updated (5a96b432be -> 92463eccb4)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch hjl/pr14995 in repository glibc. from 5a96b432be Support building glibc with gold 1.14 or above [BZ #14995] new cc28548b1e Run vismain only if linker supports protected data symbol new 92463eccb4 Check linker support for INSERT in linker script The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: config.make.in | 1 + configure | 33 +++++++++++++++++++++++++++++++++ configure.ac | 21 +++++++++++++++++++++ elf/Makefile | 2 ++ sysdeps/x86_64/Makefile | 2 ++ 5 files changed, 59 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[gcc] branch rsandifo/sve-rebase updated (5b4cc1776f3 -> 261da270156)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch rsandifo/sve-rebase in repository gcc. discards 5b4cc1776f3 Use conditional internal functions in if-conversion discards 231ad6081b6 Implement SLP of internal functions discards 3f0e0191212 Handle vector boolean types when calculating the SLP unroll factor discards 42c09e02c88 Remove unnecessary temporary in tree-if-conv.c discards 9459fcd9d50 Don't require an integer mode for PARALLELs discards 42de6c12f1b Add early rematerialisation pass discards 1d102ca4727 Record equivalences for spill registers discards 456a12b9380 Support fused multiply-adds in fully-masked reductions discards 58896e5b50e Replace FMA_EXPR with one internal fn per optab discards a7e11ea91b6 Use single-iteration epilogues when peeling for gaps discards 213f1294adc Allow single-element interleaving for non-power-of-2 strides discards 2b78f45beb3 Make tree-ssa-strlen.c handle partial unterminated strings discards c193e765edc Add support for first-faulting loads discards 4d4ff19f64f Add support for speculative loads discards 5d92e45c05b Support for aliasing with variable strides discards 765c55fc8b8 Fix for big field stores discards 5ac2211dbb5 Avoid pessimistic check for overlapping groups discards bab1a5e1e5a Add support for gather loads and scatter stores discards e3281a1b9b5 Add support for FADDA discards 9b4010e1304 Add support for CLASTB discards 7be36d32083 Add support for BRKA and LASTB discards e3a02277039 Allow capped vectorisation factors discards 9d2fca2e530 Reuse results of vect_create_addr_base_for_vector_ref discards adec056105a Add an empty_mask_is_expensive hook discards dac252557a4 Predicated arithmetic folds discards 022118c695b Predicated comparison folds discards 2c5d5405ffa SLP reductions with variable-length vectors discards b00acb2bd1a Allow combine to reorder statements discards 05a40262f14 Rework the legitimize_address_displacement hook discards 01ba1017671 Improve ivopts handling of offset multiples discards c4feca5ea41 Handle more SLP constant and extern definitions for variable VF discards 3589f213d07 Add optabs for common types of permutation discards ca28eb79390 Handle peeling for alignment with masking discards 355d8934f96 Allow the number of iterations to be smaller than VF discards 9114d45abe3 Make ivopts handle calls to internal functions discards d5ab9c7ee29 Add support for fully-predicated loops discards 71b41c785be Add support for bitwise reductions discards 7b4572047a8 Add support for masked load/store_lanes discards fcbf7b99b53 [AArch64] SVE load/store_lanes support discards dd03cc91692 Fix folding of vector mask EQ/NE expressions discards 4bc25f69d4d [AArch64] Testsuite markup for SVE discards b8fd5de83d7 [AArch64] Add SVE support discards 26ac9f1af7d Revert DECL_USER_ALIGN patch discards 3cffbeadc1a vect_masked_store discards e1671cd5ad6 vect_align_stack_vars discards 417b8e89c37 vect_variable_length discards 1849c19c85b target_vect_unaligned_possible discards d7523fa38e3 vect_element_align_preferred discards 0eda3d12b5e vect_permN discards d30eb455de7 available_vector_sizes discards f5187922eca Add VECTOR_BITS to tree-vect.h discards ff67a1b2094 Use asm volatile ("" ::: "memory") discards 204c415e0c3 Add copy_rtx call to RTL loop unroller discards 1c71de48343 [AArch64] Tighten address register subreg checks discards 37eb639398b [AArch64] Generate permute patterns using rtx builders discards 2deb65ad226 [AArch64] Rewrite aarch64_simd_valid_immediate discards 57f9e8068b2 [AArch64] Fix label mode discards 635d0fa1be8 [AArch64] Tweak aarch64_classify_address interface discards a3dd42cccae [AArch64] Add const_offset field to aarch64_address_info discards 498327fd12e [AArch64] Rename the internal "Upl" constraint discards 5e84c429ddc [AArch64] Rename cmp_result iterator discards 0a27b347f49 [AArch64] Remove use of wider vector modes discards 29c9d8f2f46 [AArch64] Set NUM_POLY_INT_COEFFS to 2 discards ef3485e6e0b [AArch64] Rework interface to add constant/offset routines discards ffc24ba4eee [AArch64] Move code around discards e6fd6567469 SUBREG_PROMOTED_VAR_P handling in expand_direct_optab_fn discards 6db0d25a7f8 Fix a failure in the Fortran matmul* tests discards 495271ac450 Improve ivopts handling of forced scales discards 0911cd7d4eb Improve vector mask pattern handling discards 6ede44cbe60 Improve canonicalisation of TARGET_MEM_REFs discards 30aacebe296 Prevent invalid register mode changes in combine discards 9e975a5a6d4 Fix infinite loop in simplify_operand_subreg discards 1492bb0ceab Use extract_bit_field_as_subreg for vectors discards 48b505c82fa Fix vectorizable_live_operation handling of vector booleans discards 01f7bc66f82 Allow the target to set MAX_BITSIZE_MODE_ANY_MODE discards 03575106827 Add support for adjusting the number of units in a mode discards 53a3fcf568c Add support for MODE_VECTOR_BOOL discards 2d93c2074d9 Improve spilling for variable-width slots discards ba0037bd728 Don't query the frontend for unsupported types discards 0fad5656c1e Make more use of simplify_gen_binary discards 6540dd20bc6 Use poly_int rtx accessors instead of hwi accessors discards b5e6c63aa05 Use poly_int tree accessors instead of hwi accessors discards 9c4477db868 Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS [...] discards bae3890ae5e poly_int: GET_MODE_SIZE discards f6f4bedfd02 poly_int: GET_MODE_BITSIZE discards b4267938646 poly_int: GET_MODE_PRECISION discards 4bd85055c37 poly_int: TYPE_VECTOR_SUBPARTS discards 88f3c042395 poly_int: GET_MODE_NUNITS discards 824fcb9e2de poly_int: vect_no_alias_p discards 9bf48826fc9 poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECT [...] discards c9ba9673b0b poly_int: get_mask_mode discards 9e791265b87 poly_int: omp_max_vf discards a493d26cad3 poly_int: vectoriser vf and uf discards c733d2d6fa1 poly_int: tree-ssa-loop-ivopts.c:iv_use discards 167301dbf6f poly_int: get_binfo_at_offset discards 9a81fa4e0ee poly_int: build_ref_for_offset discards 2c8d1307522 poly_int: MEM_REF offsets discards da7004e6444 poly_int: bit_field_size/offset discards 3c4b9f6aeed poly_int: int_size_in_bytes discards 40dbc27796f poly_int: emit_group_load/store discards 85499c61e35 poly_int: reload<->ira interface discards 87c64cbc7aa poly_int: emit_inc discards 9fca576bdd2 poly_int: cfgexpand stack variables discards 00ae0b44f64 poly_int: argument sizes discards 8c542123528 poly_int: REG_ARGS_SIZE discards 15bb511e775 poly_int: push_block/emit_push_insn discards e2c537cffc1 poly_int: frame allocations discards 29eb45fe30e poly_int: reload1.c discards 3d8028db8c7 poly_int: reload.c discards 234c565d5ba poly_int: get_inner_reference & co. discards 11cb22206f0 poly_int: get_inner_reference_aff discards 8a70343b4e1 poly_int: pointer_may_wrap_p discards 0ce73623d71 poly_int: symbolic_number discards 6bb398048ec poly_int: aff_tree discards b1abb145fa7 poly_int: get_addr_unit_base_and_extent discards c108ce200fd poly_int: get_ref_base_and_extent discards 2a3fcfab57a poly_int: ipa_parm_adjustment discards de20cba09ff poly_int: DWARF CFA offsets discards cf4593b2609 poly_int: operand_subword discards dbe9a01480d poly_int: SUBREG_BYTE discards 8437389ea2e poly_int: store_field & co discards 20efca25850 poly_int: C++ bitfield regions discards a58d2f800fc poly_int: extract_bit_field bitrange discards cb92e04c06b poly_int: store_bit_field bitrange discards 2c1628d84f2 poly_int: lra frame offsets discards ba9da4c2e26 poly_int: MEM_OFFSET and MEM_SIZE discards fe60542cc03 poly_int: rtx_addr_can_trap_p_1 discards 7987bc09dad poly_int: dse.c discards 7e302542844 poly_int: ao_ref and vn_reference_op_t discards 3e2c2d16265 poly_int: same_addr_size_stores_p discards 8ec9da5287f poly_int: fold_ctor_reference discards 265b7cb0d44 Add DWARF support for polynomial offsets discards 8070258d448 Make REG_OFFSET a poly_int64 discards 20292972199 poly_int: compute_data_ref_aligment discards 83fe1bb8b50 Add poly_int dump routines discards ca36f7f92bd Add polynomial tree constants discards 7be8081c17f Add polynomial rtx constants discards 37f497895e3 Make mode query functions accept poly_ints discards f4066f5482b Add poly-int.h new f459b81e866 Move computation of SLP_TREE_NUMBER_OF_VEC_STMTS new 74127961097 Add poly-int.h new 0cb2c724948 Make mode query functions accept poly_ints new edc1f2de919 Add polynomial rtx constants new 7d03a1ca628 Add polynomial tree constants new 08eecf285f6 Add poly_int dump routines new 606a7722304 poly_int: compute_data_ref_aligment new 71f5e95e6e1 Make REG_OFFSET a poly_int64 new be19fd9bbea Add DWARF support for polynomial offsets new 294b78e3747 poly_int: fold_ctor_reference new d52289dfd81 poly_int: same_addr_size_stores_p new fd34fb35ea5 poly_int: ao_ref and vn_reference_op_t new e1e4aa6d59e poly_int: dse.c new 68c2b0670e0 poly_int: rtx_addr_can_trap_p_1 new 07f2a7bd4dd poly_int: MEM_OFFSET and MEM_SIZE new d540c359c0a poly_int: lra frame offsets new fe9ad011150 poly_int: store_bit_field bitrange new 96b87c3a7d5 poly_int: extract_bit_field bitrange new 7f3f90667ce poly_int: C++ bitfield regions new 841f722058a poly_int: store_field & co new 99c7d427ee4 poly_int: SUBREG_BYTE new c1c73db9269 poly_int: operand_subword new aa504a9defb poly_int: DWARF CFA offsets new a5f94ef2959 poly_int: ipa_parm_adjustment new 5e01c1a7218 poly_int: get_ref_base_and_extent new 69de1b234ac poly_int: get_addr_unit_base_and_extent new b727b27fd91 poly_int: aff_tree new 4e8094406ad poly_int: symbolic_number new bd04a091529 poly_int: pointer_may_wrap_p new 74b50226282 poly_int: get_inner_reference_aff new e3d7fddf676 poly_int: get_inner_reference & co. new 0baac1d51bb poly_int: reload.c new 29f2609006b poly_int: reload1.c new 04619b24af1 poly_int: frame allocations new 300f236f5c9 poly_int: push_block/emit_push_insn new 0dc1180fc67 poly_int: REG_ARGS_SIZE new 159c8f88ee6 poly_int: argument sizes new 5d4a3af0916 poly_int: cfgexpand stack variables new 71e08defee4 poly_int: emit_inc new c04ad098d85 poly_int: reload<->ira interface new 390d35024a0 poly_int: emit_group_load/store new 390335cdd36 poly_int: int_size_in_bytes new d6b3f8ff139 poly_int: bit_field_size/offset new 3593fdd32d5 poly_int: MEM_REF offsets new d48f2402d3c poly_int: build_ref_for_offset new 9e37d99e6c5 poly_int: get_binfo_at_offset new cfcc28661c5 poly_int: tree-ssa-loop-ivopts.c:iv_use new 9370f9eb87e poly_int: vectoriser vf and uf new a35d12646d1 poly_int: omp_max_vf new e7b38f8fcb6 poly_int: get_mask_mode new bd56f880f29 poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECT [...] new 6ec2f65d030 poly_int: vect_no_alias_p new 414be8bc253 poly_int: GET_MODE_NUNITS new 07422179fed poly_int: TYPE_VECTOR_SUBPARTS new 9612b044119 Fix vectorizable_live_operation handling of vector booleans new 834f633f4f5 poly_int: GET_MODE_PRECISION new a3debea1bb5 poly_int: GET_MODE_BITSIZE new ab4a8fbb6de poly_int: GET_MODE_SIZE new bb53becdade Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS [...] new 1a5974ae2ef Use poly_int tree accessors instead of hwi accessors new 00a16c83c2d Use poly_int rtx accessors instead of hwi accessors new a232ef45122 Make more use of simplify_gen_binary new 0b92cb7a4a5 Don't query the frontend for unsupported types new 2d435f77229 Improve spilling for variable-width slots new bc768e40990 Add support for MODE_VECTOR_BOOL new 45d5a5db6e7 Add support for adjusting the number of units in a mode new af0d10f9462 Allow the target to set MAX_BITSIZE_MODE_ANY_MODE new cb5940bd7c5 Use extract_bit_field_as_subreg for vectors new bbb44532472 Fix infinite loop in simplify_operand_subreg new a1951348311 Prevent invalid register mode changes in combine new 048705dd6d5 Improve canonicalisation of TARGET_MEM_REFs new 000799d1beb Improve vector mask pattern handling new 70c6d5fd04d Improve ivopts handling of forced scales new 2daafb32003 Fix a failure in the Fortran matmul* tests new e8a397ab209 SUBREG_PROMOTED_VAR_P handling in expand_direct_optab_fn new 02263d13aff [AArch64] Move code around new 64ca59a40d5 [AArch64] Rework interface to add constant/offset routines new ac71e25258c [AArch64] Set NUM_POLY_INT_COEFFS to 2 new eceec5dfc5b [AArch64] Remove use of wider vector modes new d7560eaa0cb [AArch64] Rename cmp_result iterator new fb050c8c326 [AArch64] Rename the internal "Upl" constraint new b916f361b39 [AArch64] Add const_offset field to aarch64_address_info new 78ee462325d [AArch64] Tweak aarch64_classify_address interface new e330129a4ff [AArch64] Fix label mode new d946a4886cd [AArch64] Rewrite aarch64_simd_valid_immediate new 43b077a46a0 [AArch64] Generate permute patterns using rtx builders new e3fc1e5988c [AArch64] Tighten address register subreg checks new bbd535f546f Add copy_rtx call to RTL loop unroller new e2d94f29a4e Use asm volatile ("" ::: "memory") new f8bedd3724c Add VECTOR_BITS to tree-vect.h new 8c014f90142 available_vector_sizes new d4971658249 vect_permN new e3f20f28d8b vect_element_align_preferred new 181e21aba4a target_vect_unaligned_possible new 1a47211b963 vect_variable_length new 129e8cd807b vect_align_stack_vars new 09c4f4f5bd1 vect_masked_store new 079c0e9d9a0 Revert DECL_USER_ALIGN patch new f4e4dee39be [AArch64] Add SVE support new 8fd85315e02 [AArch64] Testsuite markup for SVE new 65a3c48e1c6 Fix folding of vector mask EQ/NE expressions new 9bd76a572f9 [AArch64] SVE load/store_lanes support new da1a711474b Add support for masked load/store_lanes new 0f0e0e42d0b Add support for bitwise reductions new 05eb779dcaf Add optabs for common types of permutation new 302a01c35df Handle more SLP constant and extern definitions for variable VF new 88d8dc05fdb SLP reductions with variable-length vectors new 45ecaa68b03 Protect against min_profitable_iters going negative new 36ad0e7384d Add support for fully-predicated loops new fc1e283b04a Improve VIEW_CONVERT_EXPR for vector booleans new e5b3bf19f92 Make ivopts handle calls to internal functions new 6f3633d4335 Allow the number of iterations to be smaller than VF new 2b31db63b4a Handle peeling for alignment with masking new 123c1bc93cd Improve ivopts handling of offset multiples new 5be83218f8f Rework the legitimize_address_displacement hook new ce305ab248d Allow combine to reorder statements new 5289982d1fd Predicated comparison folds new d93c9a5d709 Predicated arithmetic folds new babf88b6b56 Add an empty_mask_is_expensive hook new 81acb616fe2 Reuse results of vect_create_addr_base_for_vector_ref new 261f6844c66 Allow capped vectorisation factors new 882abc052b9 Add support for BRKA and LASTB new b1b95b7d468 Add support for CLASTB new da182e7510d Add support for FADDA new 5fd014a6c19 Add support for gather loads and scatter stores new e04990467bd Avoid pessimistic check for overlapping groups new d3644930ab0 Fix for big field stores new 4fe1d36102a Support for aliasing with variable strides new 95aa282a338 Add support for speculative loads new 664c10f5e2b Add support for first-faulting loads new 21215c96b33 Make tree-ssa-strlen.c handle partial unterminated strings new 241eebc89da Allow single-element interleaving for non-power-of-2 strides new 42199b1b2b9 Use single-iteration epilogues when peeling for gaps new f669471ab1e Replace FMA_EXPR with one internal fn per optab new e848c756818 Support fused multiply-adds in fully-masked reductions new 898062cc398 Record equivalences for spill registers new a3fe7f879f5 Add early rematerialisation pass new d6c69f5e526 Don't require an integer mode for PARALLELs new 034b757dc91 Remove unnecessary temporary in tree-if-conv.c new 26e573140eb Handle vector boolean types when calculating the SLP unroll factor new eb42b4335e3 Implement SLP of internal functions new 261da270156 Use conditional internal functions in if-conversion This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5b4cc1776f3) \ N -- N -- N refs/heads/rsandifo/sve-rebase (261da270156) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 142 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-sve.md | 16 + gcc/config/aarch64/aarch64.md | 13 +- gcc/expr.c | 7 +- gcc/poly-int.h | 97 +-- gcc/testsuite/gcc.dg/vect/pr53773.c | 3 +- gcc/testsuite/gcc.dg/vect/slp-28.c | 3 +- gcc/testsuite/gcc.dg/vect/slp-3.c | 6 +- .../gcc.target/aarch64/sve_cant_predicate_1.c | 45 -- gcc/testsuite/gcc.target/aarch64/sve_cap_2.c | 16 +- .../gcc.target/aarch64/sve_gather_load_2.c | 5 +- .../gcc.target/aarch64/sve_mask_gather_load_2.c | 6 +- gcc/testsuite/gcc.target/aarch64/sve_slp_1.c | 18 + gcc/testsuite/gcc.target/aarch64/sve_slp_10.c | 58 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_10_run.c | 54 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_11.c | 52 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_11_run.c | 45 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_12.c | 60 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_12_run.c | 53 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_13.c | 57 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_13_run.c | 28 + gcc/testsuite/gcc.target/aarch64/sve_slp_14.c | 47 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_14_run.c | 34 + gcc/testsuite/gcc.target/aarch64/sve_slp_2.c | 18 + gcc/testsuite/gcc.target/aarch64/sve_slp_3.c | 20 + gcc/testsuite/gcc.target/aarch64/sve_slp_4.c | 22 + gcc/testsuite/gcc.target/aarch64/sve_slp_5.c | 8 + gcc/testsuite/gcc.target/aarch64/sve_slp_6.c | 2 + gcc/testsuite/gcc.target/aarch64/sve_slp_7.c | 8 + gcc/testsuite/gcc.target/aarch64/sve_slp_8.c | 62 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_8_run.c | 44 + gcc/testsuite/gcc.target/aarch64/sve_slp_9.c | 52 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_9_run.c | 39 + gcc/tree-vect-data-refs.c | 8 +- gcc/tree-vect-loop-manip.c | 895 ++++++++++++++++----- gcc/tree-vect-loop.c | 738 ++++++++++------- gcc/tree-vect-slp.c | 112 +-- gcc/tree-vect-stmts.c | 460 ++++++----- gcc/tree-vectorizer.h | 210 +++-- 38 files changed, 2479 insertions(+), 942 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cant_predicate_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_10.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_10_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_11.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_11_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_12.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_12_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_13.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_13_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_14.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_14_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_8_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_9.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_9_run.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[lld] branch master updated (8ab7328a2 -> fc3bbfcfe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 8ab7328a2 Tweak to match change in LLVM API, in r306315. new fc3bbfcfe Add trap instructions for ARM and MIPS. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/Arch/ARM.cpp | 1 + ELF/Arch/Mips.cpp | 1 + ELF/Arch/X86.cpp | 4 +- ELF/Arch/X86_64.cpp | 4 +- test/ELF/arm-gnu-ifunc-plt.s | 6 +- test/ELF/arm-thumb-branch.s | 2 +- test/ELF/arm-thumb-plt-reloc.s | 4 +- test/ELF/mips-got16-relocatable.s | 8 +- test/ELF/mips-npic-call-pic-os.s | 32 +++---- test/ELF/mips-npic-call-pic-script.s | 170 +++++++++++++++++------------------ test/ELF/mips-npic-call-pic.s | 32 +++---- 11 files changed, 131 insertions(+), 133 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[gcc] branch linaro-dev/sve updated (d5754a616af -> abd13a68ea4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch linaro-dev/sve in repository gcc. from d5754a616af Fix a test failure in gcc.target/aarch64/sve_mask_struct_store_3.c new aacf22100d3 Relax can_div_trunc_p new c4306a1d92a Fix known_alignment new 65bf0f38b90 Move computation of SLP_TREE_NUMBER_OF_VEC_STMTS new a0304d5c07c Add support for masked grouped operations new 1cf65fdc604 Use UQDEC for constants too new 59d4ad32b57 Improve VIEW_CONVERT_EXPR for vector booleans new fc9c776ba32 Remove LOOP_VINFO_SUNK_DATAREFS new abd13a68ea4 Revert spurious whitespace change The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-sve.md | 16 + gcc/config/aarch64/aarch64.md | 13 +- gcc/expr.c | 7 +- gcc/poly-int.h | 97 +-- gcc/testsuite/gcc.dg/vect/pr53773.c | 3 +- gcc/testsuite/gcc.dg/vect/slp-28.c | 3 +- gcc/testsuite/gcc.dg/vect/slp-3.c | 6 +- .../gcc.target/aarch64/sve_cant_predicate_1.c | 45 -- gcc/testsuite/gcc.target/aarch64/sve_cap_2.c | 16 +- .../gcc.target/aarch64/sve_gather_load_2.c | 5 +- .../gcc.target/aarch64/sve_mask_gather_load_2.c | 6 +- gcc/testsuite/gcc.target/aarch64/sve_slp_1.c | 18 + gcc/testsuite/gcc.target/aarch64/sve_slp_10.c | 58 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_10_run.c | 54 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_11.c | 52 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_11_run.c | 45 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_12.c | 60 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_12_run.c | 53 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_13.c | 57 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_13_run.c | 28 + gcc/testsuite/gcc.target/aarch64/sve_slp_14.c | 47 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_14_run.c | 34 + gcc/testsuite/gcc.target/aarch64/sve_slp_2.c | 18 + gcc/testsuite/gcc.target/aarch64/sve_slp_3.c | 20 + gcc/testsuite/gcc.target/aarch64/sve_slp_4.c | 22 + gcc/testsuite/gcc.target/aarch64/sve_slp_5.c | 8 + gcc/testsuite/gcc.target/aarch64/sve_slp_6.c | 2 + gcc/testsuite/gcc.target/aarch64/sve_slp_7.c | 8 + gcc/testsuite/gcc.target/aarch64/sve_slp_8.c | 62 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_8_run.c | 44 + gcc/testsuite/gcc.target/aarch64/sve_slp_9.c | 52 ++ gcc/testsuite/gcc.target/aarch64/sve_slp_9_run.c | 39 + gcc/tree-vect-data-refs.c | 8 +- gcc/tree-vect-loop-manip.c | 895 ++++++++++++++++----- gcc/tree-vect-loop.c | 738 ++++++++++------- gcc/tree-vect-slp.c | 112 +-- gcc/tree-vect-stmts.c | 460 ++++++----- gcc/tree-vectorizer.h | 210 +++-- 38 files changed, 2479 insertions(+), 942 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cant_predicate_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_10.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_10_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_11.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_11_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_12.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_12_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_13.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_13_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_14.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_14_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_8_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_9.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_slp_9_run.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[clang] branch master updated (b6301cec3e -> 9e788cd10a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from b6301cec3e [Sema] Fix a crash-on-invalid when a template parameter list [...] new 9e788cd10a When preprocessing with -frewrite-imports and -fmodule-file= [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Frontend/Rewrite/FrontendActions.cpp | 2 ++ test/Modules/Inputs/preprocess/file.h | 6 ++++ test/Modules/Inputs/preprocess/fwd.h | 1 + test/Modules/Inputs/preprocess/module.modulemap | 2 +- test/Modules/Inputs/preprocess/other.h | 1 + test/Modules/preprocess-module.cpp | 44 ++++++++++++++++--------- 6 files changed, 40 insertions(+), 16 deletions(-) create mode 100644 test/Modules/Inputs/preprocess/other.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

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Tcwg-commits June 2017