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unknown user pushed a change to branch master
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from 699416df0f3 GlobalISel: add G_IMPLICIT_DEF instruction.
new 75d5833bd6e [SystemZ] Add all remaining instructions
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Summary of changes:
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp | 16 +-
.../SystemZ/Disassembler/SystemZDisassembler.cpp | 6 +
.../SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp | 7 +
.../SystemZ/MCTargetDesc/SystemZMCTargetDesc.h | 1 +
lib/Target/SystemZ/SystemZ.td | 1 +
lib/Target/SystemZ/SystemZFeatures.td | 22 +-
lib/Target/SystemZ/SystemZInstrFormats.td | 106 ++
lib/Target/SystemZ/SystemZInstrInfo.td | 42 -
lib/Target/SystemZ/SystemZInstrSystem.td | 517 ++++++
lib/Target/SystemZ/SystemZRegisterInfo.td | 10 +
lib/Target/SystemZ/SystemZScheduleZ13.td | 186 +-
lib/Target/SystemZ/SystemZScheduleZ196.td | 183 +-
lib/Target/SystemZ/SystemZScheduleZEC12.td | 184 +-
lib/Target/SystemZ/SystemZSubtarget.cpp | 5 +-
lib/Target/SystemZ/SystemZSubtarget.h | 15 +
test/MC/Disassembler/SystemZ/insns.txt | 1873 +++++++++++++++++++-
test/MC/SystemZ/insn-bad-z196.s | 5 +
test/MC/SystemZ/insn-bad-zEC12.s | 14 +
test/MC/SystemZ/insn-bad.s | 780 ++++++++
test/MC/SystemZ/insn-good-z196.s | 16 +
test/MC/SystemZ/insn-good-zEC12.s | 14 +
test/MC/SystemZ/insn-good.s | 1411 +++++++++++++++
test/MC/SystemZ/regs-bad.s | 63 +-
test/MC/SystemZ/regs-good.s | 51 +
24 files changed, 5367 insertions(+), 161 deletions(-)
create mode 100644 lib/Target/SystemZ/SystemZInstrSystem.td
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unknown user pushed a change to branch master
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from b423f98bea6 * config-lang.in (gtfiles): Add cp/lex.c. * cp-tree.h (ma [...]
new 483d5f69d7d 2017-06-30 Andrew Pinski <apinski(a)cavium.com>
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Summary of changes:
gcc/ChangeLog | 5 +++++
gcc/testsuite/ChangeLog | 4 ++++
gcc/testsuite/gcc.dg/torture/pr81245.c | 16 ++++++++++++++++
gcc/tree-if-conv.c | 7 +++++--
4 files changed, 30 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/torture/pr81245.c
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unknown user pushed a change to branch master
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from 409c609253e Revert "[Hexagon] Guard the generation of lookup table"
new 7005a5a0471 [Hexagon] Emit jump tables in text section based on a flag
new 699416df0f3 GlobalISel: add G_IMPLICIT_DEF instruction.
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Summary of changes:
include/llvm/Target/GenericOpcodes.td | 6 +++
include/llvm/Target/TargetOpcodes.def | 2 +
lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 14 ++++++
lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 2 +
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 2 +-
lib/Target/AArch64/AArch64LegalizerInfo.cpp | 3 ++
lib/Target/Hexagon/HexagonTargetObjectFile.cpp | 9 ++++
lib/Target/Hexagon/HexagonTargetObjectFile.h | 3 ++
test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 19 +++++++-
.../AArch64/GlobalISel/arm64-irtranslator.ll | 26 +++++-----
test/CodeGen/AArch64/GlobalISel/call-translator.ll | 2 +-
.../AArch64/GlobalISel/irtranslator-exceptions.ll | 2 +-
test/CodeGen/AArch64/GlobalISel/legalize-undef.mir | 15 ++++++
test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 10 ++--
test/CodeGen/Hexagon/jt-in-text.ll | 57 ++++++++++++++++++++++
15 files changed, 149 insertions(+), 23 deletions(-)
create mode 100644 test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
create mode 100644 test/CodeGen/Hexagon/jt-in-text.ll
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unknown user pushed a change to branch master
in repository clang.
from fcf6e44da0 clang-format: Do not binpack initialization lists
new 1e786d52fd [clang-rename] Just return instead of calling exit(3) from main.
new 0ce8b803dc clang-format: add options to merge empty record body
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include/clang/Format/Format.h | 24 ++++-
lib/Format/Format.cpp | 16 ++-
lib/Format/FormatToken.h | 13 +++
lib/Format/UnwrappedLineFormatter.cpp | 28 +++++-
tools/clang-rename/ClangRename.cpp | 19 ++--
unittests/Format/FormatTest.cpp | 180 +++++++++++++++++++++++++++++++++-
6 files changed, 256 insertions(+), 24 deletions(-)
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unknown user pushed a change to branch master
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from ecea903af0b [SimplifyCFG] Update the name of switch generated lookup table.
new ae521f4192c [Hexagon] Guard the generation of lookup table
new 409c609253e Revert "[Hexagon] Guard the generation of lookup table"
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unknown user pushed a change to branch master
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from 1c35de7 Moved builders clang-with-lto-ubuntu, clang-with-thin-lto-ubu [...]
new 9f7415c [asan] Fix API check for x86 devices
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zorg/buildbot/builders/sanitizers/buildbot_android.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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from f0dc005cf08 Make 0 argument getSubtargetImpl functions for the X86, AAr [...]
new a8b6c543a8f ARM: fix big-endian 64-bit cmpxchg.
new a6974a4e446 [ORE] Remove old "diagnostic hotness" spelling
new ecea903af0b [SimplifyCFG] Update the name of switch generated lookup table.
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Summary of changes:
include/llvm/IR/LLVMContext.h | 9 ------
lib/IR/LLVMContext.cpp | 7 -----
lib/Target/ARM/ARMISelLowering.cpp | 15 +++++++---
lib/Transforms/Utils/SimplifyCFG.cpp | 10 ++++---
test/CodeGen/ARM/cmpxchg-O0-be.ll | 26 ++++++++++++++++++
.../SimplifyCFG/X86/switch-covered-bug.ll | 2 +-
.../Transforms/SimplifyCFG/X86/switch-table-bug.ll | 2 +-
.../SimplifyCFG/X86/switch_to_lookup_table.ll | 32 +++++++++++-----------
8 files changed, 61 insertions(+), 42 deletions(-)
create mode 100644 test/CodeGen/ARM/cmpxchg-O0-be.ll
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unknown user pushed a change to branch master
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from 77c1cc560f [ORE] Use LLVM's "diagnostics hotness" spelling
new fcf6e44da0 clang-format: Do not binpack initialization lists
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lib/Format/ContinuationIndenter.cpp | 4 ++--
unittests/Format/FormatTest.cpp | 24 ++++++++++++++++++++----
unittests/Format/FormatTestJava.cpp | 5 ++++-
3 files changed, 26 insertions(+), 7 deletions(-)
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from 9a170a630e1 [PowerPC] auto-generate check lines; NFC
new f0dc005cf08 Make 0 argument getSubtargetImpl functions for the X86, AAr [...]
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lib/Target/AArch64/AArch64TargetMachine.h | 1 +
lib/Target/PowerPC/PPCTargetMachine.h | 1 +
lib/Target/X86/X86TargetMachine.h | 1 +
3 files changed, 3 insertions(+)
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from 912945a78d [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs.
new 77c1cc560f [ORE] Use LLVM's "diagnostics hotness" spelling
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lib/CodeGen/CodeGenAction.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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