Tcwg-commits June 2017

tcwg-commits@lists.linaro.org

8 participants
3431 discussions

[glibc] branch hjl/tunables/master updated (e935e64770 -> 70e39a058e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch hjl/tunables/master in repository glibc. discards e935e64770 Add TUNABLES to control IFUNC selection and cache sizes discards 9f8e103a6c ld.so: Consolidate 2 strtouls into _dl_strtoul adds 199fc19d3a Remove __need macros from stdio.h and wchar.h. new 37b66c0b1a ld.so: Consolidate 2 strtouls into _dl_strtoul [BZ #21528] new 70e39a058e Add TUNABLES to control IFUNC selection and cache sizes This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e935e64770) \ N -- N -- N refs/heads/hjl/tunables/master (70e39a058e) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 38 +++++++ grp/grp.h | 3 +- gshadow/gshadow.h | 4 +- hurd/hurd.h | 3 +- iconv/gconv.h | 6 +- include/bits/types/FILE.h | 1 + include/bits/types/__FILE.h | 1 + include/bits/types/__mbstate_t.h | 1 + include/bits/types/mbstate_t.h | 1 + include/bits/types/wint_t.h | 1 + include/bits/wctype-wchar.h | 1 + include/stdio.h | 16 ++- include/wchar.h | 10 +- include/wctype.h | 29 +---- libio/Makefile | 3 +- libio/bits/types/FILE.h | 9 ++ libio/bits/types/__FILE.h | 7 ++ libio/stdio.h | 47 ++------- mach/mach.h | 6 +- misc/mntent.h | 4 +- pwd/pwd.h | 3 +- shadow/shadow.h | 4 +- stdio-common/printf.h | 5 +- sysdeps/generic/_G_config.h | 7 +- sysdeps/unix/sysv/linux/_G_config.h | 7 +- sysdeps/x86/cpu-features.h | 1 - wcsmbs/Makefile | 3 +- wcsmbs/bits/types/__mbstate_t.h | 23 ++++ wcsmbs/bits/types/mbstate_t.h | 8 ++ wcsmbs/bits/types/wint_t.h | 23 ++++ wcsmbs/uchar.h | 9 +- wcsmbs/wchar.h | 119 +++++---------------- wctype/Makefile | 2 +- wctype/{wctype.h => bits/wctype-wchar.h} | 152 ++------------------------- wctype/wctype.h | 175 ++----------------------------- 35 files changed, 207 insertions(+), 525 deletions(-) create mode 100644 include/bits/types/FILE.h create mode 100644 include/bits/types/__FILE.h create mode 100644 include/bits/types/__mbstate_t.h create mode 100644 include/bits/types/mbstate_t.h create mode 100644 include/bits/types/wint_t.h create mode 100644 include/bits/wctype-wchar.h create mode 100644 libio/bits/types/FILE.h create mode 100644 libio/bits/types/__FILE.h create mode 100644 wcsmbs/bits/types/__mbstate_t.h create mode 100644 wcsmbs/bits/types/mbstate_t.h create mode 100644 wcsmbs/bits/types/wint_t.h copy wctype/{wctype.h => bits/wctype-wchar.h} (53%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[llvm] branch master updated (b45962cb215 -> 4c04c2d0722)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from b45962cb215 AMDGPU: Work around build special casing .inc files new 4c04c2d0722 [CGP] don't expand a memcmp with nobuiltin attribute The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/Analysis/TargetLibraryInfo.h | 8 ++++++++ lib/CodeGen/CodeGenPrepare.cpp | 10 ++++------ .../PowerPC/memCmpUsedInZeroEqualityComparison.ll | 21 +++++++++++++++------ 3 files changed, 27 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[lld] branch master updated (3372b8f0e -> e70efb814)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 3372b8f0e Move fabricateDefaultCommands earlier. new e70efb814 Fix a bug in output section directive. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/ScriptParser.cpp | 47 ++++++++++++++++++++++++++++-------------- test/ELF/linkerscript/noload.s | 2 +- 2 files changed, 33 insertions(+), 16 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[glibc] branch hjl/tunables/master updated (e5c2103926 -> e935e64770)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch hjl/tunables/master in repository glibc. discards e5c2103926 Add TUNABLES to control IFUNC selection and cache sizes new e935e64770 Add TUNABLES to control IFUNC selection and cache sizes This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e5c2103926) \ N -- N -- N refs/heads/hjl/tunables/master (e935e64770) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sysdeps/x86/cpu-features.c | 10 ++++------ sysdeps/x86/cpu-features.h | 4 ++++ sysdeps/x86/cpu-tunables.c | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[gcc] branch gcc-7-branch updated (3713017e72b -> a98ddbd66a1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-7-branch in repository gcc. from 3713017e72b PR c/81006 * c-typeck.c (handle_omp_array_sections_1): Co [...] new a98ddbd66a1 PR target/81015 Revert: 2016-12-14 Uros Bizjak <ubizja [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 100 ++++++++++++++++-------------- gcc/config/i386/i386.md | 36 ----------- gcc/testsuite/ChangeLog | 33 ++++++---- gcc/testsuite/gcc.target/i386/pr59874-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr59874-2.c | 2 +- gcc/testsuite/gcc.target/i386/pr81015.c | 21 +++++++ 6 files changed, 98 insertions(+), 96 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr81015.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[gcc] branch gcc-5-branch updated (92d11d97bc9 -> 25e9a8a8601)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gcc-5-branch in repository gcc. from 92d11d97bc9 Daily bump. new 25e9a8a8601 PR c/81006 * c-typeck.c (handle_omp_array_sections_1): Co [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/c/ChangeLog | 6 ++++++ gcc/c/c-typeck.c | 6 +++--- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/semantics.c | 6 +++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/c-c++-common/gomp/pr81006.c | 10 ++++++++++ 6 files changed, 33 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/gomp/pr81006.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[llvm] branch master updated (271bf6ebf9d -> b45962cb215)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 271bf6ebf9d AMDGPU: Use correct register names in inline assembly new b45962cb215 AMDGPU: Work around build special casing .inc files The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../AMDGPU/{AMDGPURegAsmNames.inc => AMDGPURegAsmNames.inc.cpp} | 4 ++++ lib/Target/AMDGPU/CMakeLists.txt | 1 + lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) rename lib/Target/AMDGPU/{AMDGPURegAsmNames.inc => AMDGPURegAsmNames.inc.cpp} (99%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[glibc] branch hjl/tunables/master updated (9506057c4b -> e5c2103926)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch hjl/tunables/master in repository glibc. discards 9506057c4b Add TUNABLES to control IFUNC selection and cache sizes discards 672d7f0576 x86: Don't use dl_x86_cpu_features in cacheinfo.c adds 6b69f98dcd benchtests: Add more tests for memrchr adds 8951dd0b14 Regenerate sysdeps/gnu/errlist.c. adds 7553131847 Fix struct sigaltstack namespace (bug 21517). adds c4c96f92f7 Define SIG_HOLD for XPG4 (bug 21538). adds d8a7d10324 x86-64: Update LO_HI_LONG for p{readv,writev}{64}v2 adds 7395928b95 x86_64: Remove redundant REX bytes from memrchr.S adds 30cb625a21 x86-64: Update strlen.S to support wcslen/wcsnlen adds 9cd30491dd x86: Add macros to implement ifunce selection in C adds ef9c4cb6c7 x86-64: Optimize wmemset with SSE2/AVX2/AVX512 adds 935971ba6b x86-64: Optimize memcmp/wmemcmp with AVX2 and MOVBE adds 48e7bc7a55 x86: Don't use dl_x86_cpu_features in cacheinfo.c adds 12d2dd7060 Optimize generic spinlock code and use C11 like atomic macros. adds 4bf7abaeb3 S390: Use generic spinlock code. adds d4cc385c6e x86-64: Move wcsnlen.S to multiarch/wcsnlen-sse4_1.S adds 44330b6d32 tunables: Clean up hooks to get and set tunables adds ea9b0ecbf0 tunables: Add LD_HWCAP_MASK to tunables adds 6482e63403 Add include guards to dl-procinfo.h adds ff08fc59e3 tunables: Use glibc.tune.hwcap_mask tunable instead of _dl_h [...] adds f82e9672ad aarch64: Allow overriding HWCAP_CPUID feature check using HW [...] adds 511c5a1087 Make LD_HWCAP_MASK usable for static binaries adds ea01a4da21 aarch64: Add hwcap string routines adds fdc543919a Use test-driver in sysdeps/unix/sysv/linux/tst-clone2.c adds 8f0a947cf5 Remove check for NULL buffer passed to `ptsname_r' adds 2e87c7d158 x86-64: Fold ifunc-sse4_1.h into wcsnlen.c adds bd6193907a Fix tst-timezone race (bug 14096). adds 81df4d253d Fix include paths in include/bits/types/*.h. adds 82c19bdfe3 float128: Extend the power of ten tables adds 32bf1d09da float128: Add conversion from float128 to mpn adds aab0f374e7 Remove duplicated code from __printf_fp_l, __printf_fphex, a [...] adds 2bc646c9e9 Refactor PRINT_FPHEX_LONG_DOUBLE into a reusable macro adds cf2046ec7d float128: Add strfromf128 adds 5e1122827a x86-64: Rename wmemset.h to ifunc-wmemset.h adds 4615f5aefe Add more tests for memchr new 9f8e103a6c ld.so: Consolidate 2 strtouls into _dl_strtoul new e5c2103926 Add TUNABLES to control IFUNC selection and cache sizes This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9506057c4b) \ N -- N -- N refs/heads/hjl/tunables/master (e5c2103926) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 408 ++++++++++++++++++++ NEWS | 14 + README.tunables | 69 +++- benchtests/bench-memchr.c | 17 +- bits/signum.h | 2 +- bits/types/stack_t.h | 2 +- debug/segfault.c | 2 +- elf/Versions | 2 +- elf/dl-cache.c | 5 +- elf/dl-hwcaps.c | 11 +- .../aarch64/cpu-features.c => elf/dl-hwcaps.h | 31 +- elf/dl-minimal.c | 84 ---- elf/dl-misc.c | 84 ++++ elf/dl-support.c | 2 + elf/dl-tunables.c | 125 ++---- elf/dl-tunables.h | 53 ++- elf/dl-tunables.list | 5 + elf/rtld.c | 7 +- hurd/hurd/signal.h | 2 +- hurd/trampoline.c | 2 +- include/atomic.h | 16 +- include/bits/types/clock_t.h | 2 +- include/bits/types/clockid_t.h | 2 +- include/bits/types/struct_iovec.h | 2 +- include/bits/types/struct_itimerspec.h | 2 +- include/bits/types/struct_osockaddr.h | 2 +- include/bits/types/struct_sigstack.h | 2 +- include/bits/types/struct_timespec.h | 2 +- include/bits/types/struct_timeval.h | 2 +- include/bits/types/struct_tm.h | 2 +- include/bits/types/time_t.h | 2 +- include/bits/types/timer_t.h | 2 +- include/gmp.h | 8 + include/signal.h | 4 +- include/wchar.h | 3 + login/tst-ptsname.c | 1 - malloc/arena.c | 36 +- manual/tunables.texi | 23 ++ nptl/pthread_spin_init.c | 3 +- nptl/pthread_spin_lock.c | 71 ++-- nptl/pthread_spin_trylock.c | 54 ++- nptl/pthread_spin_unlock.c | 6 +- scripts/gen-tunables.awk | 1 + signal/sigaltstack.c | 2 +- signal/signal.h | 4 +- stdio-common/printf-parsemb.c | 1 + stdio-common/printf.h | 4 +- stdio-common/printf_fp.c | 192 +++++----- stdio-common/printf_fphex.c | 131 +++---- stdio-common/printf_size.c | 83 ++-- stdio-common/vfprintf.c | 10 +- stdlib/fpioconst.c | 8 +- stdlib/fpioconst.h | 18 +- stdlib/gmp-impl.h | 3 +- stdlib/stdlib.h | 9 + stdlib/strfrom-skeleton.c | 6 + string/test-memrchr.c | 17 + sysdeps/aarch64/atomic-machine.h | 1 + sysdeps/aarch64/nptl/pthread_spin_lock.c | 24 -- sysdeps/alpha/atomic-machine.h | 3 + sysdeps/arm/atomic-machine.h | 1 + sysdeps/arm/nptl/pthread_spin_lock.c | 23 -- sysdeps/generic/ldsodefs.h | 6 + sysdeps/gnu/errlist.c | 82 ++-- sysdeps/hppa/nptl/pthread_spin_lock.c | 23 -- sysdeps/i386/atomic-machine.h | 1 + sysdeps/ia64/atomic-machine.h | 3 + sysdeps/ieee754/float128/Makefile | 3 + sysdeps/ieee754/float128/Versions | 5 + .../float128/float1282mpn.c} | 7 +- sysdeps/ieee754/float128/float128_private.h | 2 + .../float128/strfromf128.c} | 14 +- sysdeps/ieee754/ldbl-128/ldbl2mpn.c | 3 +- sysdeps/ieee754/ldbl-128/printf_fphex.c | 88 +---- .../{printf_fphex.c => printf_fphex_macros.h} | 23 +- sysdeps/m68k/coldfire/atomic-machine.h | 3 + sysdeps/m68k/m680x0/m68020/atomic-machine.h | 3 + sysdeps/m68k/nptl/pthread_spin_lock.c | 24 -- sysdeps/mach/hurd/i386/signal-defines.sym | 6 +- sysdeps/mach/hurd/sigaltstack.c | 6 +- sysdeps/mach/hurd/sigstack.c | 2 +- sysdeps/microblaze/atomic-machine.h | 3 + sysdeps/microblaze/nptl/pthread_spin_lock.c | 24 -- sysdeps/mips/atomic-machine.h | 13 +- sysdeps/mips/nptl/pthread_spin_lock.c | 23 -- sysdeps/nios2/nptl/pthread_spin_lock.c | 24 -- sysdeps/powerpc/powerpc32/atomic-machine.h | 1 + sysdeps/powerpc/powerpc64/atomic-machine.h | 1 + sysdeps/s390/atomic-machine.h | 2 + sysdeps/s390/nptl/pthread_spin_lock.c | 32 -- sysdeps/s390/nptl/pthread_spin_trylock.c | 32 -- sysdeps/s390/nptl/pthread_spin_unlock.c | 32 -- sysdeps/sparc/sparc32/atomic-machine.h | 3 + sysdeps/sparc/sparc32/dl-machine.h | 6 +- sysdeps/sparc/sparc32/sparcv9/atomic-machine.h | 3 + sysdeps/sparc/sparc64/atomic-machine.h | 3 + sysdeps/tile/tilegx/atomic-machine.h | 1 + sysdeps/tile/tilepro/atomic-machine.h | 1 + sysdeps/unix/bsd/bits/signum.h | 2 +- sysdeps/unix/sysv/linux/aarch64/cpu-features.c | 10 +- sysdeps/unix/sysv/linux/aarch64/dl-procinfo.c | 15 + sysdeps/unix/sysv/linux/aarch64/dl-procinfo.h | 86 +++++ sysdeps/unix/sysv/linux/alpha/bits/signum.h | 2 +- sysdeps/unix/sysv/linux/alpha/sys/procfs.h | 2 +- sysdeps/unix/sysv/linux/bits/signum.h | 2 +- sysdeps/unix/sysv/linux/bits/types/stack_t.h | 2 +- sysdeps/unix/sysv/linux/dl-librecon.h | 2 +- sysdeps/unix/sysv/linux/hppa/____longjmp_chk.c | 2 +- sysdeps/unix/sysv/linux/hppa/atomic-machine.h | 3 + sysdeps/unix/sysv/linux/hppa/bits/signum.h | 2 +- sysdeps/unix/sysv/linux/i386/dl-procinfo.h | 3 + sysdeps/unix/sysv/linux/ia64/sys/procfs.h | 2 +- sysdeps/unix/sysv/linux/m68k/____longjmp_chk.c | 2 +- .../unix/sysv/linux/m68k/coldfire/atomic-machine.h | 3 + sysdeps/unix/sysv/linux/mips/bits/signum.h | 2 +- sysdeps/unix/sysv/linux/mips/bits/types/stack_t.h | 2 +- sysdeps/unix/sysv/linux/nios2/atomic-machine.h | 3 + sysdeps/unix/sysv/linux/powerpc/sys/procfs.h | 2 +- sysdeps/unix/sysv/linux/ptsname.c | 6 - sysdeps/unix/sysv/linux/s390/dl-procinfo.h | 3 + sysdeps/unix/sysv/linux/sh/atomic-machine.h | 3 + sysdeps/unix/sysv/linux/sh/sys/procfs.h | 2 +- sysdeps/unix/sysv/linux/sparc/bits/signum.h | 2 +- sysdeps/unix/sysv/linux/sys/procfs.h | 2 +- sysdeps/unix/sysv/linux/tst-clone2.c | 7 +- sysdeps/unix/sysv/linux/x86_64/sysdep.h | 2 +- sysdeps/unix/sysv/linux/x86_64/x32/sysdep.h | 4 + sysdeps/x86/cacheinfo.c | 55 +-- sysdeps/x86/cpu-features.c | 28 +- sysdeps/x86/cpu-features.h | 9 + sysdeps/x86/cpu-tunables.c | 6 +- sysdeps/x86/init-arch.h | 40 ++ sysdeps/x86_64/atomic-machine.h | 1 + sysdeps/x86_64/memrchr.S | 36 +- sysdeps/x86_64/memset.S | 18 +- sysdeps/x86_64/multiarch/Makefile | 10 +- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 37 ++ sysdeps/x86_64/multiarch/ifunc-wmemset.h | 42 ++ sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S | 425 +++++++++++++++++++++ sysdeps/x86_64/multiarch/memcmp.S | 13 +- .../x86_64/multiarch/memset-avx2-unaligned-erms.S | 8 +- .../multiarch/memset-avx512-unaligned-erms.S | 9 +- .../x86_64/multiarch/memset-vec-unaligned-erms.S | 24 +- sysdeps/x86_64/multiarch/memset.S | 13 +- sysdeps/x86_64/multiarch/wcsnlen-c.c | 9 + sysdeps/x86_64/multiarch/wcsnlen-sse4_1.S | 5 + sysdeps/x86_64/multiarch/{wmemcmp.S => wcsnlen.c} | 49 +-- sysdeps/x86_64/multiarch/wmemcmp-avx2-movbe.S | 4 + sysdeps/x86_64/multiarch/wmemcmp.S | 13 +- sysdeps/x86_64/multiarch/{wmemcmp.S => wmemset.c} | 33 +- .../multiarch/wmemset_chk-nonshared.S} | 8 +- .../multiarch/wmemset_chk.c} | 32 +- sysdeps/x86_64/strlen.S | 61 ++- sysdeps/x86_64/{bzero.S => wmemset.S} | 0 .../stack_t.h => sysdeps/x86_64/wmemset_chk.S | 30 +- timezone/Makefile | 1 + 156 files changed, 2260 insertions(+), 1162 deletions(-) copy sysdeps/unix/sysv/linux/aarch64/cpu-features.c => elf/dl-hwcaps.h (66%) delete mode 100644 sysdeps/aarch64/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/arm/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/hppa/nptl/pthread_spin_lock.c create mode 100644 sysdeps/ieee754/float128/Makefile copy sysdeps/{s390/nptl/pthread_spin_init.c => ieee754/float128/float1282mpn.c} (78%) copy sysdeps/{s390/nptl/pthread_spin_init.c => ieee754/float128/strfromf128.c} (71%) copy sysdeps/ieee754/ldbl-128/{printf_fphex.c => printf_fphex_macros.h} (85%) delete mode 100644 sysdeps/m68k/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/microblaze/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/mips/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/nios2/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/s390/nptl/pthread_spin_lock.c delete mode 100644 sysdeps/s390/nptl/pthread_spin_trylock.c delete mode 100644 sysdeps/s390/nptl/pthread_spin_unlock.c create mode 100644 sysdeps/unix/sysv/linux/aarch64/dl-procinfo.h create mode 100644 sysdeps/x86_64/multiarch/ifunc-wmemset.h create mode 100644 sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S create mode 100644 sysdeps/x86_64/multiarch/wcsnlen-c.c create mode 100644 sysdeps/x86_64/multiarch/wcsnlen-sse4_1.S copy sysdeps/x86_64/multiarch/{wmemcmp.S => wcsnlen.c} (56%) create mode 100644 sysdeps/x86_64/multiarch/wmemcmp-avx2-movbe.S copy sysdeps/x86_64/multiarch/{wmemcmp.S => wmemset.c} (65%) rename sysdeps/{s390/nptl/pthread_spin_init.c => x86_64/multiarch/wmemset_chk-nons [...] copy sysdeps/{unix/sysv/linux/aarch64/cpu-features.c => x86_64/multiarch/wmemset_c [...] copy sysdeps/x86_64/{bzero.S => wmemset.S} (100%) copy bits/types/stack_t.h => sysdeps/x86_64/wmemset_chk.S (63%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[gcc] branch rsandifo/sve-rebase created (now 5b4cc1776f3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch rsandifo/sve-rebase in repository gcc. at 5b4cc1776f3 Use conditional internal functions in if-conversion This branch includes the following new commits: new bb7dfe3efef Add missing ECF_NOTHROW flags to internal.def new 40b69cff196 Improve ECF_NOTHROW flags for direct internal functions new 71f65b1e625 Add a mem_alias_size helper class new c25a25d1b67 Add a fixed_size_mode class new 953902585c4 Add a fixed_size_mode_pod class new c26e4c20f58 Widening optab cleanup new c2034dc61a3 Add a full_integral_type_p helper function new 59b2f8365a1 Add a partial_integral_type_p helper function new e03d86d45bb Make more use of paradoxical_subreg_p new 175387c7bfd Add a partial_subreg_p predicate new f662fc1f4ca Make more use of HWI_COMPUTABLE_MODE_P new 43ecd42adb4 Make more use of df_read_modify_subreg_p new 64b2f1d436f Make more use of subreg_offset_from_lsb new d1ae4048a50 Make more use of subreg_lowpart_offset new 89002777a1e Make more use of subreg_size_lowpart_offset new b4ac7958b40 Make more use of byte_lowpart_offset new eec23e50a03 Add subreg_memory_offset helper functions new 792ef1caf62 Add wider_subreg_mode helper functions new debbb7a286f Fix bogus CONST_WIDE_INT hash new 64a442ea773 Make more use of GET_MODE_UNIT_SIZE new a8131d3e69c Make more use of GET_MODE_UNIT_BITSIZE new 4ef2343e472 Make more use of GET_MODE_UNIT_PRECISION new 1d897d7eae4 Add helpers for shift count modes new 53974281653 Simplify pad_below implementation new 5407ba2baa4 Remove the frame size argument from function_prologue/epilogue new f522c3c8c51 Turn HARD_REGNO_CALL_PART_CLOBBERED into a target hook new 5f7383da3b5 Turn HARD_REGNO_MODE_OK into a target hook new 4614d7f6388 Turn MODES_TIEABLE_P into a target hook new 1a08aafee3b Turn SLOW_UNALIGNED_ACCESS into a target hook new 46fe110a43c Turn FUNCTION_ARG_PADDING into a target hook new 39895728dcf Use MACRO_MODE for HARD_REGNO_NREGS new 722833ab410 Use MACRO_MODE for SECONDARY_MEMORY_NEEDED_MODE new 16a67e21de4 Use MACRO_MODE for SECONDARY_MEMORY_NEEDED new eead50e23de Use MACRO_MODE for targhooks.c and address.h wrappers new 1544c45c5ad Use MACRO_MODE for CANNOT_CHANGE_MODE_CLASS new 029458d9574 Use MACRO_MODE for TRULY_NOOP_TRUNCATION_MODES_P new 3e5ad491e31 Use MACRO_MODE for FUNCTION_ARG_OFFSET new 03817ebe107 Pass rtx and index to read-md.c iterator routines new eca4e545ccb Factor out the mode handling in lower-subreg.c new 5864e8c8e6c Add a vect_get_num_copies helper routine new 56f47407d2e Add a vect_worthwhile_without_simd_p helper routine new fdb783eef05 Store VECTOR_CST_NELTS directly in tree node new 336cb967a84 Pass number of elements alongside tree* when constructing vectors new bb24a5f8f28 Add gimple_build_vector* helpers new 27629ec7bf0 Make more use of gimple-fold.h new b7a28e8d0e5 Add a vect_get_dr_size helper function new 9d349efd316 Let the target choose a vectorisation alignment new 02601d6761f Pass slp_index down to vect_analyze_stmt new e69da051066 Add rtx const vec_duplicate helpers new cd3fa6ea4d6 Allow vector CONSTs new 91a9d583e19 compare_values use in extract_range_from_multiplicative_op_1 new a9febfcdae3 Add missing int_cst_rangeN checks to tree-vrp.c new 14c61dc92de Tighten tree-ssa-ccp.c:get_value_for_expr condition new 171a671c219 Fix unguarded uses of tree_to_uhwi new 441245f3f75 Add a VEC_SERIES rtl code new 26d17444bf0 Add a VEC_DUPLICATE_EXPR tree code and associated optab new 24f5938a5b4 Add VEC_SERIES_EXPR and associated optab new 9ab0eca7db0 Treat VEC_{DUPLICATE,SERIES}_EXPR as gimple constants new 234d6d62227 [AArch64] Add an endian_lane_rtx helper routine new d8c3c0f7497 Fix for match.pd handling of three-constant bitops new c450f436a0c Fix type of bitstart in vectorizable_live_operation new 24c84b415ac Add LOOP_VINFO_MAX_VECT_FACTOR new f4066f5482b Add poly-int.h new 37f497895e3 Make mode query functions accept poly_ints new 7be8081c17f Add polynomial rtx constants new ca36f7f92bd Add polynomial tree constants new 83fe1bb8b50 Add poly_int dump routines new 20292972199 poly_int: compute_data_ref_aligment new 8070258d448 Make REG_OFFSET a poly_int64 new 265b7cb0d44 Add DWARF support for polynomial offsets new 8ec9da5287f poly_int: fold_ctor_reference new 3e2c2d16265 poly_int: same_addr_size_stores_p new 7e302542844 poly_int: ao_ref and vn_reference_op_t new 7987bc09dad poly_int: dse.c new fe60542cc03 poly_int: rtx_addr_can_trap_p_1 new ba9da4c2e26 poly_int: MEM_OFFSET and MEM_SIZE new 2c1628d84f2 poly_int: lra frame offsets new cb92e04c06b poly_int: store_bit_field bitrange new a58d2f800fc poly_int: extract_bit_field bitrange new 20efca25850 poly_int: C++ bitfield regions new 8437389ea2e poly_int: store_field & co new dbe9a01480d poly_int: SUBREG_BYTE new cf4593b2609 poly_int: operand_subword new de20cba09ff poly_int: DWARF CFA offsets new 2a3fcfab57a poly_int: ipa_parm_adjustment new c108ce200fd poly_int: get_ref_base_and_extent new b1abb145fa7 poly_int: get_addr_unit_base_and_extent new 6bb398048ec poly_int: aff_tree new 0ce73623d71 poly_int: symbolic_number new 8a70343b4e1 poly_int: pointer_may_wrap_p new 11cb22206f0 poly_int: get_inner_reference_aff new 234c565d5ba poly_int: get_inner_reference & co. new 3d8028db8c7 poly_int: reload.c new 29eb45fe30e poly_int: reload1.c new e2c537cffc1 poly_int: frame allocations new 15bb511e775 poly_int: push_block/emit_push_insn new 8c542123528 poly_int: REG_ARGS_SIZE new 00ae0b44f64 poly_int: argument sizes new 9fca576bdd2 poly_int: cfgexpand stack variables new 87c64cbc7aa poly_int: emit_inc new 85499c61e35 poly_int: reload<->ira interface new 40dbc27796f poly_int: emit_group_load/store new 3c4b9f6aeed poly_int: int_size_in_bytes new da7004e6444 poly_int: bit_field_size/offset new 2c8d1307522 poly_int: MEM_REF offsets new 9a81fa4e0ee poly_int: build_ref_for_offset new 167301dbf6f poly_int: get_binfo_at_offset new c733d2d6fa1 poly_int: tree-ssa-loop-ivopts.c:iv_use new a493d26cad3 poly_int: vectoriser vf and uf new 9e791265b87 poly_int: omp_max_vf new c9ba9673b0b poly_int: get_mask_mode new 9bf48826fc9 poly_int: current_vector_size and TARGET_AUTOVECTORIZE_VECT [...] new 824fcb9e2de poly_int: vect_no_alias_p new 88f3c042395 poly_int: GET_MODE_NUNITS new 4bd85055c37 poly_int: TYPE_VECTOR_SUBPARTS new b4267938646 poly_int: GET_MODE_PRECISION new f6f4bedfd02 poly_int: GET_MODE_BITSIZE new bae3890ae5e poly_int: GET_MODE_SIZE new 9c4477db868 Base subreg rules on REGMODE_NATURAL_SIZE rather than UNITS [...] new b5e6c63aa05 Use poly_int tree accessors instead of hwi accessors new 6540dd20bc6 Use poly_int rtx accessors instead of hwi accessors new 0fad5656c1e Make more use of simplify_gen_binary new ba0037bd728 Don't query the frontend for unsupported types new 2d93c2074d9 Improve spilling for variable-width slots new 53a3fcf568c Add support for MODE_VECTOR_BOOL new 03575106827 Add support for adjusting the number of units in a mode new 01f7bc66f82 Allow the target to set MAX_BITSIZE_MODE_ANY_MODE new 48b505c82fa Fix vectorizable_live_operation handling of vector booleans new 1492bb0ceab Use extract_bit_field_as_subreg for vectors new 9e975a5a6d4 Fix infinite loop in simplify_operand_subreg new 30aacebe296 Prevent invalid register mode changes in combine new 6ede44cbe60 Improve canonicalisation of TARGET_MEM_REFs new 0911cd7d4eb Improve vector mask pattern handling new 495271ac450 Improve ivopts handling of forced scales new 6db0d25a7f8 Fix a failure in the Fortran matmul* tests new e6fd6567469 SUBREG_PROMOTED_VAR_P handling in expand_direct_optab_fn new ffc24ba4eee [AArch64] Move code around new ef3485e6e0b [AArch64] Rework interface to add constant/offset routines new 29c9d8f2f46 [AArch64] Set NUM_POLY_INT_COEFFS to 2 new 0a27b347f49 [AArch64] Remove use of wider vector modes new 5e84c429ddc [AArch64] Rename cmp_result iterator new 498327fd12e [AArch64] Rename the internal "Upl" constraint new a3dd42cccae [AArch64] Add const_offset field to aarch64_address_info new 635d0fa1be8 [AArch64] Tweak aarch64_classify_address interface new 57f9e8068b2 [AArch64] Fix label mode new 2deb65ad226 [AArch64] Rewrite aarch64_simd_valid_immediate new 37eb639398b [AArch64] Generate permute patterns using rtx builders new 1c71de48343 [AArch64] Tighten address register subreg checks new 204c415e0c3 Add copy_rtx call to RTL loop unroller new ff67a1b2094 Use asm volatile ("" ::: "memory") new f5187922eca Add VECTOR_BITS to tree-vect.h new d30eb455de7 available_vector_sizes new 0eda3d12b5e vect_permN new d7523fa38e3 vect_element_align_preferred new 1849c19c85b target_vect_unaligned_possible new 417b8e89c37 vect_variable_length new e1671cd5ad6 vect_align_stack_vars new 3cffbeadc1a vect_masked_store new 26ac9f1af7d Revert DECL_USER_ALIGN patch new b8fd5de83d7 [AArch64] Add SVE support new 4bc25f69d4d [AArch64] Testsuite markup for SVE new dd03cc91692 Fix folding of vector mask EQ/NE expressions new fcbf7b99b53 [AArch64] SVE load/store_lanes support new 7b4572047a8 Add support for masked load/store_lanes new 71b41c785be Add support for bitwise reductions new d5ab9c7ee29 Add support for fully-predicated loops new 9114d45abe3 Make ivopts handle calls to internal functions new 355d8934f96 Allow the number of iterations to be smaller than VF new ca28eb79390 Handle peeling for alignment with masking new 3589f213d07 Add optabs for common types of permutation new c4feca5ea41 Handle more SLP constant and extern definitions for variable VF new 01ba1017671 Improve ivopts handling of offset multiples new 05a40262f14 Rework the legitimize_address_displacement hook new b00acb2bd1a Allow combine to reorder statements new 2c5d5405ffa SLP reductions with variable-length vectors new 022118c695b Predicated comparison folds new dac252557a4 Predicated arithmetic folds new adec056105a Add an empty_mask_is_expensive hook new 9d2fca2e530 Reuse results of vect_create_addr_base_for_vector_ref new e3a02277039 Allow capped vectorisation factors new 7be36d32083 Add support for BRKA and LASTB new 9b4010e1304 Add support for CLASTB new e3281a1b9b5 Add support for FADDA new bab1a5e1e5a Add support for gather loads and scatter stores new 5ac2211dbb5 Avoid pessimistic check for overlapping groups new 765c55fc8b8 Fix for big field stores new 5d92e45c05b Support for aliasing with variable strides new 4d4ff19f64f Add support for speculative loads new c193e765edc Add support for first-faulting loads new 2b78f45beb3 Make tree-ssa-strlen.c handle partial unterminated strings new 213f1294adc Allow single-element interleaving for non-power-of-2 strides new a7e11ea91b6 Use single-iteration epilogues when peeling for gaps new 58896e5b50e Replace FMA_EXPR with one internal fn per optab new 456a12b9380 Support fused multiply-adds in fully-masked reductions new 1d102ca4727 Record equivalences for spill registers new 42de6c12f1b Add early rematerialisation pass new 9459fcd9d50 Don't require an integer mode for PARALLELs new 42c09e02c88 Remove unnecessary temporary in tree-if-conv.c new 3f0e0191212 Handle vector boolean types when calculating the SLP unroll factor new 231ad6081b6 Implement SLP of internal functions new 5b4cc1776f3 Use conditional internal functions in if-conversion The 201 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

[gcc] branch linaro-dev/sve updated (932eda2e8fe -> d5754a616af)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch linaro-dev/sve in repository gcc. from 932eda2e8fe Don't require an integer mode for PARALLELs new a529358f21a Add missing ECF_NOTHROW flags to internal.def new 249b6733fae Improve ECF_NOTHROW flags for direct internal functions new 3b63abf8242 Make DEF_INTERNAL_COND_OPTAB_FN define only a single function new 306bebdf30b Remove unnecessary temporary in tree-if-conv.c new cfe44616c28 Handle vector boolean types when calculating the SLP unroll factor new 3d6dbd30aaa Implement SLP of internal functions new 6422fc0f844 Use conditional internal functions in if-conversion new d5754a616af Fix a test failure in gcc.target/aarch64/sve_mask_struct_store_3.c The 8 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/aarch64/aarch64-sve.md | 11 + gcc/config/aarch64/iterators.md | 17 +- gcc/internal-fn.c | 114 +++++-- gcc/internal-fn.def | 58 ++-- gcc/internal-fn.h | 54 ++- gcc/optabs.def | 5 + .../gcc.target/aarch64/sve_cond_arith_1.c | 64 ++++ .../gcc.target/aarch64/sve_cond_arith_1_run.c | 33 ++ .../gcc.target/aarch64/sve_cond_arith_2.c | 63 ++++ .../gcc.target/aarch64/sve_cond_arith_2_run.c | 34 ++ .../gcc.target/aarch64/sve_cond_arith_3.c | 62 ++++ .../gcc.target/aarch64/sve_cond_arith_3_run.c | 32 ++ .../gcc.target/aarch64/sve_cond_arith_4.c | 83 +++++ .../gcc.target/aarch64/sve_cond_arith_4_run.c | 35 ++ .../gcc.target/aarch64/sve_mask_struct_store_3.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve_vcond_7.c | 35 ++ gcc/testsuite/gcc.target/aarch64/sve_vcond_7_run.c | 25 ++ gcc/testsuite/gcc.target/aarch64/sve_vcond_8.c | 33 ++ gcc/testsuite/gcc.target/aarch64/sve_vcond_8_run.c | 29 ++ gcc/tree-if-conv.c | 363 ++++++++++++++------- gcc/tree-vect-patterns.c | 89 ++--- gcc/tree-vect-slp.c | 115 +++++-- gcc/tree-vect-stmts.c | 75 +++-- 23 files changed, 1160 insertions(+), 271 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_cond_arith_4_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_vcond_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_vcond_7_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_vcond_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve_vcond_8_run.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 5 months

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Tcwg-commits June 2017