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from e4bf08d44b [OPENMP] Allow value of thread local variables in target regions.
new aadd3206ff Fix one test case faiulre in commit 303766.
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test/CodeGen/builtins-ppc-vsx.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
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from 32718dfb0 Move clearOutputSections earlier. NFC.
new 76afdea7c Move writeTo to OutputSectionCommand.
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ELF/LinkerScript.cpp | 70 ++++++++++++++++++++++++++++++++++++++++------
ELF/LinkerScript.h | 7 +++--
ELF/OutputSections.cpp | 66 +------------------------------------------
ELF/OutputSections.h | 2 --
ELF/SyntheticSections.cpp | 5 ++--
ELF/Writer.cpp | 71 +++++++++++++++++++++++++++++++++--------------
6 files changed, 118 insertions(+), 103 deletions(-)
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from 8abe5967888 P9: D-form vector load/store. Differential Revision: https: [...]
new 4c833e2dc2a Fix a couple of typos in memory intrinsic optimization outp [...]
new bd571bcd530 Revert "Attempt to pacify ASan and UBSan reports in CrashRe [...]
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lib/Transforms/Instrumentation/PGOInstrumentation.cpp | 2 +-
test/tools/llvm-profdata/memop-size-prof.proftext | 2 +-
tools/llvm-profdata/llvm-profdata.cpp | 2 +-
unittests/Support/CrashRecoveryTest.cpp | 6 +-----
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from 0bc55da67 Rewrite badly-formatted switch. NFC.
new 32718dfb0 Move clearOutputSections earlier. NFC.
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ELF/Writer.cpp | 2 +-
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from a9efa933622 [InstCombine] Use less bitwise operations to handle Instruc [...]
new 8abe5967888 P9: D-form vector load/store. Differential Revision: https: [...]
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lib/Target/PowerPC/PPCInstrVSX.td | 52 ++++--
test/CodeGen/PowerPC/build-vector-tests.ll | 216 +++++++++++------------
test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll | 8 +-
test/CodeGen/PowerPC/ppc64-i128-abi.ll | 8 +-
test/CodeGen/PowerPC/pr25157-peephole.ll | 2 +-
test/CodeGen/PowerPC/swaps-le-6.ll | 8 +-
test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll | 48 ++---
test/CodeGen/PowerPC/vsx-ldst.ll | 4 +-
test/CodeGen/PowerPC/vsx-p9.ll | 72 ++++----
test/CodeGen/PowerPC/vsx_insert_extract_le.ll | 4 +-
test/CodeGen/PowerPC/vsx_shuffle_le.ll | 48 ++---
11 files changed, 243 insertions(+), 227 deletions(-)
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from a1adbd39e93 Move machine-cse-physreg.mir to test/CodeGen/Thumb
new a9efa933622 [InstCombine] Use less bitwise operations to handle Instruc [...]
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.../InstCombine/InstCombineSimplifyDemanded.cpp | 33 +++++++++-------------
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from f9152c247d9 [InstSimplify] Simplify uadd/sadd/umul/smul with overflow i [...]
new a1adbd39e93 Move machine-cse-physreg.mir to test/CodeGen/Thumb
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test/CodeGen/{MIR/Generic => Thumb}/machine-cse-physreg.mir | 0
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rename test/CodeGen/{MIR/Generic => Thumb}/machine-cse-physreg.mir (100%)
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from 117998d92 Do not track section types of previous sections, always use P [...]
new e02eb1063 Change the control flow so that the function is a bit more re [...]
new 90fea685f Make key-value types explicit. NFC.
new 0bc55da67 Rewrite badly-formatted switch. NFC.
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COFF/InputFiles.cpp | 21 ++++++++++++---------
COFF/Symbols.cpp | 19 +++++++++++--------
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from d10e0468f3a * cp-tree.h (ovl_skip_hidden): Declare. * tree.c (ovl_ski [...]
new c42d7ef725a When lra-remat rematerializes an instruction with a clobber [...]
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gcc/ChangeLog | 5 +++++
gcc/lra-remat.c | 22 +++++++++++++++++++---
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from e3a1116322b [ValueTracking] Convert most of the calls to computeKnownBi [...]
new f9152c247d9 [InstSimplify] Simplify uadd/sadd/umul/smul with overflow i [...]
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lib/Analysis/InstructionSimplify.cpp | 8 +++---
test/Transforms/InstSimplify/call.ll | 48 ++++++++++++++++++++++++++++++++++++
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