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from 10ad4e0 [llvm-cov] Strip redundant path components from filenames (fi [...]
new b20570e Revert r282872 "CVP. Turn marking adds as no wrap on by default"
new a328146 ARM: make sure FastISel bails on f64 operations for Cortex-M4.
new 6bc216c [NVPTX] Added support for .f16x2 instructions.
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Summary of changes:
lib/Target/ARM/ARMFastISel.cpp | 21 +-
lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp | 3 +
lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 2 +
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 346 ++++-
lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 +
lib/Target/NVPTX/NVPTXISelLowering.cpp | 332 +++--
lib/Target/NVPTX/NVPTXISelLowering.h | 6 +-
lib/Target/NVPTX/NVPTXInstrInfo.cpp | 2 +
lib/Target/NVPTX/NVPTXInstrInfo.td | 124 +-
lib/Target/NVPTX/NVPTXIntrinsics.td | 8 +
lib/Target/NVPTX/NVPTXRegisterInfo.cpp | 4 +
lib/Target/NVPTX/NVPTXRegisterInfo.td | 2 +
.../Scalar/CorrelatedValuePropagation.cpp | 5 +
test/CodeGen/ARM/fp-only-sp.ll | 62 +
test/CodeGen/NVPTX/LoadStoreVectorizer.ll | 34 +
test/CodeGen/NVPTX/f16-instructions.ll | 16 +-
test/CodeGen/NVPTX/f16x2-instructions.ll | 1433 ++++++++++++++++++++
test/CodeGen/NVPTX/param-load-store.ll | 182 ++-
test/Transforms/CorrelatedValuePropagation/add.ll | 2 +-
19 files changed, 2424 insertions(+), 162 deletions(-)
create mode 100644 test/CodeGen/ARM/fp-only-sp.ll
create mode 100644 test/CodeGen/NVPTX/f16x2-instructions.ll
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from 8580d50 Add call branch annotation for ICP promoted direct call in Sa [...]
new 10ad4e0 [llvm-cov] Strip redundant path components from filenames (fi [...]
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.../llvm-cov/Inputs/multiple-files2.covmapping | Bin 0 -> 136 bytes
test/tools/llvm-cov/multiple-files.test | 20 ++++---
tools/llvm-cov/CoverageReport.cpp | 58 ++++++++++++++++-----
3 files changed, 57 insertions(+), 21 deletions(-)
create mode 100644 test/tools/llvm-cov/Inputs/multiple-files2.covmapping
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from 186113f [AMDGPU] Shut the warning "getRegUnitWeight hides overload...". NFC.
new c5dd216 [Hexagon] Allow setting register in BitVal without storing into map
new 9bb4f10 [Hexagon] Handle saturations in Hexagon bit tracker
new 8580d50 Add call branch annotation for ICP promoted direct call in Sa [...]
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include/llvm/Passes/PassBuilder.h | 1 +
include/llvm/Transforms/Instrumentation.h | 8 ++-
include/llvm/Transforms/PGOInstrumentation.h | 5 +-
lib/Passes/PassBuilder.cpp | 8 +--
lib/Target/Hexagon/BitTracker.cpp | 16 +++---
lib/Target/Hexagon/BitTracker.h | 3 ++
lib/Target/Hexagon/HexagonBitTracker.cpp | 14 ++++++
lib/Transforms/IPO/PassManagerBuilder.cpp | 9 ++--
lib/Transforms/IPO/SampleProfile.cpp | 2 +-
.../Instrumentation/IndirectCallPromotion.cpp | 56 +++++++++++++++------
test/CodeGen/Hexagon/bit-ext-sat.ll | 57 ++++++++++++++++++++++
.../PGOProfile/indirect_call_promotion.ll | 4 ++
12 files changed, 153 insertions(+), 30 deletions(-)
create mode 100644 test/CodeGen/Hexagon/bit-ext-sat.ll
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unknown user pushed a change to branch master
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from 2acaa49 [CodeGen] Fix ExtParameterInfo bugs in C++ CodeGen code.
new 0df4330 Tighten up a regex in a test
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test/CodeGenObjCXX/arc-attrs-abi.mm | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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at 44c04ee Decouple user selection from internal selection
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new 44c04ee Decouple user selection from internal selection
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from a793abf Add context note to diagnostics that occur while declaring an [...]
new 2acaa49 [CodeGen] Fix ExtParameterInfo bugs in C++ CodeGen code.
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lib/CodeGen/CGCall.cpp | 42 +++++++++++++++++++++++++++++--------
lib/CodeGen/CGClass.cpp | 9 ++++----
lib/CodeGen/CGExprCXX.cpp | 21 ++++++++++++++-----
lib/CodeGen/CGVTables.cpp | 3 ++-
lib/CodeGen/CodeGenTypes.h | 7 +++++--
lib/CodeGen/MicrosoftCXXABI.cpp | 2 +-
test/CodeGenObjCXX/arc-attrs-abi.mm | 30 ++++++++++++++++++++++----
7 files changed, 88 insertions(+), 26 deletions(-)
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from 76c8745 Make InputSection a class. NFC.
new d53c03f Convert EhOutputSection to be a synthetic section.
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ELF/InputSection.cpp | 4 +-
ELF/InputSection.h | 2 +
ELF/OutputSections.cpp | 219 +---------------------------------------------
ELF/OutputSections.h | 48 ----------
ELF/Relocations.h | 1 -
ELF/SyntheticSections.cpp | 215 ++++++++++++++++++++++++++++++++++++++++++++-
ELF/SyntheticSections.h | 52 +++++++++++
ELF/Writer.cpp | 18 ++--
test/ELF/map-file.s | 1 +
9 files changed, 282 insertions(+), 278 deletions(-)
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from 4223061 2017-01-21 Bin Cheng <bin.cheng(a)arm.com>
new 568df2d PR tree-optimization/79389 * ifcvt.c (struct noce_if_info): [...]
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gcc/ChangeLog | 20 +++++++++++++
gcc/ifcvt.c | 92 ++++++++++++++++++++++++++++++++++++++---------------------
2 files changed, 80 insertions(+), 32 deletions(-)
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from d779422 [ORE] Remove ORE.emit{{.+}} functions
new 186113f [AMDGPU] Shut the warning "getRegUnitWeight hides overload...". NFC.
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lib/Target/AMDGPU/SIRegisterInfo.h | 2 ++
1 file changed, 2 insertions(+)
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from 17cd494 PR21166: Validate rdrand/rdseed support separately in gdb.rev [...]
new ef0b5f1 DWARF attrs: add delimiter
new 7714557 DWARF-5 basic functionality
new bc0a77d DWARF-5: call sites
new 7a7e106 DWARF-5: Macros
new 2f6cd59 DWARF-5: DW_FORM_data16
new a567769 DWARF-5: testcase
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binutils/ChangeLog | 63 ++
binutils/dwarf.c | 1335 +++++++++++++++++++++------
binutils/dwarf.h | 5 +
binutils/readelf.c | 2 +
binutils/testsuite/binutils-all/dw5.S | 679 ++++++++++++++
binutils/testsuite/binutils-all/dw5.W | 355 +++++++
binutils/testsuite/binutils-all/readelf.exp | 25 +
7 files changed, 2200 insertions(+), 264 deletions(-)
create mode 100644 binutils/testsuite/binutils-all/dw5.S
create mode 100644 binutils/testsuite/binutils-all/dw5.W
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