Tcwg-commits December 2017

tcwg-commits@lists.linaro.org

7 participants
2701 discussions

[clang] branch master updated (58744ab311 -> cbe186c3f1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 58744ab311 [ARM] ACLE parallel arithmetic and DSP style multiplications new cbe186c3f1 [Index] Add setPreprocessor member to IndexDataConsumer. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/clang/Index/IndexDataConsumer.h | 3 +++ lib/Index/IndexingAction.cpp | 22 ++++++++++++++-------- tools/libclang/CXIndexDataConsumer.h | 2 +- 3 files changed, 18 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (42a025965e8 -> 29d7ea36947)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 42a025965e8 [RISCV] MC layer support for the standard RV32D instruction [...] new 06535b0f5a2 [RISCV] MC layer support for the standard RV64I instructions new b9b4df7d228 [Testing/Support] Make matchers work with Expected<T&> new 94253b30509 [RISCV] MC layer support for the standard RV64M instruction [...] new 29d7ea36947 [RISCV] MC layer support for the standard RV64A instruction [...] The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/Testing/Support/Error.h | 16 +-- include/llvm/Testing/Support/SupportHelpers.h | 7 +- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 46 +++++-- lib/Target/RISCV/RISCV.td | 2 + lib/Target/RISCV/RISCVInstrFormats.td | 17 +++ lib/Target/RISCV/RISCVInstrInfo.td | 64 ++++++++- lib/Target/RISCV/RISCVInstrInfoA.td | 14 ++ lib/Target/RISCV/RISCVInstrInfoM.td | 8 ++ test/MC/RISCV/rv32a-invalid.s | 3 + test/MC/RISCV/rv32i-invalid.s | 4 +- test/MC/RISCV/rv32m-invalid.s | 9 ++ test/MC/RISCV/rv64a-invalid.s | 14 ++ test/MC/RISCV/rv64a-valid.s | 189 ++++++++++++++++++++++++++ test/MC/RISCV/rv64i-invalid.s | 20 +++ test/MC/RISCV/rv64i-valid.s | 98 +++++++++++++ test/MC/RISCV/rv64m-valid.s | 20 +++ unittests/Support/CMakeLists.txt | 2 + unittests/Support/ErrorTest.cpp | 40 ++++++ 18 files changed, 540 insertions(+), 33 deletions(-) create mode 100644 test/MC/RISCV/rv32m-invalid.s create mode 100644 test/MC/RISCV/rv64a-invalid.s create mode 100644 test/MC/RISCV/rv64a-valid.s create mode 100644 test/MC/RISCV/rv64i-invalid.s create mode 100644 test/MC/RISCV/rv64i-valid.s create mode 100644 test/MC/RISCV/rv64m-valid.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (e65af32d44f -> 42a025965e8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from e65af32d44f [RISCV] MC layer support for the standard RV32F instruction [...] new fd11bc08130 [CodeGen] Use MachineOperand::print in the MIRPrinter for M [...] new 42a025965e8 [RISCV] MC layer support for the standard RV32D instruction [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 56 +- include/llvm/CodeGen/LivePhysRegs.h | 8 +- include/llvm/CodeGen/MachineBasicBlock.h | 4 +- include/llvm/CodeGen/MachineInstr.h | 10 + include/llvm/CodeGen/MachineInstrBundle.h | 2 +- include/llvm/CodeGen/MachineOperand.h | 33 +- include/llvm/CodeGen/TargetInstrInfo.h | 4 +- include/llvm/CodeGen/TargetRegisterInfo.h | 5 + lib/CodeGen/AggressiveAntiDepBreaker.cpp | 8 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 6 +- lib/CodeGen/BranchFolding.cpp | 2 +- lib/CodeGen/CriticalAntiDepBreaker.cpp | 8 +- lib/CodeGen/ExpandPostRAPseudos.cpp | 2 +- lib/CodeGen/ImplicitNullChecks.cpp | 2 +- lib/CodeGen/InlineSpiller.cpp | 2 +- lib/CodeGen/LiveIntervalAnalysis.cpp | 4 +- lib/CodeGen/LiveVariables.cpp | 12 +- lib/CodeGen/MIRPrinter.cpp | 105 +- lib/CodeGen/MachineCSE.cpp | 8 +- lib/CodeGen/MachineCopyPropagation.cpp | 18 +- lib/CodeGen/MachineInstr.cpp | 89 +- lib/CodeGen/MachineOperand.cpp | 158 +-- lib/CodeGen/MachineSink.cpp | 6 +- lib/CodeGen/MachineVerifier.cpp | 2 +- lib/CodeGen/RegAllocFast.cpp | 4 +- lib/CodeGen/RegisterCoalescer.cpp | 30 +- lib/CodeGen/RegisterScavenging.cpp | 2 +- lib/CodeGen/SplitKit.cpp | 2 +- lib/CodeGen/TargetRegisterInfo.cpp | 15 + lib/CodeGen/TwoAddressInstructionPass.cpp | 48 +- lib/CodeGen/VirtRegMap.cpp | 10 +- lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp | 6 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 6 +- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 4 +- lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 17 +- lib/Target/AMDGPU/CaymanInstructions.td | 4 +- lib/Target/AMDGPU/EvergreenInstructions.td | 4 +- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 8 +- lib/Target/AMDGPU/SIFixWWMLiveness.cpp | 4 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 4 +- lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 2 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 +- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 +- lib/Target/ARM/ARMISelLowering.cpp | 2 +- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 +- lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 +- lib/Target/Hexagon/HexagonBlockRanges.cpp | 2 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 6 +- lib/Target/Hexagon/HexagonCopyToCombine.cpp | 8 +- lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 36 +- lib/Target/Hexagon/HexagonExpandCondsets.cpp | 12 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 2 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 8 +- lib/Target/Hexagon/HexagonNewValueJump.cpp | 12 +- lib/Target/Hexagon/HexagonPeephole.cpp | 28 +- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 24 +- .../Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp | 4 +- .../Hexagon/MCTargetDesc/HexagonMCShuffler.cpp | 14 +- lib/Target/Hexagon/RDFGraph.h | 2 +- lib/Target/Mips/MipsInstrInfo.cpp | 2 +- lib/Target/NVPTX/NVPTXPeephole.cpp | 6 +- lib/Target/PowerPC/PPCBranchCoalescing.cpp | 24 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 6 +- lib/Target/PowerPC/PPCMIPeephole.cpp | 6 +- lib/Target/PowerPC/PPCQPXLoadSplat.cpp | 4 +- lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 18 +- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 64 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 25 + lib/Target/RISCV/RISCV.td | 8 + lib/Target/RISCV/RISCVInstrInfo.td | 1 + lib/Target/RISCV/RISCVInstrInfoD.td | 131 ++ lib/Target/RISCV/RISCVRegisterInfo.td | 27 + lib/Target/RISCV/RISCVSubtarget.h | 2 + lib/Target/SystemZ/SystemZElimCompare.cpp | 4 +- lib/Target/X86/README-X86-64.txt | 8 +- lib/Target/X86/X86FixupBWInsts.cpp | 6 +- lib/Target/X86/X86InstrInfo.cpp | 10 +- lib/Target/X86/X86VZeroUpper.cpp | 2 +- test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 24 +- .../AArch64/GlobalISel/verify-regbankselected.mir | 4 +- .../CodeGen/AArch64/GlobalISel/verify-selected.mir | 6 +- .../AArch64/aarch64-a57-fp-load-balancing.ll | 2 +- .../CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll | 2 +- test/CodeGen/AArch64/arm64-csldst-mmo.ll | 2 +- .../CodeGen/AArch64/arm64-dead-register-def-bug.ll | 2 +- test/CodeGen/AArch64/arm64-fast-isel-rem.ll | 6 +- test/CodeGen/AArch64/arm64-ldp-cluster.ll | 52 +- .../AArch64/arm64-misched-forwarding-A53.ll | 2 +- test/CodeGen/AArch64/arm64-misched-memdep-bug.ll | 4 +- test/CodeGen/AArch64/arm64-misched-multimmo.ll | 2 +- test/CodeGen/AArch64/loh.mir | 78 +- test/CodeGen/AArch64/machine-copy-prop.ll | 12 +- test/CodeGen/AArch64/scheduledag-constreg.mir | 8 +- test/CodeGen/AArch64/tailcall_misched_graph.ll | 6 +- test/CodeGen/AMDGPU/llvm.dbg.value.ll | 2 +- test/CodeGen/AMDGPU/schedule-regpressure.mir | 2 +- .../ARM/2010-06-29-PartialRedefFastAlloc.ll | 4 +- test/CodeGen/ARM/2011-11-14-EarlyClobber.ll | 2 +- .../ARM/2014-01-09-pseudo_expand_implicit_reg.ll | 4 +- test/CodeGen/ARM/Windows/vla-cpsr.ll | 2 +- test/CodeGen/ARM/crash-greedy.ll | 2 +- test/CodeGen/ARM/ifcvt-dead-def.ll | 2 +- test/CodeGen/ARM/misched-copy-arm.ll | 6 +- test/CodeGen/ARM/misched-int-basic-thumb2.mir | 22 +- test/CodeGen/ARM/misched-int-basic.mir | 14 +- test/CodeGen/ARM/sched-it-debug-nodes.mir | 6 +- test/CodeGen/ARM/single-issue-r52.mir | 14 +- test/CodeGen/ARM/subreg-remat.ll | 6 +- test/CodeGen/ARM/vldm-liveness.mir | 8 +- .../AVR/select-must-add-unconditional-jump.ll | 10 +- test/CodeGen/Hexagon/branch-folder-hoist-kills.mir | 14 +- test/CodeGen/Hexagon/post-inc-aa-metadata.ll | 2 +- .../Lanai/lanai-misched-trivial-disjoint.ll | 2 +- test/CodeGen/PowerPC/byval-agg-info.ll | 2 +- test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 16 +- test/CodeGen/PowerPC/quadint-return.ll | 4 +- test/CodeGen/SystemZ/pr32505.ll | 4 +- .../SystemZ/regalloc-fast-invalid-kill-flag.mir | 2 +- test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll | 4 +- test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll | 4 +- test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll | 2 +- test/CodeGen/X86/2010-04-08-CoalescerBug.ll | 4 +- test/CodeGen/X86/2010-05-12-FastAllocKills.ll | 24 +- test/CodeGen/X86/GlobalISel/add-scalar.ll | 10 +- test/CodeGen/X86/GlobalISel/ext-x86-64.ll | 2 +- test/CodeGen/X86/GlobalISel/ext.ll | 4 +- test/CodeGen/X86/GlobalISel/gep.ll | 4 +- test/CodeGen/X86/GlobalISel/x86_64-fallback.ll | 2 +- test/CodeGen/X86/add-sub-nsw-nuw.ll | 2 +- test/CodeGen/X86/add.ll | 4 +- test/CodeGen/X86/addcarry.ll | 2 +- test/CodeGen/X86/anyext.ll | 8 +- test/CodeGen/X86/atomic-eflags-reuse.ll | 2 +- test/CodeGen/X86/avx-cast.ll | 14 +- test/CodeGen/X86/avx-cmp.ll | 2 +- test/CodeGen/X86/avx-intrinsics-fast-isel.ll | 56 +- test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 4 +- test/CodeGen/X86/avx-vinsertf128.ll | 6 +- test/CodeGen/X86/avx-vzeroupper.ll | 12 +- test/CodeGen/X86/avx2-conversions.ll | 8 +- test/CodeGen/X86/avx2-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/avx2-shift.ll | 8 +- test/CodeGen/X86/avx2-vector-shifts.ll | 8 +- test/CodeGen/X86/avx512-arith.ll | 24 +- test/CodeGen/X86/avx512-build-vector.ll | 2 +- test/CodeGen/X86/avx512-calling-conv.ll | 16 +- test/CodeGen/X86/avx512-cmp-kor-sequence.ll | 2 +- test/CodeGen/X86/avx512-cvt.ll | 66 +- test/CodeGen/X86/avx512-ext.ll | 28 +- test/CodeGen/X86/avx512-extract-subvector.ll | 4 +- test/CodeGen/X86/avx512-hadd-hsub.ll | 20 +- test/CodeGen/X86/avx512-insert-extract.ll | 104 +- test/CodeGen/X86/avx512-insert-extract_i1.ll | 2 +- test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 38 +- test/CodeGen/X86/avx512-intrinsics.ll | 24 +- test/CodeGen/X86/avx512-mask-op.ll | 132 +- test/CodeGen/X86/avx512-memfold.ll | 2 +- test/CodeGen/X86/avx512-regcall-Mask.ll | 78 +- test/CodeGen/X86/avx512-regcall-NoMask.ll | 30 +- test/CodeGen/X86/avx512-schedule.ll | 64 +- test/CodeGen/X86/avx512-select.ll | 12 +- test/CodeGen/X86/avx512-shift.ll | 10 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 14 +- test/CodeGen/X86/avx512-trunc.ll | 30 +- test/CodeGen/X86/avx512-vbroadcast.ll | 8 +- test/CodeGen/X86/avx512-vec-cmp.ll | 30 +- test/CodeGen/X86/avx512-vec3-crash.ll | 6 +- test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll | 8 +- test/CodeGen/X86/avx512bw-mov.ll | 16 +- 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| 34 +- test/CodeGen/X86/bitcast-int-to-vector-bool.ll | 10 +- test/CodeGen/X86/bitcast-int-to-vector.ll | 2 +- test/CodeGen/X86/bitcast-setcc-128.ll | 66 +- test/CodeGen/X86/bitcast-setcc-256.ll | 38 +- test/CodeGen/X86/bitcast-setcc-512.ll | 40 +- test/CodeGen/X86/bitreverse.ll | 14 +- test/CodeGen/X86/bmi-schedule.ll | 24 +- test/CodeGen/X86/bmi.ll | 22 +- test/CodeGen/X86/bool-simplify.ll | 4 +- test/CodeGen/X86/bool-vector.ll | 8 +- test/CodeGen/X86/broadcastm-lowering.ll | 8 +- test/CodeGen/X86/bypass-slow-division-32.ll | 14 +- test/CodeGen/X86/bypass-slow-division-64.ll | 8 +- test/CodeGen/X86/clz.ll | 68 +- test/CodeGen/X86/cmov-into-branch.ll | 2 +- test/CodeGen/X86/cmov-promotion.ll | 8 +- test/CodeGen/X86/cmov.ll | 2 +- test/CodeGen/X86/cmovcmov.ll | 4 +- test/CodeGen/X86/coalescer-dce.ll | 8 +- test/CodeGen/X86/combine-abs.ll | 4 +- test/CodeGen/X86/compress_expand.ll | 22 +- test/CodeGen/X86/critical-edge-split-2.ll | 2 +- test/CodeGen/X86/ctpop-combine.ll | 2 +- test/CodeGen/X86/dagcombine-cse.ll | 4 +- test/CodeGen/X86/divide-by-constant.ll | 34 +- test/CodeGen/X86/divrem.ll | 4 +- test/CodeGen/X86/divrem8_ext.ll | 36 +- test/CodeGen/X86/extractelement-index.ll | 50 +- test/CodeGen/X86/f16c-intrinsics-fast-isel.ll | 4 +- test/CodeGen/X86/fast-isel-cmp.ll | 8 +- test/CodeGen/X86/fast-isel-sext-zext.ll | 16 +- test/CodeGen/X86/fast-isel-shift.ll | 24 +- test/CodeGen/X86/fixup-bw-copy.ll | 2 +- test/CodeGen/X86/fixup-bw-inst.mir | 4 +- test/CodeGen/X86/gpr-to-mask.ll | 40 +- test/CodeGen/X86/half.ll | 2 +- test/CodeGen/X86/handle-move.ll | 6 +- test/CodeGen/X86/horizontal-reduce-smax.ll | 96 +- test/CodeGen/X86/horizontal-reduce-smin.ll | 96 +- test/CodeGen/X86/horizontal-reduce-umax.ll | 96 +- test/CodeGen/X86/horizontal-reduce-umin.ll | 96 +- test/CodeGen/X86/iabs.ll | 2 +- test/CodeGen/X86/illegal-bitfield-loadstore.ll | 6 +- test/CodeGen/X86/imul.ll | 4 +- test/CodeGen/X86/inline-asm-fpstack.ll | 6 +- test/CodeGen/X86/lea-3.ll | 8 +- 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test/CodeGen/X86/pr28173.ll | 4 +- test/CodeGen/X86/pr28560.ll | 2 +- test/CodeGen/X86/pr29061.ll | 4 +- test/CodeGen/X86/pr32282.ll | 2 +- test/CodeGen/X86/pr32329.ll | 2 +- test/CodeGen/X86/pr32345.ll | 6 +- test/CodeGen/X86/pr34653.ll | 8 +- test/CodeGen/X86/promote-vec3.ll | 48 +- test/CodeGen/X86/psubus.ll | 2 +- test/CodeGen/X86/reduce-trunc-shl.ll | 2 +- test/CodeGen/X86/remat-phys-dead.ll | 4 +- test/CodeGen/X86/sar_fold64.ll | 8 +- test/CodeGen/X86/schedule-x86_64.ll | 40 +- test/CodeGen/X86/select.ll | 12 +- test/CodeGen/X86/select_const.ll | 12 +- test/CodeGen/X86/setcc-lowering.ll | 4 +- test/CodeGen/X86/sext-i1.ll | 4 +- test/CodeGen/X86/shift-combine.ll | 8 +- test/CodeGen/X86/shift-double.ll | 4 +- test/CodeGen/X86/shrink-compare.ll | 4 +- test/CodeGen/X86/shuffle-vs-trunc-256.ll | 10 +- test/CodeGen/X86/sse2-schedule.ll | 20 +- test/CodeGen/X86/sse42-schedule.ll | 36 +- test/CodeGen/X86/subvector-broadcast.ll | 112 +- test/CodeGen/X86/tbm-intrinsics-fast-isel.ll | 8 +- test/CodeGen/X86/tbm_patterns.ll | 10 +- test/CodeGen/X86/umul-with-overflow.ll | 6 +- test/CodeGen/X86/urem-i8-constant.ll | 2 +- test/CodeGen/X86/urem-power-of-two.ll | 12 +- test/CodeGen/X86/vec_cmp_uint-128.ll | 8 +- test/CodeGen/X86/vec_fp_to_int.ll | 94 +- test/CodeGen/X86/vec_ins_extract-1.ll | 8 +- test/CodeGen/X86/vec_insert-4.ll | 2 +- test/CodeGen/X86/vec_insert-5.ll | 2 +- test/CodeGen/X86/vec_insert-8.ll | 4 +- test/CodeGen/X86/vec_insert-mmx.ll | 2 +- test/CodeGen/X86/vec_int_to_fp.ll | 186 +-- test/CodeGen/X86/vec_minmax_sint.ll | 48 +- test/CodeGen/X86/vec_minmax_uint.ll | 48 +- test/CodeGen/X86/vec_ss_load_fold.ll | 20 +- test/CodeGen/X86/vector-bitreverse.ll | 16 +- test/CodeGen/X86/vector-compare-all_of.ll | 36 +- test/CodeGen/X86/vector-compare-any_of.ll | 36 +- test/CodeGen/X86/vector-compare-results.ll | 52 +- test/CodeGen/X86/vector-extend-inreg.ll | 4 +- test/CodeGen/X86/vector-half-conversions.ll | 122 +- test/CodeGen/X86/vector-lzcnt-128.ll | 16 +- test/CodeGen/X86/vector-lzcnt-256.ll | 16 +- test/CodeGen/X86/vector-popcnt-128.ll | 16 +- test/CodeGen/X86/vector-popcnt-256.ll | 16 +- test/CodeGen/X86/vector-rotate-128.ll | 38 +- test/CodeGen/X86/vector-rotate-256.ll | 38 +- test/CodeGen/X86/vector-sext.ll | 28 +- test/CodeGen/X86/vector-shift-ashr-128.ll | 32 +- test/CodeGen/X86/vector-shift-ashr-256.ll | 28 +- test/CodeGen/X86/vector-shift-lshr-128.ll | 18 +- test/CodeGen/X86/vector-shift-lshr-256.ll | 10 +- test/CodeGen/X86/vector-shift-shl-128.ll | 14 +- test/CodeGen/X86/vector-shift-shl-256.ll | 10 +- test/CodeGen/X86/vector-shuffle-256-v4.ll | 6 +- test/CodeGen/X86/vector-shuffle-512-v16.ll | 4 +- test/CodeGen/X86/vector-shuffle-512-v8.ll | 8 +- test/CodeGen/X86/vector-shuffle-avx512.ll | 84 +- test/CodeGen/X86/vector-shuffle-combining-avx2.ll | 24 +- test/CodeGen/X86/vector-shuffle-v1.ll | 46 +- test/CodeGen/X86/vector-shuffle-variable-128.ll | 228 ++-- test/CodeGen/X86/vector-shuffle-variable-256.ll | 72 +- test/CodeGen/X86/vector-trunc-math.ll | 126 +- test/CodeGen/X86/vector-trunc.ll | 42 +- test/CodeGen/X86/vector-tzcnt-128.ll | 16 +- test/CodeGen/X86/vector-tzcnt-256.ll | 16 +- test/CodeGen/X86/verifier-phi-fail0.mir | 4 +- test/CodeGen/X86/vpshufbitqbm-intrinsics.ll | 2 +- test/CodeGen/X86/vselect-pcmp.ll | 8 +- test/CodeGen/X86/widen_bitops-0.ll | 36 +- test/CodeGen/X86/x86-interleaved-access.ll | 4 +- test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll | 2 +- .../X86/live-debug-vars-unused-arg-debugonly.mir | 8 +- test/MC/AArch64/arm64-leaf-compact-unwind.s | 2 +- test/MC/RISCV/rv32d-invalid.s | 21 + test/MC/RISCV/rv32d-valid.s | 159 +++ test/MC/RISCV/rv32f-invalid.s | 3 + unittests/CodeGen/MachineOperandTest.cpp | 39 + 341 files changed, 4646 insertions(+), 4120 deletions(-) create mode 100644 lib/Target/RISCV/RISCVInstrInfoD.td create mode 100644 test/MC/RISCV/rv32d-invalid.s create mode 100644 test/MC/RISCV/rv32d-valid.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[lldb] branch master updated (bdf0d2c21 -> fc6a261d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lldb. from bdf0d2c21 [lldb] Use PRIVATE in target_link_libraries new fc6a261d6 Variable: Fix usage of uninitialised value The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: source/Symbol/Variable.cpp | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[binutils-gdb] branch master updated (05a5feafdd -> 931c97c81a)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 05a5feafdd Rewrite check_shared_lib_support new 931c97c81a mcore-elf lacks shared lib support The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ld/ChangeLog | 4 ++++ ld/emulparams/elf32mcore.sh | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (2bd791038b5 -> e65af32d44f)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 2bd791038b5 [TableGen] Give the option of tolerating duplicate register names new e65af32d44f [RISCV] MC layer support for the standard RV32F instruction [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 36 +++++ .../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 12 +- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h | 4 + lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 58 ++++++- lib/Target/RISCV/RISCV.td | 6 + lib/Target/RISCV/RISCVInstrFormats.td | 47 +++++- lib/Target/RISCV/RISCVInstrInfo.td | 1 + lib/Target/RISCV/RISCVInstrInfoF.td | 167 +++++++++++++++++++++ lib/Target/RISCV/RISCVRegisterInfo.td | 52 +++++++ lib/Target/RISCV/RISCVSubtarget.h | 2 + test/MC/RISCV/rv32f-invalid.s | 29 ++++ test/MC/RISCV/rv32f-valid.s | 164 ++++++++++++++++++++ test/MC/RISCV/rv32i-invalid.s | 4 + 14 files changed, 594 insertions(+), 13 deletions(-) create mode 100644 lib/Target/RISCV/RISCVInstrInfoF.td create mode 100644 test/MC/RISCV/rv32f-invalid.s create mode 100644 test/MC/RISCV/rv32f-valid.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (1d4832bccf8 -> 2bd791038b5)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 1d4832bccf8 [X86][FMA][FMA4]: Adding full coverage of MC encoding for t [...] new 2bd791038b5 [TableGen] Give the option of tolerating duplicate register names The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/TableGen/StringMatcher.h | 7 ++- include/llvm/Target/Target.td | 8 +++ lib/TableGen/StringMatcher.cpp | 25 ++++---- test/TableGen/AllowDuplicateRegisterNames.td | 86 ++++++++++++++++++++++++++++ utils/TableGen/AsmMatcherEmitter.cpp | 8 ++- 5 files changed, 118 insertions(+), 16 deletions(-) create mode 100644 test/TableGen/AllowDuplicateRegisterNames.td -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[clang] branch master updated (e767a3be6e -> 58744ab311)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from e767a3be6e Ignore pointers to incomplete types when diagnosing misalign [...] new 58744ab311 [ARM] ACLE parallel arithmetic and DSP style multiplications The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/clang/Basic/BuiltinsARM.def | 1 + lib/Sema/SemaChecking.cpp | 21 ++-- test/Sema/builtins-arm.c | 184 ++++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[binutils-gdb] branch master updated (34ac47f671 -> 05a5feafdd)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 34ac47f671 Automatic date update in version.in new 05a5feafdd Rewrite check_shared_lib_support The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ld/ChangeLog | 5 ++++ ld/testsuite/lib/ld-lib.exp | 63 ++++++++------------------------------------- 2 files changed, 16 insertions(+), 52 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[gcc] branch master updated (93213c80bf5 -> fd2ce043154)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 93213c80bf5 rs6000: Split rs6000_cpu new 1bd1c9882bd rs6000: Don't use rs6000_cpu_attr directly new fd2ce043154 rs6000: Initialise rs6000_cpu correctly (PR43871) The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 22 ++++++++ gcc/config/rs6000/rs6000.c | 123 +++++++++++++++++++++++--------------------- gcc/config/rs6000/rs6000.h | 3 -- gcc/config/rs6000/rs6000.md | 4 +- 4 files changed, 87 insertions(+), 65 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

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Tcwg-commits December 2017