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from 5933b2471c8 [Hexagon] Make a test more flexible in HexagonLoopIdiomRecognition
new 3c64d8ff3ae [InstCombine] Update stale comment. NFC
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lib/Transforms/InstCombine/InstCombineCompares.cpp | 3 +--
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from 8986a29776a RISC-V: Implement movmemsi
new a3fc216d05c * g++.dg/pr50763-3.C (evalPoint): Return a value.
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gcc/testsuite/ChangeLog | 4 ++++
gcc/testsuite/g++.dg/pr50763-3.C | 2 +-
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from e2686b2cbc SystemZ Swift TargetInfo: swifterror support in the backend [...]
new 74ca15e3f7 [index] index field references in __builtin_offset
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lib/Index/IndexBody.cpp | 11 +++++++++++
test/Index/Core/index-source.cpp | 33 +++++++++++++++++++++++++++++++++
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unknown user pushed a change to branch master
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from f77bb6c56b RISC-V: Fix riscv g++ testsuite EH failures.
new 180093c763 RISC-V: Add Jim Wilson as a maintainer, and clean up our entries
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binutils/MAINTAINERS | 5 +++--
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from 1270b047fd RISC-V: Add satp as an alias for sptbr
new f77bb6c56b RISC-V: Fix riscv g++ testsuite EH failures.
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gas/ChangeLog | 8 ++++++++
gas/config/tc-riscv.c | 15 +++++++++++++++
gas/testsuite/gas/riscv/eh-relocs.d | 12 ++++++++++++
gas/testsuite/gas/riscv/eh-relocs.s | 11 +++++++++++
gas/testsuite/gas/riscv/riscv.exp | 1 +
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create mode 100644 gas/testsuite/gas/riscv/eh-relocs.d
create mode 100644 gas/testsuite/gas/riscv/eh-relocs.s
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from 79b94e462f8 RISC-V: Define MUSL_DYNAMIC_LINKER
new 8986a29776a RISC-V: Implement movmemsi
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gcc/ChangeLog | 16 +++++
gcc/config/riscv/riscv-protos.h | 4 +-
gcc/config/riscv/riscv.c | 156 ++++++++++++++++++++++++++++++++++++++++
gcc/config/riscv/riscv.h | 21 +++++-
gcc/config/riscv/riscv.md | 13 ++++
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unknown user pushed a change to branch master
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from 99835246622 [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ
new 5933b2471c8 [Hexagon] Make a test more flexible in HexagonLoopIdiomRecognition
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lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 69 ++++++++++++++++------
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from a02b41a7e6 Add some more breakpoint/location range tests
new 1270b047fd RISC-V: Add satp as an alias for sptbr
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gas/ChangeLog | 7 +++++++
gas/config/tc-riscv.c | 1 +
gas/testsuite/gas/riscv/riscv.exp | 1 +
gas/testsuite/gas/riscv/{t_insns.d => satp.d} | 3 ++-
gas/testsuite/gas/riscv/satp.s | 3 +++
include/ChangeLog | 6 ++++++
include/opcode/riscv-opc.h | 7 +++++--
7 files changed, 25 insertions(+), 3 deletions(-)
copy gas/testsuite/gas/riscv/{t_insns.d => satp.d} (52%)
create mode 100644 gas/testsuite/gas/riscv/satp.s
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from 0a1e59e30f4 [AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand
new 79b94e462f8 RISC-V: Define MUSL_DYNAMIC_LINKER
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gcc/ChangeLog | 5 +++++
gcc/config/riscv/linux.h | 11 +++++++++++
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from 6cf02b953eb [AArch64][SVE] Asm: Add SVE (Z) Register definitions and pa [...]
new 99835246622 [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZ
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lib/Target/AArch64/AArch64InstrInfo.td | 2 +
lib/Target/AArch64/AArch64SVEInstrInfo.td | 17 +++++++
lib/Target/AArch64/SVEInstrFormats.td | 41 +++++++++++++++++
test/MC/AArch64/SVE/assembler_tests/add.s | 66 ++++++++++++++++++++++++++++
test/MC/AArch64/SVE/assembler_tests/sub.s | 66 ++++++++++++++++++++++++++++
test/MC/AArch64/SVE/disassembler_tests/add.s | 50 +++++++++++++++++++++
test/MC/AArch64/SVE/disassembler_tests/sub.s | 50 +++++++++++++++++++++
7 files changed, 292 insertions(+)
create mode 100644 lib/Target/AArch64/AArch64SVEInstrInfo.td
create mode 100644 lib/Target/AArch64/SVEInstrFormats.td
create mode 100644 test/MC/AArch64/SVE/assembler_tests/add.s
create mode 100644 test/MC/AArch64/SVE/assembler_tests/sub.s
create mode 100644 test/MC/AArch64/SVE/disassembler_tests/add.s
create mode 100644 test/MC/AArch64/SVE/disassembler_tests/sub.s
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