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from e02e28c43a7 PR tree-optimization/82726 PR tree-optimization/70754 * [...]
new 7aa110c73cd Add noexcept to generic std::size, std::empty and std::data
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libstdc++-v3/ChangeLog | 5 +++++
libstdc++-v3/include/bits/range_access.h | 14 +++++++++-----
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from dffab709 [clangd] Support returning a limited number of completion results.
new ffa62912 [clangd] Fix time units in clangd performance trace
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clangd/Trace.cpp | 2 +-
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from a53ee5453b BuiltinOperatorOverloadBuilder: Don't consider types that ar [...]
new ff736a1b3f Try to fix test/SemaCXX/deleted-operator.cpp after r318309
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test/SemaCXX/deleted-operator.cpp | 4 ++--
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from b98166777 Tolerate even more [[nodiscard]] in the STL. Reviewed as http [...]
new 37b5a6b49 Clean up the tests for free data(), size() and empty()
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test/std/iterators/iterator.container/data.pass.cpp | 17 +++++++++--------
test/std/iterators/iterator.container/empty.pass.cpp | 16 ++++++++--------
test/std/iterators/iterator.container/size.pass.cpp | 19 +++++++++++--------
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unknown user pushed a change to branch master
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from d0212d429d Use Linux 4.14 in build-many-glibcs.py.
new ad4f43a234 Cleanup sigpause implementation
new 1ba1d8a44d Optimize sigrelse implementation
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ChangeLog | 8 ++++++++
signal/sigrelse.c | 12 +++---------
sysdeps/posix/sigpause.c | 26 ++++++--------------------
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from f640c8e4d83 [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
new 9c19935acce [AArch64] Adjust the cost model for Exynos M1 and M2
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lib/Target/AArch64/AArch64SchedM1.td | 31 ++++++++++++++-----------------
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from 5770e94c8 Propagate sh_entsize out.
new ce198ae16 Remove an unnecessary constraint.
new e743b05a9 Drop conflicting sh_entsize values.
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ELF/InputFiles.cpp | 11 +----------
ELF/OutputSections.cpp | 14 ++++++--------
test/ELF/linkerscript/merge-sections.s | 2 +-
test/ELF/merge-align.s | 34 ++++++++++++++++++++++++++++++++++
test/ELF/merge-entsize.s | 27 +++++++++++++++++++++++++++
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create mode 100644 test/ELF/merge-align.s
create mode 100644 test/ELF/merge-entsize.s
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from e074ad4a0cd [SLP] Added more missed optimization remarks
new f640c8e4d83 [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
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lib/Target/X86/X86InstrExtension.td | 62 +++++++++++++++++------------------
lib/Target/X86/X86SchedSandyBridge.td | 1 +
test/CodeGen/X86/schedule-x86_64.ll | 40 +++++++++++-----------
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unknown user pushed a change to branch master
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from 0b7fe98286 ASTMatchers.h: Fix ODR violations by avoiding internal linka [...]
new a53ee5453b BuiltinOperatorOverloadBuilder: Don't consider types that ar [...]
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lib/Sema/SemaOverload.cpp | 141 ++++++++++++++++-----------------
test/SemaCXX/microsoft-vs-float128.cpp | 34 ++++++++
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create mode 100644 test/SemaCXX/microsoft-vs-float128.cpp
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from 2180fee114 Check length of ifname before copying it into to ifreq structure.
new d0212d429d Use Linux 4.14 in build-many-glibcs.py.
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ChangeLog | 5 +++++
scripts/build-many-glibcs.py | 2 +-
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