Tcwg-commits November 2017

tcwg-commits@lists.linaro.org

7 participants
3251 discussions

[llvm] branch master updated (11acbdedb46 -> 360f53a4419)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 11acbdedb46 [ARM GlobalISel] Bail out for byval new 360f53a4419 Revert r319423: [MC] Function stack size section. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: docs/CodeGenerator.rst | 5305 ++++++++++++++++---------------- docs/CommandGuide/llc.rst | 400 ++- include/llvm/CodeGen/AsmPrinter.h | 2 - include/llvm/CodeGen/CommandFlags.def | 727 +++-- include/llvm/MC/MCObjectFileInfo.h | 747 +++-- include/llvm/Target/TargetOptions.h | 5 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 28 - lib/MC/MCObjectFileInfo.cpp | 1812 ++++++----- test/CodeGen/X86/stack-size-section.ll | 30 - 9 files changed, 4481 insertions(+), 4575 deletions(-) delete mode 100644 test/CodeGen/X86/stack-size-section.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (73846526685 -> 11acbdedb46)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 73846526685 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output new 11acbdedb46 [ARM GlobalISel] Bail out for byval The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/ARM/ARMCallLowering.cpp | 8 +++++++- test/CodeGen/ARM/GlobalISel/arm-unsupported.ll | 15 +++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (996d6ddb49d -> 73846526685)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 996d6ddb49d [X86][AVX512] Tag binop/rounding/sae instructions scheduler [...] new 73846526685 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/CodeGen/MachineOperand.h | 4 +- include/llvm/CodeGen/TargetInstrInfo.h | 16 ++--- include/llvm/CodeGen/TargetRegisterInfo.h | 4 +- lib/CodeGen/DetectDeadLanes.cpp | 12 ++-- lib/CodeGen/LiveIntervalAnalysis.cpp | 20 +++---- lib/CodeGen/MachineVerifier.cpp | 2 +- lib/CodeGen/PeepholeOptimizer.cpp | 20 +++---- lib/CodeGen/RegAllocGreedy.cpp | 30 +++++----- lib/CodeGen/RegisterCoalescer.cpp | 54 ++++++++--------- lib/CodeGen/RenameIndependentSubregs.cpp | 24 ++++---- lib/CodeGen/SplitKit.cpp | 4 +- lib/CodeGen/TargetRegisterInfo.cpp | 4 +- lib/Target/AArch64/AArch64InstrInfo.cpp | 22 +++---- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 12 ++-- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 34 +++++------ lib/Target/AMDGPU/SIFoldOperands.cpp | 8 +-- lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 10 ++-- lib/Target/AMDGPU/SIRegisterInfo.cpp | 10 ++-- lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- lib/Target/ARM/ARMBaseInstrInfo.h | 16 ++--- lib/Target/BPF/BPFISelDAGToDAG.cpp | 8 +-- lib/Target/Hexagon/BitTracker.cpp | 16 ++--- lib/Target/Hexagon/HexagonBitSimplify.cpp | 22 +++---- lib/Target/Hexagon/HexagonBlockRanges.cpp | 2 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 2 +- lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 34 +++++------ lib/Target/Hexagon/HexagonExpandCondsets.cpp | 70 +++++++++++----------- lib/Target/Hexagon/HexagonGenInsert.cpp | 8 +-- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 6 +- lib/Target/Hexagon/HexagonPeephole.cpp | 40 ++++++------- lib/Target/Hexagon/HexagonStoreWidening.cpp | 6 +- lib/Target/Hexagon/HexagonSubtarget.cpp | 8 +-- lib/Target/NVPTX/NVPTXPeephole.cpp | 6 +- lib/Target/PowerPC/PPCBranchCoalescing.cpp | 38 ++++++------ lib/Target/PowerPC/PPCInstrInfo.cpp | 2 +- lib/Target/PowerPC/PPCMIPeephole.cpp | 10 ++-- lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 40 ++++++------- lib/Target/X86/X86ISelLowering.cpp | 4 +- test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 30 +++++----- .../AArch64/GlobalISel/verify-regbankselected.mir | 4 +- .../CodeGen/AArch64/GlobalISel/verify-selected.mir | 6 +- test/CodeGen/AArch64/aarch64-stp-cluster.ll | 56 ++++++++--------- test/CodeGen/AArch64/arm64-fast-isel-rem.ll | 4 +- test/CodeGen/AArch64/arm64-ldp-cluster.ll | 52 ++++++++-------- .../AArch64/arm64-misched-forwarding-A53.ll | 6 +- test/CodeGen/AArch64/arm64-misched-memdep-bug.ll | 10 ++-- test/CodeGen/AArch64/tailcall_misched_graph.ll | 10 ++-- test/CodeGen/AMDGPU/lds-output-queue.ll | 18 +++--- test/CodeGen/AMDGPU/liveness.mir | 2 +- test/CodeGen/AMDGPU/spill-empty-live-interval.mir | 2 +- test/CodeGen/AMDGPU/subreg-intervals.mir | 4 +- test/CodeGen/ARM/2011-11-14-EarlyClobber.ll | 4 +- test/CodeGen/ARM/Windows/dbzchk.ll | 2 +- test/CodeGen/ARM/crash-greedy.ll | 2 +- test/CodeGen/ARM/misched-copy-arm.ll | 6 +- test/CodeGen/ARM/misched-int-basic-thumb2.mir | 24 ++++---- test/CodeGen/ARM/misched-int-basic.mir | 14 ++--- test/CodeGen/ARM/single-issue-r52.mir | 14 ++--- test/CodeGen/ARM/subreg-remat.ll | 8 +-- .../AVR/select-must-add-unconditional-jump.ll | 8 +-- test/CodeGen/Hexagon/circ_ldd_bug.ll | 8 +-- test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 4 +- test/CodeGen/Hexagon/post-inc-aa-metadata.ll | 2 +- .../Lanai/lanai-misched-trivial-disjoint.ll | 2 +- test/CodeGen/MIR/AArch64/spill-fold.mir | 2 +- test/CodeGen/PowerPC/quadint-return.ll | 4 +- test/CodeGen/WebAssembly/dbgvalue.ll | 2 +- test/CodeGen/X86/2011-09-14-valcoalesce.ll | 12 ++-- test/CodeGen/X86/GlobalISel/x86_64-fallback.ll | 2 +- test/CodeGen/X86/cmovcmov.ll | 10 ++-- test/CodeGen/X86/coalescer-dce.ll | 28 ++++----- test/CodeGen/X86/crash.ll | 6 +- test/CodeGen/X86/handle-move.ll | 18 +++--- test/CodeGen/X86/invalid-liveness.mir | 6 +- test/CodeGen/X86/liveness-local-regalloc.ll | 2 +- test/CodeGen/X86/misched-copy.ll | 2 +- test/CodeGen/X86/norex-subreg.ll | 6 +- test/CodeGen/X86/phys_subreg_coalesce-3.ll | 8 +-- .../X86/live-debug-vars-unused-arg-debugonly.mir | 6 +- 79 files changed, 523 insertions(+), 523 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[gcc] branch master updated (3dee933857c -> 01fc12577e3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 3dee933857c PR target/83210 * internal-fn.c (expand_mul_overflow): Op [...] new 01fc12577e3 Remove inv_list. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/c-family/ChangeLog | 4 ++++ gcc/c-family/c-common.h | 11 ----------- 2 files changed, 4 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (a90c32e02fc -> 996d6ddb49d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from a90c32e02fc [DAGCombine] Refactor ReduceLoadWidth new 5e536b7694c [MC] Function stack size section. new 996d6ddb49d [X86][AVX512] Tag binop/rounding/sae instructions scheduler [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: docs/CodeGenerator.rst | 5305 ++++++++++++++++---------------- docs/CommandGuide/llc.rst | 400 +-- include/llvm/CodeGen/AsmPrinter.h | 2 + include/llvm/CodeGen/CommandFlags.def | 727 ++--- include/llvm/MC/MCObjectFileInfo.h | 747 ++--- include/llvm/Target/TargetOptions.h | 5 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 28 + lib/MC/MCObjectFileInfo.cpp | 1812 +++++------ lib/Target/X86/X86InstrAVX512.td | 267 +- test/CodeGen/X86/stack-size-section.ll | 30 + 10 files changed, 4718 insertions(+), 4605 deletions(-) create mode 100644 test/CodeGen/X86/stack-size-section.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[clang] branch master updated (aac00512b5 -> 96c9689f47)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from aac00512b5 [ARM] disable FPU features when using soft floating point. new 96c9689f47 Revert [ARM] disable FPU features when using soft floating point. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Driver/ToolChains/Arch/ARM.cpp | 20 +-- test/Driver/arm-cortex-cpus.c | 6 +- test/Driver/arm-dotprod.c | 21 +-- test/Driver/arm-mfpu.c | 117 +----------- test/Preprocessor/arm-target-features.c | 309 +++++--------------------------- 5 files changed, 66 insertions(+), 407 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[openmp] branch master updated (9cdb255 -> 1696d28)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository openmp. from 9cdb255 Make kmp_r_sched_t into a union new 1696d28 Extension of HWLOC topology discovery with NUMA nodes and tiles The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: runtime/src/i18n/en_US.txt | 4 + runtime/src/kmp.h | 4 + runtime/src/kmp_affinity.cpp | 517 +++++++++++++++++++++++++++++-------------- runtime/src/kmp_global.cpp | 2 + runtime/src/kmp_settings.cpp | 37 +++- 5 files changed, 385 insertions(+), 179 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (86e196b704a -> a90c32e02fc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 86e196b704a Support generic lowering of vector bswap new a90c32e02fc [DAGCombine] Refactor ReduceLoadWidth The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 83 +++++++++++++------------------- 1 file changed, 33 insertions(+), 50 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[clang] branch master updated (f64fbddb87 -> aac00512b5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from f64fbddb87 clang-format: [JS] do not wrap after async/await. new aac00512b5 [ARM] disable FPU features when using soft floating point. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Driver/ToolChains/Arch/ARM.cpp | 20 ++- test/Driver/arm-cortex-cpus.c | 6 +- test/Driver/arm-dotprod.c | 21 ++- test/Driver/arm-mfpu.c | 117 +++++++++++- test/Preprocessor/arm-target-features.c | 309 +++++++++++++++++++++++++++----- 5 files changed, 407 insertions(+), 66 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

[llvm] branch master updated (b785e2618f6 -> 86e196b704a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from b785e2618f6 [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes new 86e196b704a Support generic lowering of vector bswap The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/IntrinsicLowering.cpp | 20 ++++++++-------- test/CodeGen/Generic/bswap.ll | 50 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 10 deletions(-) create mode 100644 test/CodeGen/Generic/bswap.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 11 months

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Tcwg-commits November 2017