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from 4ef99ab6831 [X86][XOP] Add missing scheduler classes to XOP instructions
new 4f7355afcdd [TableGen] AsmMatcher: Fix bug with reported diagnostic for [...]
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test/MC/AArch64/arm64-diags.s | 8 ++++----
test/MC/AArch64/basic-a64-diagnostics.s | 22 +++++++++++-----------
utils/TableGen/AsmMatcherEmitter.cpp | 5 ++---
3 files changed, 17 insertions(+), 18 deletions(-)
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from 5bc846a955a [ARM] Use SEH exceptions on thumbv7-windows
new 906bf03f280 [RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
new 4ef99ab6831 [X86][XOP] Add missing scheduler classes to XOP instructions
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lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 23 +++++-------
lib/Target/X86/X86InstrXOP.td | 67 ++++++++++++++++++++--------------
2 files changed, 48 insertions(+), 42 deletions(-)
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unknown user pushed a change to branch gcc-7-branch
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from da5de60cf6e Adapt Solaris 12 references
new 5fe0eb01fd7 [ARC] Backport r254866.
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gcc/ChangeLog | 8 ++++++++
gcc/config/arc/linux.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
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from 4ced528dfc2 * print-tree.h (debug_vec_tree): Remove prototype. * gdbi [...]
new 64bcf87bc20 [ARC] Reimplement exception handling support.
new 1d943b609ae Don't split call from its call arg location.
new eecc0d1efb0 * tree-ssa-threadbackward.c (find_jump_threads_backwards): [...]
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gcc/ChangeLog | 34 ++++++
gcc/cfgrtl.c | 5 +
gcc/config/arc/arc-protos.h | 2 +-
gcc/config/arc/arc.c | 202 +++++++++++++++++++++++++-------
gcc/config/arc/arc.h | 7 +-
gcc/config/arc/arc.md | 33 ------
gcc/testsuite/ChangeLog | 4 +
gcc/testsuite/gcc.target/arc/loop-5.cpp | 20 ++++
gcc/tree-ssa-threadbackward.c | 2 +-
9 files changed, 230 insertions(+), 79 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/loop-5.cpp
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from 6f46cf274f5 [X86][LWP] Add missing LWP itinerary class to lwpins instructions
new 5bc846a955a [ARM] Use SEH exceptions on thumbv7-windows
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lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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unknown user pushed a change to branch aldyh/threader
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from bb911e1a433 Make def_chain public in the gori map instead of protected [...]
new c60b4774358 Import from mainline and adjust accordingly:
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gcc/ChangeLog | 28 ++++
gcc/hash-set.h | 4 +
gcc/tree-ssa-threadbackward.c | 317 +++++++++++++++++++++---------------------
gcc/tree-ssa-threadbackward.h | 25 ----
4 files changed, 189 insertions(+), 185 deletions(-)
delete mode 100644 gcc/tree-ssa-threadbackward.h
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unknown user pushed a change to branch master
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from 0054242c55 [Analyzer] Revert r318750 because incorrect files were added [...]
new 3763c9e562 [Analyzer] Stable iteration on indirect goto LabelDecl's to [...]
new 1e94decf41 [MINGW] normalize WIN32 macros
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lib/Analysis/CFG.cpp | 2 +-
lib/Basic/Targets.cpp | 9 ++-
lib/Basic/Targets.h | 2 +-
lib/Basic/Targets/AArch64.cpp | 13 ----
lib/Basic/Targets/AArch64.h | 3 -
lib/Basic/Targets/ARM.cpp | 3 -
lib/Basic/Targets/OSTargets.h | 5 ++
lib/Basic/Targets/X86.h | 17 -----
test/Analysis/cfg-indirect-goto-determinism.cpp | 96 +++++++++++++++++++++++++
test/Preprocessor/predefined-macros.c | 58 +++++++++++++++
10 files changed, 169 insertions(+), 39 deletions(-)
create mode 100644 test/Analysis/cfg-indirect-goto-determinism.cpp
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from ec5c18ff129 [MI scheduler] Fix VADD and VSUB in cortex-a57 model
new 6f46cf274f5 [X86][LWP] Add missing LWP itinerary class to lwpins instructions
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lib/Target/X86/X86InstrInfo.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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from 9b22fdf383 [Analyzer] Non-determinism: stable iteration on indirect got [...]
new a091b96c92 [CodeGen] Generate TBAA type descriptors in a more reliable manner
new 0054242c55 [Analyzer] Revert r318750 because incorrect files were added [...]
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lib/AST/ASTImporter.cpp | 309 ++----------------------
lib/CodeGen/CodeGenTBAA.cpp | 99 ++++----
lib/CodeGen/CodeGenTBAA.h | 8 +
test/Analysis/cfg-indirect-goto-determinism.cpp | 96 --------
4 files changed, 81 insertions(+), 431 deletions(-)
delete mode 100644 test/Analysis/cfg-indirect-goto-determinism.cpp
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from 09a18aac31f [x86][icelake]BITALG vpopcnt{b,w} Differential Revision: ht [...]
new ec5c18ff129 [MI scheduler] Fix VADD and VSUB in cortex-a57 model
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lib/Target/ARM/ARMScheduleA57.td | 4 ++--
test/CodeGen/ARM/cortex-a57-misched-vadd.ll | 26 ++++++++++++++++++++++++++
test/CodeGen/ARM/cortex-a57-misched-vsub.ll | 26 ++++++++++++++++++++++++++
3 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/ARM/cortex-a57-misched-vadd.ll
create mode 100644 test/CodeGen/ARM/cortex-a57-misched-vsub.ll
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