Tcwg-commits October 2017

tcwg-commits@lists.linaro.org

9 participants
3371 discussions

[llvm] branch master updated (11435388441 -> aa354152445)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 11435388441 bpf: fix a bug in trunc-op optimization new aa354152445 Use range-based-for. NFC The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[clang] branch master updated (cbd4fdfd80 -> c7d0ffff68)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from cbd4fdfd80 Add missing clangRewrite lib dependency for clangToolingRefactor new c7d0ffff68 CodeGen: Fix missing debug loc due to alloca The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/CGExpr.cpp | 3 +-- test/CodeGenOpenCL/func-call-dbg-loc.cl | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 test/CodeGenOpenCL/func-call-dbg-loc.cl -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[lld] branch master updated (25dc8527d -> d6513c032)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository lld. from 25dc8527d [codeview] Fix handling of S_HEAPALLOCSITE new d6513c032 LLD/ELF/AMDGPU: Process AMDGPU-specific e_flags The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ELF/Arch/AMDGPU.cpp | 19 +++++++++++++++++++ test/ELF/Inputs/amdgpu-kernel-0.s | 6 ++++++ test/ELF/Inputs/amdgpu-kernel-1.s | 6 ++++++ test/ELF/Inputs/amdgpu-kernel-2.o | Bin 0 -> 408 bytes test/ELF/amdgpu-elf-flags-err.s | 7 +++++++ test/ELF/amdgpu-elf-flags.s | 10 ++++++++++ 6 files changed, 48 insertions(+) create mode 100644 test/ELF/Inputs/amdgpu-kernel-0.s create mode 100644 test/ELF/Inputs/amdgpu-kernel-1.s create mode 100644 test/ELF/Inputs/amdgpu-kernel-2.o create mode 100644 test/ELF/amdgpu-elf-flags-err.s create mode 100644 test/ELF/amdgpu-elf-flags.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[gcc] branch master updated (cbde9eb3e5a -> 41ca0095ec3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from cbde9eb3e5a Cleanup autopref scheduling new 41ca0095ec3 2017-10-24 Paolo Carlini <paolo.carlini(a)oracle.com> The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 12 +++++++++--- gcc/c/ChangeLog | 6 ++++++ gcc/c/c-decl.c | 3 ++- gcc/cp/ChangeLog | 8 ++++++++ gcc/cp/decl.c | 12 ++++++++++-- gcc/doc/invoke.texi | 3 ++- gcc/testsuite/ChangeLog | 9 +++++++++ gcc/testsuite/c-c++-common/Wbuiltin-declaration-mismatch-1.c | 4 ++++ .../c-c++-common/Wno-builtin-declaration-mismatch-1.c | 4 ++++ gcc/testsuite/g++.dg/parse/builtin2.C | 2 +- gcc/testsuite/g++.dg/warn/Wbuiltin_declaration_mismatch-1.C | 7 +++++++ gcc/testsuite/g++.old-deja/g++.mike/p811.C | 2 +- 12 files changed, 63 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/Wbuiltin-declaration-mismatch-1.c create mode 100644 gcc/testsuite/c-c++-common/Wno-builtin-declaration-mismatch-1.c create mode 100644 gcc/testsuite/g++.dg/warn/Wbuiltin_declaration_mismatch-1.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[compiler-rt] branch master updated (e6931d583 -> e9b5a2559)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository compiler-rt. from e6931d583 [XRay][compiler-rt] More fixups. new e9b5a2559 [asan] Add more x86 prologue decodings to handle x64 VC 2017 CRT The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/interception/interception_win.cc | 3 +++ 1 file changed, 3 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[llvm] branch master updated (db15b485c49 -> 11435388441)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from db15b485c49 [globalisel][tablegen] Fix future undefined behaviour in r316463. new 11435388441 bpf: fix a bug in trunc-op optimization The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/BPF/BPFISelDAGToDAG.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[llvm] branch master updated (edab7579664 -> db15b485c49)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from edab7579664 MIR: Print the register class or bank in vreg defs new db15b485c49 [globalisel][tablegen] Fix future undefined behaviour in r316463. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: utils/TableGen/GlobalISelEmitter.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[llvm] branch master updated (7c330fabaed -> edab7579664)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 7c330fabaed [PowerPC] Try to simplify a Swap if it feeds a Splat new edab7579664 MIR: Print the register class or bank in vreg defs The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/CodeGen/MIRPrinter.cpp | 46 +- .../AArch64/GlobalISel/arm64-callingconv-ios.ll | 16 +- .../AArch64/GlobalISel/arm64-callingconv.ll | 70 +- .../GlobalISel/arm64-irtranslator-stackprotect.ll | 4 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 794 ++++++++++----------- .../AArch64/GlobalISel/arm64-regbankselect.mir | 272 +++---- .../AArch64/GlobalISel/call-translator-ios.ll | 60 +- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 150 ++-- test/CodeGen/AArch64/GlobalISel/debug-insts.ll | 4 +- test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll | 46 +- .../AArch64/GlobalISel/irtranslator-bitcast.ll | 2 +- .../AArch64/GlobalISel/irtranslator-exceptions.ll | 42 +- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 42 +- test/CodeGen/AArch64/GlobalISel/legalize-and.mir | 16 +- test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 20 +- .../AArch64/GlobalISel/legalize-combines.mir | 34 +- .../AArch64/GlobalISel/legalize-constant.mir | 28 +- test/CodeGen/AArch64/GlobalISel/legalize-div.mir | 40 +- .../AArch64/GlobalISel/legalize-exceptions.ll | 16 +- test/CodeGen/AArch64/GlobalISel/legalize-ext.mir | 34 +- .../AArch64/GlobalISel/legalize-extracts.mir | 54 +- test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir | 8 +- test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir | 12 +- test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir | 68 +- test/CodeGen/AArch64/GlobalISel/legalize-gep.mir | 14 +- .../GlobalISel/legalize-ignore-non-generic.mir | 2 +- .../AArch64/GlobalISel/legalize-inserts.mir | 36 +- test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir | 98 +-- .../AArch64/GlobalISel/legalize-load-store.mir | 40 +- test/CodeGen/AArch64/GlobalISel/legalize-mul.mir | 28 +- .../GlobalISel/legalize-nonpowerof2eltsvec.mir | 8 +- test/CodeGen/AArch64/GlobalISel/legalize-or.mir | 26 +- test/CodeGen/AArch64/GlobalISel/legalize-phi.mir | 105 ++- test/CodeGen/AArch64/GlobalISel/legalize-pow.mir | 4 +- test/CodeGen/AArch64/GlobalISel/legalize-rem.mir | 52 +- test/CodeGen/AArch64/GlobalISel/legalize-shift.mir | 44 +- .../CodeGen/AArch64/GlobalISel/legalize-simple.mir | 40 +- test/CodeGen/AArch64/GlobalISel/legalize-sub.mir | 14 +- test/CodeGen/AArch64/GlobalISel/legalize-undef.mir | 8 +- test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 30 +- test/CodeGen/AArch64/GlobalISel/legalize-xor.mir | 14 +- .../GlobalISel/localizer-in-O0-pipeline.mir | 26 +- test/CodeGen/AArch64/GlobalISel/localizer.mir | 196 ++--- test/CodeGen/AArch64/GlobalISel/no-regclass.mir | 2 +- .../AArch64/GlobalISel/regbankselect-default.mir | 315 +++----- test/CodeGen/AArch64/GlobalISel/select-binop.mir | 327 +++------ test/CodeGen/AArch64/GlobalISel/select-bitcast.mir | 70 +- test/CodeGen/AArch64/GlobalISel/select-br.mir | 2 +- test/CodeGen/AArch64/GlobalISel/select-bswap.mir | 14 +- test/CodeGen/AArch64/GlobalISel/select-cbz.mir | 8 +- .../CodeGen/AArch64/GlobalISel/select-constant.mir | 16 +- .../AArch64/GlobalISel/select-dbg-value.mir | 4 +- test/CodeGen/AArch64/GlobalISel/select-fma.mir | 14 +- .../CodeGen/AArch64/GlobalISel/select-fp-casts.mir | 154 ++-- test/CodeGen/AArch64/GlobalISel/select-imm.mir | 8 +- .../AArch64/GlobalISel/select-implicit-def.mir | 7 +- .../AArch64/GlobalISel/select-insert-extract.mir | 16 +- test/CodeGen/AArch64/GlobalISel/select-int-ext.mir | 106 +-- .../AArch64/GlobalISel/select-int-ptr-casts.mir | 51 +- .../GlobalISel/select-intrinsic-aarch64-sdiv.mir | 10 +- test/CodeGen/AArch64/GlobalISel/select-load.mir | 152 +--- test/CodeGen/AArch64/GlobalISel/select-muladd.mir | 16 +- .../AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir | 8 +- test/CodeGen/AArch64/GlobalISel/select-phi.mir | 28 +- test/CodeGen/AArch64/GlobalISel/select-pr32733.mir | 6 +- test/CodeGen/AArch64/GlobalISel/select-store.mir | 135 +--- test/CodeGen/AArch64/GlobalISel/select-trunc.mir | 27 +- test/CodeGen/AArch64/GlobalISel/select-xor.mir | 44 +- test/CodeGen/AArch64/GlobalISel/select.mir | 42 +- test/CodeGen/AArch64/GlobalISel/translate-gep.ll | 66 +- .../AArch64/GlobalISel/varargs-ios-translator.ll | 4 +- test/CodeGen/AArch64/GlobalISel/vastart.ll | 2 +- test/CodeGen/AArch64/arm64-regress-opt-cmp.mir | 2 +- test/CodeGen/AArch64/regcoal-physreg.mir | 12 +- test/CodeGen/AArch64/spill-undef.mir | 18 +- .../AMDGPU/GlobalISel/amdgpu-irtranslator.ll | 2 +- .../AMDGPU/GlobalISel/inst-select-load-flat.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 74 +- .../AMDGPU/GlobalISel/inst-select-store-flat.mir | 4 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 22 +- test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir | 6 +- test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 6 +- .../AMDGPU/GlobalISel/legalize-constant.mir | 9 +- test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir | 6 +- test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 6 +- test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 6 +- test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 12 +- test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 6 +- test/CodeGen/AMDGPU/clamp-omod-special-case.mir | 24 +- test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 78 +- test/CodeGen/AMDGPU/detect-dead-lanes.mir | 62 +- test/CodeGen/AMDGPU/endpgm-dce.mir | 6 +- test/CodeGen/AMDGPU/fold-cndmask.mir | 12 +- test/CodeGen/AMDGPU/fold-immediate-output-mods.mir | 16 +- test/CodeGen/AMDGPU/fold-operands-order.mir | 6 +- .../AMDGPU/macro-fusion-cluster-vcc-uses.mir | 48 +- test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 14 +- test/CodeGen/AMDGPU/regcoal-subrange-join.mir | 8 +- test/CodeGen/AMDGPU/regcoalesce-dbg.mir | 10 +- .../rename-independent-subregs-mac-operands.mir | 18 +- test/CodeGen/AMDGPU/sdwa-gfx9.mir | 30 +- test/CodeGen/AMDGPU/sdwa-peephole-instr.mir | 118 +-- test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir | 12 +- test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir | 22 +- .../si-instr-info-correct-implicit-operands.ll | 2 +- test/CodeGen/AMDGPU/spill-empty-live-interval.mir | 12 +- test/CodeGen/AMDGPU/twoaddr-mad.mir | 10 +- test/CodeGen/AMDGPU/vop-shrink-frame-index.mir | 28 +- test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir | 8 +- .../ARM/GlobalISel/arm-instruction-select-cmp.mir | 404 +++++------ .../GlobalISel/arm-instruction-select-combos.mir | 34 +- .../ARM/GlobalISel/arm-instruction-select.mir | 170 ++--- test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 718 +++++++++---------- .../CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir | 288 ++++---- test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 746 +++++++++---------- test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 146 ++-- .../ARM/GlobalISel/arm-select-globals-pic.mir | 32 +- .../GlobalISel/arm-select-globals-ropi-rwpi.mir | 44 +- .../ARM/GlobalISel/arm-select-globals-static.mir | 20 +- test/CodeGen/ARM/imm-peephole-arm.mir | 19 +- test/CodeGen/ARM/imm-peephole-thumb.mir | 19 +- test/CodeGen/Hexagon/cext-opt-basic.mir | 15 +- test/CodeGen/Hexagon/early-if-debug.mir | 10 +- test/CodeGen/Hexagon/expand-condsets-def-undef.mir | 3 +- test/CodeGen/Hexagon/expand-condsets-imm.mir | 3 +- test/CodeGen/Hexagon/expand-condsets-impuse.mir | 2 +- test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 4 +- test/CodeGen/Hexagon/hwloop-redef-imm.mir | 2 +- test/CodeGen/Hexagon/regalloc-liveout-undef.mir | 3 +- .../CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir | 3 +- test/CodeGen/Lanai/peephole-compare.mir | 168 ++--- test/CodeGen/MIR/AArch64/atomic-memoperands.mir | 8 +- test/CodeGen/MIR/AArch64/spill-fold.mir | 4 +- test/CodeGen/MIR/AArch64/target-memoperands.mir | 6 +- test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir | 52 +- test/CodeGen/MIR/AMDGPU/fold-multiple.mir | 4 +- test/CodeGen/MIR/AMDGPU/intrinsics.mir | 2 +- test/CodeGen/MIR/AMDGPU/target-flags.mir | 4 +- .../NVPTX/floating-point-immediate-operands.mir | 8 +- test/CodeGen/MIR/X86/generic-instr-type.mir | 8 +- test/CodeGen/MIR/X86/metadata-operands.mir | 2 +- test/CodeGen/MIR/X86/roundtrip.mir | 4 +- test/CodeGen/MIR/X86/stack-object-operands.mir | 4 +- .../CodeGen/MIR/X86/subregister-index-operands.mir | 4 +- test/CodeGen/MIR/X86/subregister-operands.mir | 6 +- test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir | 4 +- test/CodeGen/MIR/X86/virtual-registers.mir | 12 +- test/CodeGen/PowerPC/debuginfo-split-int.ll | 4 +- test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 16 +- test/CodeGen/PowerPC/tls_get_addr_fence1.mir | 18 +- .../X86/GlobalISel/irtranslator-callingconv.ll | 598 ++++++++-------- test/CodeGen/X86/GlobalISel/legalize-GV.mir | 2 +- test/CodeGen/X86/GlobalISel/legalize-add-v128.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-add-v256.mir | 80 +-- test/CodeGen/X86/GlobalISel/legalize-add-v512.mir | 192 ++--- test/CodeGen/X86/GlobalISel/legalize-add.mir | 30 +- .../CodeGen/X86/GlobalISel/legalize-and-scalar.mir | 26 +- test/CodeGen/X86/GlobalISel/legalize-brcond.mir | 2 +- test/CodeGen/X86/GlobalISel/legalize-cmp.mir | 40 +- test/CodeGen/X86/GlobalISel/legalize-constant.mir | 30 +- .../CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir | 54 +- test/CodeGen/X86/GlobalISel/legalize-ext.mir | 78 +- .../X86/GlobalISel/legalize-fadd-scalar.mir | 12 +- .../X86/GlobalISel/legalize-fdiv-scalar.mir | 12 +- .../X86/GlobalISel/legalize-fmul-scalar.mir | 12 +- .../X86/GlobalISel/legalize-fpext-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fsub-scalar.mir | 12 +- test/CodeGen/X86/GlobalISel/legalize-gep.mir | 28 +- .../X86/GlobalISel/legalize-insert-vec256.mir | 6 +- .../X86/GlobalISel/legalize-insert-vec512.mir | 12 +- .../X86/GlobalISel/legalize-memop-scalar.mir | 53 +- .../CodeGen/X86/GlobalISel/legalize-mul-scalar.mir | 30 +- test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir | 18 +- test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir | 18 +- test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir | 18 +- test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir | 26 +- test/CodeGen/X86/GlobalISel/legalize-phi.mir | 92 +-- test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir | 24 +- test/CodeGen/X86/GlobalISel/legalize-sub.mir | 16 +- test/CodeGen/X86/GlobalISel/legalize-trunc.mir | 7 +- test/CodeGen/X86/GlobalISel/legalize-undef.mir | 24 +- .../CodeGen/X86/GlobalISel/legalize-xor-scalar.mir | 26 +- .../X86/GlobalISel/regbankselect-X86_64.mir | 51 +- test/CodeGen/X86/GlobalISel/select-GV.mir | 32 +- test/CodeGen/X86/GlobalISel/select-add-v128.mir | 32 +- test/CodeGen/X86/GlobalISel/select-add-v256.mir | 24 +- test/CodeGen/X86/GlobalISel/select-add-v512.mir | 40 +- test/CodeGen/X86/GlobalISel/select-add-x32.mir | 27 +- test/CodeGen/X86/GlobalISel/select-add.mir | 86 +-- test/CodeGen/X86/GlobalISel/select-and-scalar.mir | 40 +- test/CodeGen/X86/GlobalISel/select-blsi.mir | 22 +- test/CodeGen/X86/GlobalISel/select-blsr.mir | 22 +- test/CodeGen/X86/GlobalISel/select-brcond.mir | 22 +- test/CodeGen/X86/GlobalISel/select-cmp.mir | 208 ++---- test/CodeGen/X86/GlobalISel/select-constant.mir | 35 +- test/CodeGen/X86/GlobalISel/select-copy.mir | 26 +- test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir | 67 +- test/CodeGen/X86/GlobalISel/select-ext.mir | 73 +- .../X86/GlobalISel/select-extract-vec256.mir | 16 +- .../X86/GlobalISel/select-extract-vec512.mir | 17 +- test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/select-fconstant.mir | 25 +- test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir | 36 +- .../CodeGen/X86/GlobalISel/select-fpext-scalar.mir | 7 +- test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir | 36 +- test/CodeGen/X86/GlobalISel/select-gep.mir | 10 +- test/CodeGen/X86/GlobalISel/select-inc.mir | 6 +- .../X86/GlobalISel/select-insert-vec256.mir | 86 +-- .../X86/GlobalISel/select-insert-vec512.mir | 76 +- .../select-intrinsic-x86-flags-read-u32.mir | 7 +- .../X86/GlobalISel/select-leaf-constant.mir | 16 +- .../X86/GlobalISel/select-memop-scalar-x32.mir | 68 +- .../CodeGen/X86/GlobalISel/select-memop-scalar.mir | 120 ++-- test/CodeGen/X86/GlobalISel/select-memop-v128.mir | 42 +- test/CodeGen/X86/GlobalISel/select-memop-v256.mir | 55 +- test/CodeGen/X86/GlobalISel/select-memop-v512.mir | 28 +- .../CodeGen/X86/GlobalISel/select-merge-vec256.mir | 26 +- .../CodeGen/X86/GlobalISel/select-merge-vec512.mir | 32 +- test/CodeGen/X86/GlobalISel/select-mul-scalar.mir | 30 +- test/CodeGen/X86/GlobalISel/select-mul-vec.mir | 150 ++-- test/CodeGen/X86/GlobalISel/select-or-scalar.mir | 40 +- test/CodeGen/X86/GlobalISel/select-phi.mir | 12 +- test/CodeGen/X86/GlobalISel/select-sub-v128.mir | 88 +-- test/CodeGen/X86/GlobalISel/select-sub-v256.mir | 80 +-- test/CodeGen/X86/GlobalISel/select-sub-v512.mir | 40 +- test/CodeGen/X86/GlobalISel/select-sub.mir | 63 +- test/CodeGen/X86/GlobalISel/select-trunc.mir | 42 +- test/CodeGen/X86/GlobalISel/select-undef.mir | 14 +- .../X86/GlobalISel/select-unmerge-vec256.mir | 20 +- .../X86/GlobalISel/select-unmerge-vec512.mir | 26 +- test/CodeGen/X86/GlobalISel/select-xor-scalar.mir | 40 +- test/CodeGen/X86/debugloc-no-line-0.ll | 2 - test/CodeGen/X86/domain-reassignment.mir | 187 ++--- test/CodeGen/X86/implicit-use-spill.mir | 2 +- test/CodeGen/X86/lea-opt-with-debug.mir | 8 +- test/CodeGen/X86/movtopush.mir | 8 +- test/CodeGen/X86/peephole-recurrence.mir | 96 +-- test/CodeGen/X86/peephole.mir | 10 +- test/CodeGen/X86/sqrt-fastmath-mir.ll | 54 +- test/CodeGen/X86/tail-dup-debugloc.ll | 4 +- test/CodeGen/X86/update-terminator-debugloc.ll | 12 +- test/CodeGen/X86/xor-combine-debugloc.ll | 10 +- 246 files changed, 5414 insertions(+), 6949 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[gcc] branch hjl/pr82699 updated (84027615156 -> 9037eb21333)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch hjl/pr82699 in repository gcc. discards 84027615156 i386: Insert ENDBR before the profiling counter call new 9037eb21333 i386: Insert ENDBR before the profiling counter call This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (84027615156) \ N -- N -- N refs/heads/hjl/pr82699 (9037eb21333) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.target/i386/{pr82699-3.c => pr82699-6.c} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) copy gcc/testsuite/gcc.target/i386/{pr82699-3.c => pr82699-6.c} (60%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

[llvm] branch master updated (d9ad9f92cf6 -> 7c330fabaed)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from d9ad9f92cf6 BinaryFormat/MachO.h Don't mark header functions as file-sc [...] new 7c330fabaed [PowerPC] Try to simplify a Swap if it feeds a Splat The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/PowerPC/PPCMIPeephole.cpp | 47 ++++++++ .../PowerPC/p8-scalar_vector_conversions.ll | 4 +- test/CodeGen/PowerPC/ppc64-peephole-swap.ll | 134 +++++++++++++++++++++ 3 files changed, 183 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/PowerPC/ppc64-peephole-swap.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

7 years, 1 month

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Tcwg-commits October 2017