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from cfb1beeeeab [hsa] Add missing guard in OMP gridification
new b1a01306f5b Remove ios_mode::trunc from basic_ofstream openmode arguments
new c320789713c Fix ia64 build failure.
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Summary of changes:
gcc/ChangeLog | 4 ++++
gcc/gimplify.c | 1 +
libstdc++-v3/ChangeLog | 6 ++++++
libstdc++-v3/include/std/fstream | 45 ++++++++++------------------------------
4 files changed, 22 insertions(+), 34 deletions(-)
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from 4fc74ab57a8 Minor tweak to libstdc++ FAQ
new cfb1beeeeab [hsa] Add missing guard in OMP gridification
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gcc/ChangeLog | 5 +++++
gcc/omp-grid.c | 2 ++
2 files changed, 7 insertions(+)
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from 6d8efcd4440 Implement LWG 2485
new 6c391d9ac8e Minor header reorganization for unordered containers
new 4fc74ab57a8 Minor tweak to libstdc++ FAQ
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libstdc++-v3/ChangeLog | 9 +++++++++
libstdc++-v3/doc/xml/faq.xml | 13 +++++++++----
libstdc++-v3/include/bits/hashtable_policy.h | 4 +++-
libstdc++-v3/include/std/unordered_map | 3 +--
libstdc++-v3/include/std/unordered_set | 3 +--
5 files changed, 23 insertions(+), 9 deletions(-)
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unknown user pushed a change to branch master
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from 963ec731b44 [PassManager, SimplifyCFG] add test for PR34603 / D38566; NFC
new 1fd065d4bbf [X86] Regenerate test using update_llc_test_checks.py
new 7f36a3ae353 [X86] Remove AVX512 early out from X86FastISel::X86SelectCmp.
new 87eb2fe42c6 [X86] Make sure we don't create locked inc/dec instructions [...]
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lib/Target/X86/X86FastISel.cpp | 3 -
lib/Target/X86/X86ISelLowering.cpp | 55 +++-
lib/Target/X86/X86ISelLowering.h | 2 +-
lib/Target/X86/X86InstrCompiler.td | 36 ++-
lib/Target/X86/X86InstrInfo.td | 10 +
test/CodeGen/X86/atomic-eflags-reuse.ll | 70 +++--
test/CodeGen/X86/avx512-fsel.ll | 11 +-
test/CodeGen/X86/pr27591.ll | 4 +-
test/CodeGen/X86/pr32241.ll | 9 +-
test/CodeGen/X86/pr32284.ll | 496 +++++++++++++++++++++++++++++---
10 files changed, 602 insertions(+), 94 deletions(-)
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unknown user pushed a change to branch master
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from 68fe16dd32 ffsl, ffsll: Declare under __USE_MISC, not just __USE_GNU
new 4484b9e296 Assume that _DIRENT_HAVE_D_TYPE is always defined.
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ChangeLog | 15 +++++++++++++++
elf/ldconfig.c | 17 ++---------------
io/tst-mkdirat.c | 2 --
io/tst-mkfifoat.c | 2 --
io/tst-mknodat.c | 2 --
locale/programs/charmap-dir.c | 2 --
locale/programs/locale.c | 2 --
locale/programs/locarchive.c | 4 ----
posix/bug-glob2.c | 8 --------
posix/tst-dir.c | 10 ----------
posix/tst-glob_lstat_compat.c | 2 --
posix/tst-gnuglob-skeleton.c | 11 -----------
12 files changed, 17 insertions(+), 60 deletions(-)
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unknown user pushed a change to branch master
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from 5aa4dd9f9d CodeGen: Fix insertion position of addrspace cast for alloca
new f822d3299b [clang-format] Handle CRLF correctly when formatting escaped [...]
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lib/Format/FormatTokenLexer.cpp | 18 +++++++++++++-----
unittests/Format/FormatTest.cpp | 34 ++++++++++++++++++++++++++++++----
2 files changed, 43 insertions(+), 9 deletions(-)
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from 4ccf677f27f [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector lo [...]
new a52756b2c94 [AMDGPU] Emit metadata for hidden arguments for kernel enqueue
new 963ec731b44 [PassManager, SimplifyCFG] add test for PR34603 / D38566; NFC
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docs/AMDGPUUsage.rst | 8 +-
.../AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp | 38 +++++++++
.../MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp | 17 +++-
test/CodeGen/AMDGPU/enqueue-kernel.ll | 17 +++-
test/CodeGen/AMDGPU/hsa-metadata-enqueu-kernel.ll | 96 ++++++++++++++++++++++
.../AMDGPU/hsa-metadata-from-llvm-ir-full.ll | 47 +++++++++++
.../PhaseOrdering/simplifycfg-options.ll | 42 +++++++++-
7 files changed, 255 insertions(+), 10 deletions(-)
create mode 100644 test/CodeGen/AMDGPU/hsa-metadata-enqueu-kernel.ll
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from bd3b05d2cc [clang-format] Format raw string literals
new 1f7d6d2a21 Keep MSVC2015 happy after r316903
new 5aa4dd9f9d CodeGen: Fix insertion position of addrspace cast for alloca
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lib/CodeGen/CGExpr.cpp | 6 +++++-
lib/Format/Format.cpp | 4 ++--
test/CodeGenCXX/vla.cpp | 31 +++++++++++++++++++++++--------
3 files changed, 30 insertions(+), 11 deletions(-)
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from 97cd4b7c2aa [gcc]
new 6d8efcd4440 Implement LWG 2485
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libstdc++-v3/ChangeLog | 24 +++++++++++++++++++++
libstdc++-v3/include/debug/array | 8 +++++++
libstdc++-v3/include/std/array | 8 +++++++
libstdc++-v3/include/std/tuple | 16 ++++++++++++++
libstdc++-v3/include/std/utility | 25 ++++++++++++++++++++++
libstdc++-v3/testsuite/20_util/pair/astuple/get.cc | 5 +++++
.../testsuite/20_util/pair/astuple/get_by_type.cc | 7 ++++++
.../testsuite/20_util/tuple/element_access/get2.cc | 15 +++++++++++++
.../20_util/tuple/element_access/get2_by_type.cc | 18 ++++++++++++++++
.../23_containers/array/tuple_interface/get.cc | 5 +++++
.../tuple_interface/tuple_element_debug_neg.cc | 2 +-
.../array/tuple_interface/tuple_element_neg.cc | 2 +-
12 files changed, 133 insertions(+), 2 deletions(-)
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unknown user pushed a change to branch master
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from 3db281db106 [GlobalISel|ARM] : Allow legalizing G_FSUB
new 4d7518052e4 [Hexagon] Allow the RDF optimizations to be run in .mir testcases
new 4ccf677f27f [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector lo [...]
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include/llvm/Analysis/TargetTransformInfo.h | 17 +-
include/llvm/Analysis/TargetTransformInfoImpl.h | 5 +-
lib/Analysis/TargetTransformInfo.cpp | 5 +-
lib/CodeGen/CodeGenPrepare.cpp | 51 +--
lib/Target/Hexagon/HexagonRDFOpt.cpp | 10 +-
lib/Target/Hexagon/HexagonTargetMachine.cpp | 2 +
lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 14 +-
lib/Target/PowerPC/PPCTargetTransformInfo.h | 3 +-
lib/Target/X86/X86TargetTransformInfo.cpp | 33 +-
lib/Target/X86/X86TargetTransformInfo.h | 3 +-
lib/Transforms/Scalar/MergeICmps.cpp | 3 +-
test/CodeGen/X86/memcmp-optsize.ll | 381 ++++++++++++++-----
test/CodeGen/X86/memcmp.ll | 482 +++++++++++++++++-------
test/Transforms/CodeGenPrepare/X86/memcmp.ll | 28 +-
14 files changed, 737 insertions(+), 300 deletions(-)
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