Tcwg-commits September 2016

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[toolchain/gcc] branch linaro-local/gcc-6-integration-branch updated (a1d0b72 -> eed9c6d)

by Yvan Roux

8 years, 2 months

[llvm] branch master updated (bda8c85 -> e888613)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from bda8c85 [AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit [...] new e888613 [X86] Make some static arrays of opcodes const and shrink to [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86FastISel.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 years, 2 months

[llvm] branch master updated (ac396ea -> bda8c85)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from ac396ea [Coroutines] Part11: Add final suspend handling. new 481ecf2 [Target] Remove the AvailableRegClasses vector from TargetLow [...] new bda8c85 [AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/Target/TargetLowering.h | 4 -- lib/Target/X86/X86InstrInfo.cpp | 27 +++------- lib/Target/X86/X86RegisterInfo.cpp | 10 ---- lib/Target/X86/X86RegisterInfo.h | 3 -- test/CodeGen/X86/avx512-calling-conv.ll | 27 ++++------ test/CodeGen/X86/avx512-ext.ll | 8 +-- test/CodeGen/X86/avx512-intrinsics.ll | 90 +++++++++++++++---------------- test/CodeGen/X86/avx512-mask-op.ll | 2 +- test/CodeGen/X86/avx512-select.ll | 4 +- test/CodeGen/X86/avx512-vbroadcast.ll | 4 +- test/CodeGen/X86/masked_gather_scatter.ll | 36 ++++++------- test/CodeGen/X86/masked_memop.ll | 4 +- test/CodeGen/X86/pmul.ll | 61 +++++++-------------- test/CodeGen/X86/vector-sext.ll | 2 +- test/CodeGen/X86/vector-zext.ll | 2 +- 15 files changed, 112 insertions(+), 172 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 years, 2 months

[toolchain/gcc] branch linaro-local/gcc-6-integration-branch updated (b6686e2 -> a1d0b72)

by Yvan Roux

This is an automated email from the git hooks/post-receive script. Yvan Roux pushed a change to branch linaro-local/gcc-6-integration-branch in repository toolchain/gcc. from b6686e2 gcc/ Backport from trunk r237988. 2016-07-04 Jiong Wang [...] new a1d0b72 gcc/ Backport from trunk r239739. 2016-08-24 Michael Coll [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/arm/arm-modes.def | 1 + gcc/config/arm/arm-protos.h | 2 + gcc/config/arm/arm.c | 29 +++ gcc/config/arm/arm.md | 325 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/builtin_saddl.c | 17 ++ gcc/testsuite/gcc.target/arm/builtin_saddll.c | 18 ++ gcc/testsuite/gcc.target/arm/builtin_ssubl.c | 17 ++ gcc/testsuite/gcc.target/arm/builtin_ssubll.c | 18 ++ gcc/testsuite/gcc.target/arm/builtin_uaddl.c | 17 ++ gcc/testsuite/gcc.target/arm/builtin_uaddll.c | 18 ++ gcc/testsuite/gcc.target/arm/builtin_usubl.c | 17 ++ gcc/testsuite/gcc.target/arm/builtin_usubll.c | 18 ++ 12 files changed, 497 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/builtin_saddl.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_saddll.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_ssubl.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_ssubll.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_uaddl.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_uaddll.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_usubl.c create mode 100644 gcc/testsuite/gcc.target/arm/builtin_usubll.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 years, 2 months

[toolchain/gcc] branch linaro-local/gcc-6-integration-branch updated (94d916d -> b6686e2)

by Yvan Roux

8 years, 2 months

[toolchain/gcc] branch linaro-local/gcc-6-integration-branch updated (ca4e6a6 -> 94d916d)

by Yvan Roux

This is an automated email from the git hooks/post-receive script. Yvan Roux pushed a change to branch linaro-local/gcc-6-integration-branch in repository toolchain/gcc. from ca4e6a6 gcc/testsuite/ Backport from trunk r237987. 2016-07-04 Ch [...] new 94d916d gcc/testsuite/ Backport from trunk r237798. 2016-06-27 Ch [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../aarch64/advsimd-intrinsics/vget_lane.c | 2 + .../advsimd-intrinsics/vld2_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vld2q_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vld3_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vld3q_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vld4_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vld4q_lane_f16_indices_1.c | 1 + .../aarch64/advsimd-intrinsics/vreinterpret.c | 52 +++++++++++++++++++++- .../aarch64/advsimd-intrinsics/vreinterpret_p128.c | 6 +++ .../aarch64/advsimd-intrinsics/vreinterpret_p64.c | 10 +++++ .../advsimd-intrinsics/vst2_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vst2q_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vst3_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vst3q_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vst4_lane_f16_indices_1.c | 1 + .../advsimd-intrinsics/vst4q_lane_f16_indices_1.c | 1 + .../aarch64/advsimd-intrinsics/vstX_lane.c | 6 +++ 17 files changed, 87 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 years, 2 months

[toolchain/gcc] branch linaro-local/gcc-6-integration-branch updated (bb27c38 -> ca4e6a6)

by Yvan Roux

8 years, 2 months

[toolchain/gcc] branch linaro-local/gcc-6-integration-branch updated (b9ee8ff -> bb27c38)

by Yvan Roux

8 years, 2 months

[llvm] branch master updated (384a721 -> ac396ea)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 384a721 [X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. new ac396ea [Coroutines] Part11: Add final suspend handling. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Transforms/Coroutines/CoroEarly.cpp | 33 +++++++++++-- lib/Transforms/Coroutines/CoroSplit.cpp | 59 +++++++++++++++++++++-- lib/Transforms/Coroutines/Coroutines.cpp | 18 +++---- test/Transforms/Coroutines/{ex3.ll => ex5.ll} | 69 ++++++++++++++++----------- 4 files changed, 134 insertions(+), 45 deletions(-) copy test/Transforms/Coroutines/{ex3.ll => ex5.ll} (51%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 years, 2 months

[llvm] branch master updated (d02e8e5 -> 384a721)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from d02e8e5 [CMake] [OCaml] Allow building OCaml bindings out of tree. new bfa3e95 [X86] Remove FsVMOVAPSrm/FsVMOVAPDrm/FsMOVAPSrm/FsMOVAPDrm. D [...] new 384a721 [X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86InstrFragmentsSIMD.td | 5 -- lib/Target/X86/X86InstrInfo.cpp | 12 --- lib/Target/X86/X86InstrSSE.td | 23 ------ test/CodeGen/X86/vec_ss_load_fold.ll | 130 ++++++++++++++++++++++++++++++++ 4 files changed, 130 insertions(+), 40 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

8 years, 2 months

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Tcwg-commits September 2016