In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: stable@vger.kernel.org Signed-off-by: Ley Foon Tan leyfoon.tan@starfivetech.com
--- v3: Resolved comment from Samuel Holland. - Function riscv_clock_event_stop() needs to be called before clockevents_config_and_register(), move riscv_clock_event_stop().
v2: Resolved comments from Anup. - Moved riscv_clock_event_stop() to riscv_timer_starting_cpu(). - Added Fixes tag --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..79bb9a98baa7 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
+ /* Clear timer interrupt */ + riscv_clock_event_stop(); + ce->cpumask = cpumask_of(cpu); ce->irq = riscv_clock_event_irq; if (riscv_timer_cannot_wake_cpu)
On 2024-03-06 11:23 AM, Ley Foon Tan wrote:
In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: stable@vger.kernel.org Signed-off-by: Ley Foon Tan leyfoon.tan@starfivetech.com
v3: Resolved comment from Samuel Holland.
- Function riscv_clock_event_stop() needs to be called before clockevents_config_and_register(), move riscv_clock_event_stop().
v2: Resolved comments from Anup.
- Moved riscv_clock_event_stop() to riscv_timer_starting_cpu().
- Added Fixes tag
drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+)
Reviewed-by: Samuel Holland samuel.holland@sifive.com Tested-by: Samuel Holland samuel.holland@sifive.com
On Tue, Mar 12, 2024 at 10:40 AM Samuel Holland samuel.holland@sifive.com wrote:
On 2024-03-06 11:23 AM, Ley Foon Tan wrote:
In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: stable@vger.kernel.org Signed-off-by: Ley Foon Tan leyfoon.tan@starfivetech.com
v3: Resolved comment from Samuel Holland.
- Function riscv_clock_event_stop() needs to be called before clockevents_config_and_register(), move riscv_clock_event_stop().
v2: Resolved comments from Anup.
- Moved riscv_clock_event_stop() to riscv_timer_starting_cpu().
- Added Fixes tag
drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+)
Reviewed-by: Samuel Holland samuel.holland@sifive.com Tested-by: Samuel Holland samuel.holland@sifive.com
Reviewed-by: Atish Patra atishp@rivosinc.com
On 06/03/2024 18:23, Ley Foon Tan wrote:
In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: stable@vger.kernel.org Signed-off-by: Ley Foon Tan leyfoon.tan@starfivetech.com
Applied, thanks
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 8248ca30ef89f9cc74ace62ae1b9a22b5f16736c Gitweb: https://git.kernel.org/tip/8248ca30ef89f9cc74ace62ae1b9a22b5f16736c Author: Ley Foon Tan leyfoon.tan@starfivetech.com AuthorDate: Thu, 07 Mar 2024 01:23:30 +08:00 Committer: Daniel Lezcano daniel.lezcano@linaro.org CommitterDate: Wed, 13 Mar 2024 12:08:59 +01:00
clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization
In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value.
Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: stable@vger.kernel.org Signed-off-by: Ley Foon Tan leyfoon.tan@starfivetech.com Reviewed-by: Samuel Holland samuel.holland@sifive.com Tested-by: Samuel Holland samuel.holland@sifive.com Reviewed-by: Atish Patra atishp@rivosinc.com Signed-off-by: Daniel Lezcano daniel.lezcano@linaro.org Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.c... --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd..79bb9a9 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
+ /* Clear timer interrupt */ + riscv_clock_event_stop(); + ce->cpumask = cpumask_of(cpu); ce->irq = riscv_clock_event_irq; if (riscv_timer_cannot_wake_cpu)
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