This reverts commit 5b7a256c982636ebc4f16b708b40ff56d33c8a86.

Since, we now have an actual fix for this issue, we can get rid of this workaround as it can cause pin failures if enough VRAM isn't carved out by the BIOS.

Cc: stable@vger.kernel.org # 6.1+ Signed-off-by: Hamza Mahfooz hamza.mahfooz@amd.com --- v2: new to the series --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 ------------------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++-- 3 files changed, 3 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 83a9607a87b8..3a86d11d1605 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1316,7 +1316,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); int amdgpu_device_pci_reset(struct amdgpu_device *adev); bool amdgpu_device_need_post(struct amdgpu_device *adev); -bool amdgpu_sg_display_supported(struct amdgpu_device *adev); bool amdgpu_device_pcie_dynamic_switching_supported(void); bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); bool amdgpu_device_aspm_support_quirk(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5f32e8d4f3d3..3d540b0cf0e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1358,32 +1358,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) return true; }

-/* - * On APUs with >= 64GB white flickering has been observed w/ SG enabled. - * Disable S/G on such systems until we have a proper fix. - * https://gitlab.freedesktop.org/drm/amd/-/issues/2354 - * https://gitlab.freedesktop.org/drm/amd/-/issues/2735 - */ -bool amdgpu_sg_display_supported(struct amdgpu_device *adev) -{ - switch (amdgpu_sg_display) { - case -1: - break; - case 0: - return false; - case 1: - return true; - default: - return false; - } - if ((totalram_pages() << (PAGE_SHIFT - 10)) + - (adev->gmc.real_vram_size / 1024) >= 64000000) { - DRM_WARN("Disabling S/G due to >=64GB RAM\n"); - return false; - } - return true; -} - /* * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic * speed switching. Until we have confirmation from Intel that a specific host diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5f14cd9391ca..740a6fcafe4c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1654,8 +1654,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) } break; } - if (init_data.flags.gpu_vm_support) - init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev); + if (init_data.flags.gpu_vm_support && + (amdgpu_sg_display == 0)) + init_data.flags.gpu_vm_support = false;

if (init_data.flags.gpu_vm_support) adev->mode_info.gpu_vm_support = true;

Series is: Reviewed-by: Alex Deucher alexander.deucher@amd.com

On Fri, Sep 8, 2023 at 10:56 AM Hamza Mahfooz hamza.mahfooz@amd.com wrote:

From: Yifan Zhang yifan1.zhang@amd.com

Dropping bit 31:4 of page table base is wrong, it makes page table base points to wrong address if phys addr is beyond 64GB; dropping page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup will do that. Also, while we are at it, cleanup the assignments using upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT.

Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") Signed-off-by: Yifan Zhang yifan1.zhang@amd.com Signed-off-by: Hamza Mahfooz hamza.mahfooz@amd.com

---

v2: use upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1bb1a394f55f..5f14cd9391ca 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1283,11 +1283,15 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_

    pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

•   page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
  

•   page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
  

•   page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
  

•   page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
  

•   page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
  

•   page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
  

•                                              AMDGPU_GPU_PAGE_SHIFT);
  

•   page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
  

•                                             AMDGPU_GPU_PAGE_SHIFT);
  

•   page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
  

•                                            AMDGPU_GPU_PAGE_SHIFT);
  

•   page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
  

•                                           AMDGPU_GPU_PAGE_SHIFT);
  

•   page_table_base.high_part = upper_32_bits(pt_base);
    page_table_base.low_part = lower_32_bits(pt_base);
  
    pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
  

-- 2.41.0