On Tue, Feb 25, 2025 at 11:02 AM Claudiu claudiu.beznea@tuxon.dev wrote:

From: Claudiu Beznea claudiu.beznea.uj@bp.renesas.com

phy-rcar-gen3-usb2 driver exports 4 PHYs. The timing registers are common to all PHYs. There is no need to set them every time a PHY is initialized. Set timing register only when the 1st PHY is initialized.

Fixes: f3b5a8d9b50d ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver") Cc: stable@vger.kernel.org Reviewed-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com Tested-by: Yoshihiro Shimoda yoshihiro.shimoda.uh@renesas.com Signed-off-by: Claudiu Beznea claudiu.beznea.uj@bp.renesas.com

---

Changes in v2:

• collected tags

drivers/phy/renesas/phy-rcar-gen3-usb2.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)

Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com

Cheers, Prabhakar

diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 21cf14ea3437..a89621d3f94b 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -467,8 +467,11 @@ static int rcar_gen3_phy_usb2_init(struct phy *p) val = readl(usb2_base + USB2_INT_ENABLE); val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits; writel(val, usb2_base + USB2_INT_ENABLE);

•   writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
  

•   writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
  

•   if (!rcar_gen3_is_any_rphy_initialized(channel)) {
  

•           writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
  

•           writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
  

•   }
  
    /* Initialize otg part (only if we initialize a PHY with IRQs). */
    if (rphy->int_enable_bits)
  

-- 2.43.0