Changes since v2 [1]: - Rework some of the changelogs per feedback (Bjorn, and I) - Move the cxl_register_map refactor earlier in the series to make the cxl_setup_pci_regs() refactor easier to read. - Fix a bug added in v5.14 for handling the error return case cxl_pci_map_regblock() - Split the addition of @base to cxl_register_map to its own patch - Drop the cxl_pci_dvsec() wrapper (Christoph) - Drop the SIOV conversion patch given Baolu's feedback about it being dead code
[1]: https://lore.kernel.org/r/20210923172647.72738-1-ben.widawsky@intel.com
--- I am helping out with the review feedback on this set while Ben is focusing on region provisioning. It appears this rework will be suitable to just carry in cxl/next, no need to make a cross-tree dependency for "PCI: Add pci_find_dvsec_capability to find designated VSEC" at this time.
Ben's original cover:
Provide the ability to obtain CXL register blocks as discrete functionality. This functionality will become useful for other CXL drivers that need access to CXL register blocks. It is also in line with other additions to core which moves register mapping functionality.
At the introduction of the CXL driver the only user of CXL MMIO was cxl_pci (then known as cxl_mem). As the driver has evolved it is clear that cxl_pci will not be the only entity that needs access to CXL MMIO. This series stops short of moving the generalized functionality into cxl_core for the sake of getting eyes on the important foundational bits sooner rather than later. The ultimate plan is to move much of the code into cxl_core.
Via review of two previous patches [1] & [2] it has been suggested that the bits which are being used for DVSEC enumeration move into PCI core. As CXL core is soon going to require these, let's try to get the ball rolling now on making that happen.
---
[1]: https://lore.kernel.org/linux-pci/20210913190131.xiiszmno46qie7v5@intel.com/ [2]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@inte... [3]: https://lore.kernel.org/linux-cxl/20210921220459.2437386-1-ben.widawsky@inte...
---
Ben Widawsky (8): cxl/pci: Convert register block identifiers to an enum cxl/pci: Remove dev_dbg for unknown register blocks cxl/pci: Remove pci request/release regions cxl/pci: Make more use of cxl_register_map cxl/pci: Split cxl_pci_setup_regs() PCI: Add pci_find_dvsec_capability to find designated VSEC cxl/pci: Use pci core's DVSEC functionality ocxl: Use pci core's DVSEC functionality
Dan Williams (2): cxl/pci: Fix NULL vs ERR_PTR confusion cxl/pci: Add @base to cxl_register_map
arch/powerpc/platforms/powernv/ocxl.c | 3 - drivers/cxl/cxl.h | 1 drivers/cxl/pci.c | 157 +++++++++++++-------------------- drivers/cxl/pci.h | 14 ++- drivers/misc/ocxl/config.c | 13 --- drivers/pci/pci.c | 32 +++++++ include/linux/pci.h | 1 7 files changed, 105 insertions(+), 116 deletions(-)
base-commit: ed97afb53365cd03dde266c9644334a558fe5a16
cxl_pci_map_regblock() may return an ERR_PTR(), but cxl_pci_setup_regs() is only prepared for NULL as the error case.
Fixes: f8a7e8c29be8 ("cxl/pci: Reserve all device regions at once") Cc: stable@vger.kernel.org Cc: Jonathan Cameron Jonathan.Cameron@huawei.com Cc: Ira Weiny ira.weiny@intel.com Signed-off-by: Dan Williams dan.j.williams@intel.com --- drivers/cxl/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ccc7c2573ddc..9c178002d49e 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -317,7 +317,7 @@ static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm, if (pci_resource_len(pdev, bar) < offset) { dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, &pdev->resource[bar], (unsigned long long)offset); - return IOMEM_ERR_PTR(-ENXIO); + return NULL; }
addr = pci_iomap(pdev, bar, 0);
On Sat, Oct 09, 2021 at 09:44:13AM -0700, Dan Williams wrote:
cxl_pci_map_regblock() may return an ERR_PTR(), but cxl_pci_setup_regs() is only prepared for NULL as the error case.
Fixes: f8a7e8c29be8 ("cxl/pci: Reserve all device regions at once") Cc: stable@vger.kernel.org Cc: Jonathan Cameron Jonathan.Cameron@huawei.com Cc: Ira Weiny ira.weiny@intel.com
Reviewed-by: Ira Weiny ira.weiny@intel.com
Signed-off-by: Dan Williams dan.j.williams@intel.com
drivers/cxl/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ccc7c2573ddc..9c178002d49e 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -317,7 +317,7 @@ static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm, if (pci_resource_len(pdev, bar) < offset) { dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, &pdev->resource[bar], (unsigned long long)offset);
return IOMEM_ERR_PTR(-ENXIO);
return NULL;addr = pci_iomap(pdev, bar, 0);
On Sat, 9 Oct 2021 09:44:13 -0700 Dan Williams dan.j.williams@intel.com wrote:
cxl_pci_map_regblock() may return an ERR_PTR(), but cxl_pci_setup_regs() is only prepared for NULL as the error case.
What's the logic behind doing this rather than adjusting the call site to check for an error pointer?
Either approach is fine as far as I'm concerned though so this is really just a request for a bit more info in this patch description.
FWIW
Reviewed-by: Jonathan Cameron Jonathan.Cameron@huawei.com
Fixes: f8a7e8c29be8 ("cxl/pci: Reserve all device regions at once") Cc: stable@vger.kernel.org Cc: Jonathan Cameron Jonathan.Cameron@huawei.com Cc: Ira Weiny ira.weiny@intel.com Signed-off-by: Dan Williams dan.j.williams@intel.com
drivers/cxl/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ccc7c2573ddc..9c178002d49e 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -317,7 +317,7 @@ static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm, if (pci_resource_len(pdev, bar) < offset) { dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, &pdev->resource[bar], (unsigned long long)offset);
return IOMEM_ERR_PTR(-ENXIO);
return NULL;addr = pci_iomap(pdev, bar, 0);
On Fri, Oct 15, 2021 at 9:16 AM Jonathan Cameron Jonathan.Cameron@huawei.com wrote:
On Sat, 9 Oct 2021 09:44:13 -0700 Dan Williams dan.j.williams@intel.com wrote:
cxl_pci_map_regblock() may return an ERR_PTR(), but cxl_pci_setup_regs() is only prepared for NULL as the error case.
What's the logic behind doing this rather than adjusting the call site to check for an error pointer?
Minimize the fix for the stable backport. In the later patches the cxl_pci_map_regblock() => cxl_map_regblock() conversion goes from returning a pointer to an error code.
Either approach is fine as far as I'm concerned though so this is really just a request for a bit more info in this patch description.
I can include that note above to clarify.
FWIW
Reviewed-by: Jonathan Cameron Jonathan.Cameron@huawei.com
Thanks.
cxl_pci_map_regblock() may return an ERR_PTR(), but cxl_pci_setup_regs() is only prepared for NULL as the error case. Pick the minimal fix for -stable backport purposes and just have cxl_pci_map_regblock() return NULL for errors.
Fixes: f8a7e8c29be8 ("cxl/pci: Reserve all device regions at once") Cc: stable@vger.kernel.org Reviewed-by: Ira Weiny ira.weiny@intel.com Reviewed-by: Jonathan Cameron Jonathan.Cameron@huawei.com Signed-off-by: Dan Williams dan.j.williams@intel.com --- Changes since v3: - clarify in the changelog why cxl_pci_map_regblock() was changed to return NULL rather than fix the caller to expect an ERR_PTR(). (Jonathan)
drivers/cxl/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ccc7c2573ddc..9c178002d49e 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -317,7 +317,7 @@ static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm, if (pci_resource_len(pdev, bar) < offset) { dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, &pdev->resource[bar], (unsigned long long)offset); - return IOMEM_ERR_PTR(-ENXIO); + return NULL; }
addr = pci_iomap(pdev, bar, 0);
linux-stable-mirror@lists.linaro.org
-
Dan Williams -
Ira Weiny -
Jonathan Cameron