Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. And this would cause kernel to try to enable interrupt line 0, which is not expected. So delete this part from device tree.
Cc: stable@vger.kernel.org Reported-by: Bo Gan ganboing@gmail.com Link: https://lore.kernel.org/all/c8b6e960-2459-130f-e4e4-7c9c2ebaa6d3@gmail.com/ Signed-off-by: Shengyu Qu wiagn233@outlook.com --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 45b58b6f3df8..7783d464d529 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -238,7 +238,6 @@ &i2c5 { axp15060: pmic@36 { compatible = "x-powers,axp15060"; reg = <0x36>; - interrupts = <0>; interrupt-controller; #interrupt-cells = <1>;
On Thu, Mar 07, 2024 at 08:21:12PM +0800, Shengyu Qu wrote:
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. And this would cause kernel to try to enable interrupt line 0, which is not expected. So delete this part from device tree.
Cc: stable@vger.kernel.org Reported-by: Bo Gan ganboing@gmail.com Link: https://lore.kernel.org/all/c8b6e960-2459-130f-e4e4-7c9c2ebaa6d3@gmail.com/ Signed-off-by: Shengyu Qu wiagn233@outlook.com
Thanks for resending. Just to note that I already sent all 6.8 and 6.9 material, so since this is only something that manifests with that "improved" version of OpenSBI I'm gonna pick this up after the merge window.
Fixes: 2378341504de ("riscv: dts: starfive: Enable axp15060 pmic for cpufreq")
And hopefully I remember to re-write the commit message to mention that the board doesn't actually connect the interrupt link to a GPIO etc, so the original patch was invalid and a hack.
I should have rejected it and got the driver fixed at the time to allow not having an interrupt, but clearly I didn't register that that zero was a plic interrupt, not a GPIO.
Thanks, Conor.
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 1 - 1 file changed, 1 deletion(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 45b58b6f3df8..7783d464d529 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -238,7 +238,6 @@ &i2c5 { axp15060: pmic@36 { compatible = "x-powers,axp15060"; reg = <0x36>;
interrupts = <0>;2.39.2
From: Conor Dooley conor.dooley@microchip.com
On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. And this would cause kernel to try to enable interrupt line 0, which is not expected. So delete this part from device tree.
Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote the commit message to add some more information as promised.
[1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board https://git.kernel.org/conor/c/0b163f43920d
Thanks, Conor.
On 3/26/24 1:37 PM, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. And this would cause kernel to try to enable interrupt line 0, which is not expected. So delete this part from device tree.
Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote the commit message to add some more information as promised.
[1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board https://git.kernel.org/conor/c/0b163f43920d
Thanks, Conor.
Hi Conor,
Thank you very much for taking care of this. Actually the PLIC may silently ignore the enablement of interrupt 0, so the upstream openSBI won't notice anything. My modified version, however, will deliberately trigger a fault for all writes to the reserved fields of PLIC, thus catching this issue.
Hope it can clarify things a bit more.
Bo
On Tue, Mar 26, 2024 at 03:06:33PM -0700, Bo Gan wrote:
On 3/26/24 1:37 PM, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. And this would cause kernel to try to enable interrupt line 0, which is not expected. So delete this part from device tree.
Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote the commit message to add some more information as promised.
[1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board https://git.kernel.org/conor/c/0b163f43920d
Thanks, Conor.
Hi Conor,
Thank you very much for taking care of this. Actually the PLIC may silently ignore the enablement of interrupt 0, so the upstream openSBI won't notice anything. My modified version, however, will deliberately trigger a fault for all writes to the reserved fields of PLIC, thus catching this issue.
Hope it can clarify things a bit more.
https://git.kernel.org/conor/c/0f74c64f0a9f
Better?
On 3/26/24 3:10 PM, Conor Dooley wrote:
On Tue, Mar 26, 2024 at 03:06:33PM -0700, Bo Gan wrote:
On 3/26/24 1:37 PM, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. And this would cause kernel to try to enable interrupt line 0, which is not expected. So delete this part from device tree.
Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote the commit message to add some more information as promised.
[1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board https://git.kernel.org/conor/c/0b163f43920d
Thanks, Conor.
Hi Conor,
Thank you very much for taking care of this. Actually the PLIC may silently ignore the enablement of interrupt 0, so the upstream openSBI won't notice anything. My modified version, however, will deliberately trigger a fault for all writes to the reserved fields of PLIC, thus catching this issue.
Hope it can clarify things a bit more.
https://git.kernel.org/conor/c/0f74c64f0a9f
Better?
Great! Thanks again.
Bo
linux-stable-mirror@lists.linaro.org
-
Bo Gan -
Conor Dooley -
Shengyu Qu