From: Jakob Unterwurzacher jakob.unterwurzacher@cherry.de
Hardware CS has a very slow rise time of about 6us, causing transmission errors when CS does not reach high between transaction.
It looks like it's not driven actively when transitioning from low to high but switched to input, so only the CPU pull-up pulls it high, slowly. Transitions from high to low are fast. On the oscilloscope, CS looks like an irregular sawtooth pattern like this: _____ ^ / | ^ /| / | /| / | / | / | / | / | ___/ |___/ |_____/ |___
With cs-gpios we have a CS rise time of about 20ns, as it should be, and CS looks rectangular.
This fixes the data errors when running a flashcp loop against a m25p40 spi flash.
With the Rockchip 6.1 kernel we see the same slow rise time, but for some reason CS is always high for long enough to reach a solid high.
The RK3399 and RK3588 SoCs use the same SPI driver, so we also checked our "Puma" (RK3399) and "Tiger" (RK3588) boards. They do not have this problem. Hardware CS rise time is good.
Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Cc: stable@vger.kernel.org Reviewed-by: Quentin Schulz quentin.schulz@cherry.de Signed-off-by: Jakob Unterwurzacher jakob.unterwurzacher@cherry.de --- .../boot/dts/rockchip/px30-ringneck.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi index ab232e5c7ad6..dcc62dd9b894 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -379,6 +379,18 @@ pmic_int: pmic-int { <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + spi1 { + spi1_csn0_gpio: spi1-csn0-gpio { + rockchip,pins = + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + + spi1_csn1_gpio: spi1-csn1-gpio { + rockchip,pins = + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; };
&pmu_io_domains { @@ -396,6 +408,16 @@ &sdmmc { vqmmc-supply = <&vccio_sd>; };
+&spi1 { + /* + * Hardware CS has a very slow rise time of about 6us, + * causing transmission errors. + * With cs-gpios we have a rise time of about 20ns. + */ + cs-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>, <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi1_clk &spi1_csn0_gpio &spi1_csn1_gpio &spi1_miso &spi1_mosi>; +}; + &tsadc { status = "okay"; };
On Fri, 20 Jun 2025 13:35:46 +0200, Jakob Unterwurzacher wrote:
From: Jakob Unterwurzacher jakob.unterwurzacher@cherry.de
Hardware CS has a very slow rise time of about 6us, causing transmission errors when CS does not reach high between transaction.
It looks like it's not driven actively when transitioning from low to high but switched to input, so only the CPU pull-up pulls it high, slowly. Transitions from high to low are fast. On the oscilloscope, CS looks like an irregular sawtooth pattern like this: _____ ^ / | ^ /| / | /| / | / | / | / | / | ___/ |___/ |_____/ |___
With cs-gpios we have a CS rise time of about 20ns, as it should be, and CS looks rectangular.
This fixes the data errors when running a flashcp loop against a m25p40 spi flash.
With the Rockchip 6.1 kernel we see the same slow rise time, but for some reason CS is always high for long enough to reach a solid high.
The RK3399 and RK3588 SoCs use the same SPI driver, so we also checked our "Puma" (RK3399) and "Tiger" (RK3588) boards. They do not have this problem. Hardware CS rise time is good.
Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Cc: stable@vger.kernel.org Reviewed-by: Quentin Schulz quentin.schulz@cherry.de Signed-off-by: Jakob Unterwurzacher jakob.unterwurzacher@cherry.de
.../boot/dts/rockchip/px30-ringneck.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+)
My bot found new DTB warnings on the .dts files added or changed in this series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base: Base: attempting to guess base-commit... Base: tags/next-20250619 (exact match)
If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/rockchip/' for 20250620113549.2900285-1-jakob.unterwurzacher@cherry.de:
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dtb: spi1: spi1-csn0-gpio: {'rockchip,pins': [[3, 9, 0, 150]], 'phandle': 87} is not of type 'array' from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dtb: spi1: spi1-csn1-gpio: {'rockchip,pins': [[3, 10, 0, 150]], 'phandle': 88} is not of type 'array' from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml#
Hi Jakob,
Am Freitag, 20. Juni 2025, 13:35:46 Mitteleuropäische Sommerzeit schrieb Jakob Unterwurzacher:
From: Jakob Unterwurzacher jakob.unterwurzacher@cherry.de
Hardware CS has a very slow rise time of about 6us, causing transmission errors when CS does not reach high between transaction.
It looks like it's not driven actively when transitioning from low to high but switched to input, so only the CPU pull-up pulls it high, slowly. Transitions from high to low are fast. On the oscilloscope, CS looks like an irregular sawtooth pattern like this: _____ ^ / | ^ /| / | /| / | / | / | / | / | ___/ |___/ |_____/ |___
With cs-gpios we have a CS rise time of about 20ns, as it should be, and CS looks rectangular.
This fixes the data errors when running a flashcp loop against a m25p40 spi flash.
With the Rockchip 6.1 kernel we see the same slow rise time, but for some reason CS is always high for long enough to reach a solid high.
The RK3399 and RK3588 SoCs use the same SPI driver, so we also checked our "Puma" (RK3399) and "Tiger" (RK3588) boards. They do not have this problem. Hardware CS rise time is good.
Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Cc: stable@vger.kernel.org Reviewed-by: Quentin Schulz quentin.schulz@cherry.de Signed-off-by: Jakob Unterwurzacher jakob.unterwurzacher@cherry.de
.../boot/dts/rockchip/px30-ringneck.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi index ab232e5c7ad6..dcc62dd9b894 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -379,6 +379,18 @@ pmic_int: pmic-int { <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; }; };
- spi1 {
spi1_csn0_gpio: spi1-csn0-gpio {rockchip,pins =<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up_4ma>;};spi1_csn1_gpio: spi1-csn1-gpio {
naming the node -gpio trigger the bot, I guess a better name would be something with -pin at the end instead.
+&spi1 {
- /*
* Hardware CS has a very slow rise time of about 6us,* causing transmission errors.* With cs-gpios we have a rise time of about 20ns.*/- cs-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>, <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
please also provide a pinctrl-names = "default" here. It feels more futur proof when overriding the pinctrl-0 entry to also state we only expect that one.
- pinctrl-0 = <&spi1_clk &spi1_csn0_gpio &spi1_csn1_gpio &spi1_miso &spi1_mosi>;
+};
&tsadc { status = "okay"; };
linux-stable-mirror@lists.linaro.org
-
Heiko Stuebner -
Jakob Unterwurzacher -
Rob Herring (Arm)