This fixes incorrect pinmux on UART0 and UART5 for PX30 Ringneck on Haikou.
Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- Changes in v3: - removed already merged patches (Device Tree overlays), - rebased on top of master to avoid conflicts, - added comment above pinctrl-0 in uart5 to explain we are only adding a pinmux and not modifying anything else, - Link to v2: https://lore.kernel.org/r/20250221-ringneck-dtbos-v2-0-310c0b9a3909@cherry.d...
Changes in v2: - rename uart5_rts_gpio to uart5_rts_pin to stop triggering a false positive of the dtschema checker, - remove PU from uart5_rts_pin, - Link to v1: https://lore.kernel.org/r/20250220-ringneck-dtbos-v1-0-25c97f2385e6@cherry.d...
--- Quentin Schulz (2): arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou arm64: dts: rockchip: fix pinmux of UART5 for PX30 Ringneck on Haikou
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) --- base-commit: d082ecbc71e9e0bf49883ee4afd435a77a5101b6 change-id: 20250128-ringneck-dtbos-98064839355e
Best regards,
From: Quentin Schulz quentin.schulz@cherry.de
UART0 pinmux by default configures GPIO0_B5 in its UART RTS function for UART0. However, by default on Haikou, it is used as GPIO as UART RTS for UART5.
Therefore, let's update UART0 pinmux to not configure the pin in that mode, a later commit will make UART5 request the GPIO pinmux.
Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts index eb9470a00e549fc107603be216a5f714914e7a2c..9a568f3d0a9916dff22222c59e5e0c94ce226858 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -222,6 +222,7 @@ &u2phy_otg { };
&uart0 { + pinctrl-0 = <&uart0_xfer>; status = "okay"; };
From: Quentin Schulz quentin.schulz@cherry.de
UART5 uses GPIO0_B5 as UART RTS but muxed in its GPIO function, therefore UART5 must request this pin to be muxed in that function, so let's do that.
Fixes: 5963d97aa780 ("arm64: dts: rockchip: add rs485 support on uart5 of px30-ringneck-haikou") Cc: stable@vger.kernel.org Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts index 9a568f3d0a9916dff22222c59e5e0c94ce226858..0e0d7b755b8733ff03083665f76807cc6954ca3e 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -194,6 +194,13 @@ sd_card_led_pin: sd-card-led-pin { <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + uart { + uart5_rts_pin: uart5-rts-pin { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; };
&pwm0 { @@ -227,6 +234,8 @@ &uart0 { };
&uart5 { + /* Add pinmux for rts-gpios (uart5_rts_pin) */ + pinctrl-0 = <&uart5_xfer &uart5_rts_pin>; rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status = "okay"; };
On Tue, 25 Feb 2025 12:53:28 +0100, Quentin Schulz wrote:
This fixes incorrect pinmux on UART0 and UART5 for PX30 Ringneck on Haikou.
Applied, thanks!
[1/2] arm64: dts: rockchip: fix pinmux of UART0 for PX30 Ringneck on Haikou commit: 2db7d29c7b1629ced3cbab3de242511eb3c22066 [2/2] arm64: dts: rockchip: fix pinmux of UART5 for PX30 Ringneck on Haikou commit: 55de171bba1b8c0e3dd18b800955ac4b46a63d4b
Best regards,
linux-stable-mirror@lists.linaro.org
-
Heiko Stuebner -
Quentin Schulz