On Tue, Apr 02, 2024 at 11:41:34PM +0200, Christian Marangi wrote:

misc_cmd_type in exec_op have multiple problems. With commit a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path") it was reworked and generalized but actually dropped the handling of the OP_RESET_DEVICE command.

The rework itself was correct with supporting case where a single misc command is handled, but became problematic by the addition of exiting early if we didn't had an OP_BLOCK_ERASE or an OP_PROGRAM_PAGE operation.

Also additional logic was added without clear explaination causing the OP_RESET_DEVICE command to be broken on testing it on a ipq806x nandc.

Add some additional logic to restore OP_RESET_DEVICE command handling restoring original functionality.

I'd like to reword the commit subject and description as below. But I hope Miquel can ammend it while applying:

"mtd: rawnand: qcom: Fix broken OP_RESET_DEVICE command in qcom_misc_cmd_type_exec()

While migrating to exec_ops in commit a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path"), OP_RESET_DEVICE command handling got broken unintentionally. Right now for the OP_RESET_DEVICE command, qcom_misc_cmd_type_exec() will simply return 0 without handling it. Even, if that gets fixed, an unnecessary FLASH_STATUS read descriptor command is being added in the middle and that seems to be causing the command to fail on IPQ806x devices.

So let's fix the above two issues to make OP_RESET_DEVICE command working again."

Fixes: a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path") Cc: stable@vger.kernel.org Signed-off-by: Christian Marangi ansuelsmth@gmail.com

With the above change,

Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

- Mani

---

Changes v3:

• Merge patches
• Rework commit description

Changes v2:

• Split patches

drivers/mtd/nand/raw/qcom_nandc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index b079605c84d3..b8cff9240b28 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2815,7 +2815,7 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub host->cfg0_raw & ~(7 << CW_PER_PAGE)); nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); instrs = 3;

• } else {

• } else if (q_op.cmd_reg != OP_RESET_DEVICE) { return 0; }

@@ -2830,9 +2830,8 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub nandc_set_reg(chip, NAND_EXEC_CMD, 1); write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);

• (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0,
• 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc,
• NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);

• if (q_op.cmd_reg == OP_BLOCK_ERASE)

• write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
  

write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); -- 2.43.0