One layout supported by the Marvell NAND controller supports NAND pages of 2048 bytes, all handled in one single chunk when using BCH with a strength of 4-bit per 512 bytes. In this case, instead of the generic XTYPE_WRITE_DISPATCH/XTYPE_LAST_NAKED_RW couple, the controller expects to receive XTYPE_MONOLITHIC_RW.
This fixes problems at boot like:
[ 1.315475] Scanning device for bad blocks [ 3.203108] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 3.209564] nand_bbt: error while writing BBT block -110 [ 4.243106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.283106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.289562] nand_bbt: error -110 while marking block 2047 bad [ 6.323106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 6.329559] nand_bbt: error while writing BBT block -110 [ 7.363106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.403105] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.409559] nand_bbt: error -110 while marking block 2046 bad ...
Fixes: 02f26ecf8c772 ("mtd: nand: add reworked Marvell NAND controller driver") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com ---
Chris,
Can you please give this patch a try? This is very likely to solve your boot issue.
Thanks, Miquèl
drivers/mtd/nand/raw/marvell_nand.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index e4b964fd40d8..db5ec4e8bde9 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -1408,6 +1408,7 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; + u32 xtype; int ret; struct marvell_nfc_op nfc_op = { .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD, @@ -1423,7 +1424,12 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, * last naked write. */ if (chunk == 0) { - nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_WRITE_DISPATCH) | + if (lt->nchunks == 1) + xtype = XTYPE_MONOLITHIC_RW; + else + xtype = XTYPE_WRITE_DISPATCH; + + nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | NDCB0_CMD1(NAND_CMD_SEQIN); nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
Hi Miquel,
On 03/05/18 22:00, Miquel Raynal wrote:
One layout supported by the Marvell NAND controller supports NAND pages of 2048 bytes, all handled in one single chunk when using BCH with a strength of 4-bit per 512 bytes. In this case, instead of the generic XTYPE_WRITE_DISPATCH/XTYPE_LAST_NAKED_RW couple, the controller expects to receive XTYPE_MONOLITHIC_RW.
This fixes problems at boot like:
[ 1.315475] Scanning device for bad blocks [ 3.203108] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 3.209564] nand_bbt: error while writing BBT block -110 [ 4.243106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.283106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.289562] nand_bbt: error -110 while marking block 2047 bad [ 6.323106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 6.329559] nand_bbt: error while writing BBT block -110 [ 7.363106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.403105] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.409559] nand_bbt: error -110 while marking block 2046 bad ...
Fixes: 02f26ecf8c772 ("mtd: nand: add reworked Marvell NAND controller driver") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com
For the following combinations
SoC NAND Size EB Page OOB --- ---- ---- -- ---- --- Armada-385 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224 Armada-385 Micron MT29F2G08ABAEAWP 256 MiB 128 KiB 2048 64 Armada-385 Macronix MX30LF2G18AC 256 MiB 128 KiB 2048 64 Armada-98DX4251 AMD/Spansion S34ML08G2 1024 MiB 128 KiB 2048 128 Armada-98DX4251 Macronix MX60LF8G18AC 1024 MiB 128 KiB 2048 64 Armada-98DX4251 Micron MT29F8G08ABABAWP 1024 MiB 512 KiB 4096 224
Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz
I do have one platform that passes the initial detection but starts to report ubifs errors when mounted.
Armada-98DX4251 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224
This is probably unrelated to this particular fix. It may be as simple as something not catering for the Armada-98DX4251 SoC or a genuine difference between Armada-98DX4251 and Armada-385. 4.16.4 with pxa3xx_nand works with this combination.
Chris,
Can you please give this patch a try? This is very likely to solve your boot issue.
Thanks, Miquèl
drivers/mtd/nand/raw/marvell_nand.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index e4b964fd40d8..db5ec4e8bde9 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -1408,6 +1408,7 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
- u32 xtype; int ret; struct marvell_nfc_op nfc_op = { .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
@@ -1423,7 +1424,12 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, * last naked write. */ if (chunk == 0) {
nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_WRITE_DISPATCH) |
if (lt->nchunks == 1)xtype = XTYPE_MONOLITHIC_RW;elsextype = XTYPE_WRITE_DISPATCH;nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | NDCB0_CMD1(NAND_CMD_SEQIN);
Hi Chris,
On Fri, 4 May 2018 00:06:48 +0000, Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
Hi Miquel,
On 03/05/18 22:00, Miquel Raynal wrote:
One layout supported by the Marvell NAND controller supports NAND pages of 2048 bytes, all handled in one single chunk when using BCH with a strength of 4-bit per 512 bytes. In this case, instead of the generic XTYPE_WRITE_DISPATCH/XTYPE_LAST_NAKED_RW couple, the controller expects to receive XTYPE_MONOLITHIC_RW.
This fixes problems at boot like:
[ 1.315475] Scanning device for bad blocks [ 3.203108] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 3.209564] nand_bbt: error while writing BBT block -110 [ 4.243106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.283106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.289562] nand_bbt: error -110 while marking block 2047 bad [ 6.323106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 6.329559] nand_bbt: error while writing BBT block -110 [ 7.363106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.403105] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.409559] nand_bbt: error -110 while marking block 2046 bad ...
Fixes: 02f26ecf8c772 ("mtd: nand: add reworked Marvell NAND controller driver") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com
For the following combinations
SoC NAND Size EB Page OOB
Armada-385 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224 Armada-385 Micron MT29F2G08ABAEAWP 256 MiB 128 KiB 2048 64 Armada-385 Macronix MX30LF2G18AC 256 MiB 128 KiB 2048 64 Armada-98DX4251 AMD/Spansion S34ML08G2 1024 MiB 128 KiB 2048 128 Armada-98DX4251 Macronix MX60LF8G18AC 1024 MiB 128 KiB 2048 64 Armada-98DX4251 Micron MT29F8G08ABABAWP 1024 MiB 512 KiB 4096 224
Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz
Thank you very much for testing all this!
I do have one platform that passes the initial detection but starts to report ubifs errors when mounted.
Armada-98DX4251 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224
This is probably unrelated to this particular fix. It may be as simple as something not catering for the Armada-98DX4251 SoC or a genuine difference between Armada-98DX4251 and Armada-385. 4.16.4 with pxa3xx_nand works with this combination.
Can you please share more details: the device tree (at least the NAND node), the strength requested, the boot log, the errors?
Are you sure Linux ECC configuration is aligned with the bootloader's?
Thanks, Miquèl
Hi Miquel,
On 04/05/18 19:10, Miquel Raynal wrote:
Hi Chris,
On Fri, 4 May 2018 00:06:48 +0000, Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
I do have one platform that passes the initial detection but starts to report ubifs errors when mounted.
Armada-98DX4251 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224
This is probably unrelated to this particular fix. It may be as simple as something not catering for the Armada-98DX4251 SoC or a genuine difference between Armada-98DX4251 and Armada-385. 4.16.4 with pxa3xx_nand works with this combination.
I did spot a few problems in the pinctrl driver for this platform, but nothing that was stopping things from working (the bootloader set the MPP functions correctly). I've sent some patches for that.
Can you please share more details: the device tree (at least the NAND node), the strength requested, the boot log, the errors?
Here's the relevant part of the device tree
nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <0x1>; #size-cells = <0x1>; interrupts = <0x71>; clocks = <0xc 0x0>; status = "okay"; num-cs = <0x1>; marvell,nand-enable-arbiter; nand-on-flash-bbt; };
...
dfx-server@ac000000 { compatible = "marvell,dfx-server", "simple-bus"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x8000000 0x0 0x100000>; reg = <0x8000000 0x0 0x100000>; phandle = <0xe>;
corediv-clock@f8268 { compatible = "marvell,mv98dx3236-corediv-clock"; reg = <0xf8268 0xc>; #clock-cells = <0x1>; clocks = <0x9>; clock-output-names = "nand"; phandle = <0xc>; }; };
Boot output
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xd3 nand: Micron MT29F8G08ABACAWP nand: 1024 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224 Bad block table found at page 261952, version 0x01 Bad block table found at page 261888, version 0x01 nand_read_bbt: bad block at 0x00003ff80000 nand_read_bbt: bad block at 0x00003ffc0000
Error at mount time
Re-mounting file system... UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 1096 UBIFS error (ubi0:0 pid 1093): check_lpt_type.constprop.6: invalid type (0) in LPT node type 2 CPU: 0 PID: 1093 Comm: mount Not tainted 4.17.0-rc2-at1+ #1 Hardware name: Marvell Armada 370/XP (Device Tree) [<80110f40>] (unwind_backtrace) from [<8010c350>] (show_stack+0x10/0x14) [<8010c350>] (show_stack) from [<805c11b4>] (dump_stack+0x88/0x9c) [<805c11b4>] (dump_stack) from [<802dde14>] (check_lpt_type.constprop.6+0x48/0x50) [<802dde14>] (check_lpt_type.constprop.6) from [<802dfe70>] (ubifs_lpt_init+0x2cc/0x4d8) [<802dfe70>] (ubifs_lpt_init) from [<802c9810>] (ubifs_mount+0x106c/0x1594) [<802c9810>] (ubifs_mount) from [<801ef1dc>] (mount_fs+0x14/0xa4) [<801ef1dc>] (mount_fs) from [<8020a63c>] (vfs_kern_mount+0x4c/0xf4) [<8020a63c>] (vfs_kern_mount) from [<8020d7f0>] (do_mount+0x184/0xb98) [<8020d7f0>] (do_mount) from [<8020e584>] (ksys_mount+0x8c/0xbc) [<8020e584>] (ksys_mount) from [<80101000>] (ret_fast_syscall+0x0/0x54) Exception stack(0xbda63fa8 to 0xbda63ff0) 3fa0: 00000000 00000000 7ea24f4e 7ea24f60 7ea24f48 00008010 3fc0: 00000000 00000000 7ea24f48 00000015 7ea24f4e 00008010 00000000 000a5f44 3fe0: 76e6b1b0 7ea24af0 00046020 76e6b1c0 UBIFS (ubi0:0): background thread "ubifs_bgt0_0" stops mount: mounting ubi0:user on /flash failed: Invalid argument
Are you sure Linux ECC configuration is aligned with the bootloader's?
In this case the bootloader doesn't have any NAND support enabled since this board is always network booting.
It is likely that an older kernel has set this up with ecc-strength=4. Does flash_erase destroy the ecc data as well or is there some other mtd-util to do this from userland?
That got me thinking. I ran with the new driver but the following added to the dts
+ nand-ecc-strength = <4>; + nand-ecc-step-size = <512>;
After an erase/re-init things were working.
But then if I have nothing (auto-select) or nand-ecc-strength = <8> (which would be "correct" for this chip) in the dts I get the errors above.
Thanks, Miquèl
Hi Chris,
On Mon, 7 May 2018 03:48:42 +0000 Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
Hi Miquel,
On 04/05/18 19:10, Miquel Raynal wrote:
Hi Chris,
On Fri, 4 May 2018 00:06:48 +0000, Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
I do have one platform that passes the initial detection but starts to report ubifs errors when mounted.
Armada-98DX4251 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224
This is probably unrelated to this particular fix. It may be as simple as something not catering for the Armada-98DX4251 SoC or a genuine difference between Armada-98DX4251 and Armada-385. 4.16.4 with pxa3xx_nand works with this combination.
I did spot a few problems in the pinctrl driver for this platform, but nothing that was stopping things from working (the bootloader set the MPP functions correctly). I've sent some patches for that.
Can you please share more details: the device tree (at least the NAND node), the strength requested, the boot log, the errors?
Here's the relevant part of the device tree
nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <0x1>; #size-cells = <0x1>; interrupts = <0x71>; clocks = <0xc 0x0>; status = "okay"; num-cs = <0x1>; marvell,nand-enable-arbiter; nand-on-flash-bbt; };
...
dfx-server@ac000000 { compatible = "marvell,dfx-server", "simple-bus"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x8000000 0x0 0x100000>; reg = <0x8000000 0x0 0x100000>; phandle = <0xe>;
corediv-clock@f8268 { compatible = "marvell,mv98dx3236-corediv-clock"; reg = <0xf8268 0xc>; #clock-cells = <0x1>; clocks = <0x9>; clock-output-names = "nand"; phandle = <0xc>; };};
Boot output
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xd3 nand: Micron MT29F8G08ABACAWP nand: 1024 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224 Bad block table found at page 261952, version 0x01 Bad block table found at page 261888, version 0x01 nand_read_bbt: bad block at 0x00003ff80000 nand_read_bbt: bad block at 0x00003ffc0000
Error at mount time
Re-mounting file system... UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 1096 UBIFS error (ubi0:0 pid 1093): check_lpt_type.constprop.6: invalid type (0) in LPT node type 2 CPU: 0 PID: 1093 Comm: mount Not tainted 4.17.0-rc2-at1+ #1 Hardware name: Marvell Armada 370/XP (Device Tree) [<80110f40>] (unwind_backtrace) from [<8010c350>] (show_stack+0x10/0x14) [<8010c350>] (show_stack) from [<805c11b4>] (dump_stack+0x88/0x9c) [<805c11b4>] (dump_stack) from [<802dde14>] (check_lpt_type.constprop.6+0x48/0x50) [<802dde14>] (check_lpt_type.constprop.6) from [<802dfe70>] (ubifs_lpt_init+0x2cc/0x4d8) [<802dfe70>] (ubifs_lpt_init) from [<802c9810>] (ubifs_mount+0x106c/0x1594) [<802c9810>] (ubifs_mount) from [<801ef1dc>] (mount_fs+0x14/0xa4) [<801ef1dc>] (mount_fs) from [<8020a63c>] (vfs_kern_mount+0x4c/0xf4) [<8020a63c>] (vfs_kern_mount) from [<8020d7f0>] (do_mount+0x184/0xb98) [<8020d7f0>] (do_mount) from [<8020e584>] (ksys_mount+0x8c/0xbc) [<8020e584>] (ksys_mount) from [<80101000>] (ret_fast_syscall+0x0/0x54) Exception stack(0xbda63fa8 to 0xbda63ff0) 3fa0: 00000000 00000000 7ea24f4e 7ea24f60 7ea24f48 00008010 3fc0: 00000000 00000000 7ea24f48 00000015 7ea24f4e 00008010 00000000 000a5f44 3fe0: 76e6b1b0 7ea24af0 00046020 76e6b1c0 UBIFS (ubi0:0): background thread "ubifs_bgt0_0" stops mount: mounting ubi0:user on /flash failed: Invalid argument
Can you paste the full boot logs?
Are you sure Linux ECC configuration is aligned with the bootloader's?
In this case the bootloader doesn't have any NAND support enabled since this board is always network booting.
It is likely that an older kernel has set this up with ecc-strength=4. Does flash_erase destroy the ecc data as well or is there some other mtd-util to do this from userland?
There's no metadata describing the ECC setup to use. flash_erase should place the NAND is a clean state.
That got me thinking. I ran with the new driver but the following added to the dts
nand-ecc-strength = <4>;nand-ecc-step-size = <512>;After an erase/re-init things were working.
But then if I have nothing (auto-select) or nand-ecc-strength = <8> (which would be "correct" for this chip) in the dts I get the errors above.
Maybe a problem with the 16bits/1024bytes layout, but what's weird is that the driver does not report ECC errors.
Regards,
Boris
Hi Boris,
Thanks for picking this up while Miquel is taking a break.
On 07/05/18 19:51, Boris Brezillon wrote:
Hi Chris,
On Mon, 7 May 2018 03:48:42 +0000 Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
Hi Miquel,
On 04/05/18 19:10, Miquel Raynal wrote:
Hi Chris,
On Fri, 4 May 2018 00:06:48 +0000, Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
I do have one platform that passes the initial detection but starts to report ubifs errors when mounted.
Armada-98DX4251 Micron MT29F8G08ABACAWP 1024 MiB 256 KiB 4096 224
This is probably unrelated to this particular fix. It may be as simple as something not catering for the Armada-98DX4251 SoC or a genuine difference between Armada-98DX4251 and Armada-385. 4.16.4 with pxa3xx_nand works with this combination.
I did spot a few problems in the pinctrl driver for this platform, but nothing that was stopping things from working (the bootloader set the MPP functions correctly). I've sent some patches for that.
Can you please share more details: the device tree (at least the NAND node), the strength requested, the boot log, the errors?
Here's the relevant part of the device tree
nand@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; #address-cells = <0x1>; #size-cells = <0x1>; interrupts = <0x71>; clocks = <0xc 0x0>; status = "okay"; num-cs = <0x1>; marvell,nand-enable-arbiter; nand-on-flash-bbt; };
...
dfx-server@ac000000 { compatible = "marvell,dfx-server", "simple-bus"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x8000000 0x0 0x100000>; reg = <0x8000000 0x0 0x100000>; phandle = <0xe>;
corediv-clock@f8268 { compatible = "marvell,mv98dx3236-corediv-clock"; reg = <0xf8268 0xc>; #clock-cells = <0x1>; clocks = <0x9>; clock-output-names = "nand"; phandle = <0xc>; };};
<snip old partial boot info>
Can you paste the full boot logs?
4.17.0-rc4 + xtype patch + delay patch
Booting Linux on physical CPU 0x0 Linux version 4.17.0-rc4-at1+ (@chrisp-dl) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0)) #4 SMP PREEMPT Tue May 8 00:58:27 U TC 2018 CPU: ARMv7 Processor [562f5842] revision 2 (ARMv7), cr=10c5387d CPU: div instructions available: patching division code CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache OF: fdt: Machine model: SBx81XLEM Memory policy: Data cache writealloc On node 0 totalpages: 262144 Normal zone: 2048 pages used for memmap Normal zone: 0 pages reserved Normal zone: 262144 pages, LIFO batch:31 random: get_random_bytes called from start_kernel+0x9c/0x400 with crng_init=0 percpu: Embedded 15 pages/cpu @(ptrval) s30848 r8192 d22400 u61440 pcpu-alloc: s30848 r8192 d22400 u61440 alloc=15*4096 pcpu-alloc: [0] 0 [0] 1 Built 1 zonelists, mobility grouping on. Total pages: 260096 Kernel command line: console=ttyS0,115200 root=/dev/ram0 releasefile=/var/lib/tftpboot/lif_12.rel bootversion=5.1.2 loglevel=8 mtdoop s.mtddev=errlog rtctime=050800292018.34 reladdr=0x1000000,f98f1f Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 1017708K/1048576K available (5120K kernel code, 198K rwdata, 1488K rodata, 1024K init, 108K bss, 30868K reserved, 0K cma-rese rved) Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xffc00000 - 0xfff00000 (3072 kB) vmalloc : 0xc0800000 - 0xff800000 (1008 MB) lowmem : 0x80000000 - 0xc0000000 (1024 MB) modules : 0x7f000000 - 0x80000000 ( 16 MB) .text : 0x(ptrval) - 0x(ptrval) (6112 kB) .init : 0x(ptrval) - 0x(ptrval) (1024 kB) .data : 0x(ptrval) - 0x(ptrval) ( 199 kB) .bss : 0x(ptrval) - 0x(ptrval) ( 109 kB) SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Preemptible hierarchical RCU implementation. RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. Tasks RCU enabled. RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 L2C: DT/platform modifies aux control register: 0x1a09ef00 -> 0x1a09ef02 Aurora cache controller enabled, 32 ways, 2048 kB Aurora: CACHE_ID 0x00000100, AUX_CTRL 0x1a09ef02 Switching to timer-based delay loop, resolution 40ns sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 85899345900ns clocksource: armada_370_xp_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 76450417870 ns Calibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=250000) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) CPU: Testing write buffer coherency: ok CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0x100000 - 0x100060 mvebu-soc-id: MVEBU SoC ID=0xFC00, Rev=0x0 mvebu-pmsu: Initializing Power Management Service Unit Hierarchical SRCU implementation. smp: Bringing up secondary CPUs ... CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 smp: Brought up 1 node, 2 CPUs SMP: Total of 2 processors activated (100.00 BogoMIPS). CPU: All CPU(s) started in SVC mode. devtmpfs: initialized VFP support v0.3: implementor 56 architecture 2 part 20 variant 9 rev 6 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns futex hash table entries: 512 (order: 3, 32768 bytes) pinctrl core: initialized pinctrl subsystem NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb EDAC MC: Ver: 3.0.0 EDAC DEBUG: edac_mc_sysfs_init: device mc created clocksource: Switched to clocksource armada_370_xp_clocksource NET: Registered protocol family 2 tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes) TCP established hash table entries: 8192 (order: 3, 32768 bytes) TCP bind hash table entries: 8192 (order: 4, 65536 bytes) TCP: Hash tables configured (established 8192 bind 8192) UDP hash table entries: 512 (order: 2, 16384 bytes) UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) NET: Registered protocol family 1 PCI: CLS 0 bytes, default 64 Trying to unpack rootfs image as initramfs... rootfs image is not initramfs (junk in compressed archive); looks like an initrd Freeing initrd memory: 13176K workingset: timestamp_bits=30 max_order=18 bucket_order=0 squashfs: version 4.0 (2009/01/31) Phillip Lougher Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) io scheduler mq-deadline registered io scheduler kyber registered armada-xp-pinctrl f1018000.pin-ctrl: registered pinctrl driver mvebu-pcie soc:pcie@82000000: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [io 0x1000-0xfffff] pci_bus 0000:00: root bus resource [mem 0xf8000000-0xffdfffff] pci_bus 0000:00: root bus resource [bus 00-ff] pci 0000:00:01.0: [11ab:fc00] type 01 class 0x060400 PCI: bus0: Fast back to back transfers disabled pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring pci 0000:01:00.0: [14e4:1656] type 00 class 0x020000 pci 0000:01:00.0: reg 0x10: [mem 0x94000000-0x9400ffff 64bit pref] pci 0000:01:00.0: reg 0x18: [mem 0x94010000-0x9401ffff 64bit pref] pci 0000:01:00.0: reg 0x20: [mem 0x94020000-0x9402ffff 64bit pref] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold pci 0000:01:00.1: [14e4:1656] type 00 class 0x020000 pci 0000:01:00.1: reg 0x10: [mem 0x94030000-0x9403ffff 64bit pref] pci 0000:01:00.1: reg 0x18: [mem 0x94040000-0x9404ffff 64bit pref] pci 0000:01:00.1: reg 0x20: [mem 0x94050000-0x9405ffff 64bit pref] pci 0000:01:00.1: PME# supported from D0 D3hot D3cold PCI: bus1: Fast back to back transfers disabled pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 pci 0000:00:01.0: BAR 8: assigned [mem 0xf8000000-0xf80fffff] pci 0000:01:00.0: BAR 0: assigned [mem 0xf8000000-0xf800ffff 64bit pref] pci 0000:01:00.0: BAR 2: assigned [mem 0xf8010000-0xf801ffff 64bit pref] pci 0000:01:00.0: BAR 4: assigned [mem 0xf8020000-0xf802ffff 64bit pref] pci 0000:01:00.1: BAR 0: assigned [mem 0xf8030000-0xf803ffff 64bit pref] pci 0000:01:00.1: BAR 2: assigned [mem 0xf8040000-0xf804ffff 64bit pref] pci 0000:01:00.1: BAR 4: assigned [mem 0xf8050000-0xf805ffff 64bit pref] pci 0000:00:01.0: PCI bridge to [bus 01] pci 0000:00:01.0: bridge window [mem 0xf8000000-0xf80fffff] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled console [ttyS0] disabled f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 19, base_baud = 12500000) is a 16550A console [ttyS0] enabled f1012100.serial: ttyS1 at MMIO 0xf1012100 (irq = 20, base_baud = 12500000) is a 16550A brd: module loaded loop: module loaded nand: nand_flash_detect_onfi: 00000000: 4f 4e 46 49 02 00 18 00 3f 00 00 00 00 00 00 00 ONFI....?....... 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00000020: 4d 49 43 52 4f 4e 20 20 20 20 20 20 4d 54 32 39 MICRON MT29 00000030: 46 38 47 30 38 41 42 41 43 41 57 50 20 20 20 20 F8G08ABACAWP 00000040: 2c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ,............... 00000050: 00 10 00 00 e0 00 00 04 00 00 38 00 40 00 00 00 ..........8.@... 00000060: 00 10 00 00 01 23 01 50 00 06 04 01 00 00 04 00 .....#.P........ 00000070: 08 01 0e 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00000080: 0a 3f 00 3f 00 58 02 10 27 19 00 64 00 00 00 00 .?.?.X..'..d.... 00000090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000a0: 00 00 00 00 01 00 01 00 00 02 04 80 01 81 04 01 ................ 000000b0: 02 01 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8e 3d ...............=
CP> my debug dumping the ONFI params
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xd3 nand: Micron MT29F8G08ABACAWP nand: 1024 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224 Bad block table found at page 262080, version 0x01 Bad block table found at page 262016, version 0x01 3 fixed-partitions partitions found on MTD device pxa3xx_nand-0 Creating 3 MTD partitions on "pxa3xx_nand-0": 0x000000000000-0x00003f800000 : "user" 0x00003f800000-0x00003fc00000 : "errlog" mtdoops: ready 0, 1 (no erase) mtdoops: Attached to MTD device 1 0x00003fc00000-0x000040000000 : "nand-bbt" m25p80 spi0.0: m25p128 (16384 Kbytes) 3 fixed-partitions partitions found on MTD device spi0.0 Creating 3 MTD partitions on "spi0.0": 0x000000000000-0x000000100000 : "u-boot" 0x000000100000-0x000000140000 : "u-boot-env" 0x000000140000-0x000001000000 : "unused" libphy: Fixed MDIO Bus: probed libphy: orion_mdio_bus: probed usbcore: registered new interface driver asix usbcore: registered new interface driver cdc_ether usbcore: registered new interface driver smsc75xx usbcore: registered new interface driver usb-storage i2c /dev entries driver i2c i2c-0: Added multiplexed i2c bus 1 i2c i2c-0: Added multiplexed i2c bus 2 i2c i2c-0: Added multiplexed i2c bus 3 i2c i2c-0: Added multiplexed i2c bus 4 i2c i2c-0: Added multiplexed i2c bus 5 i2c i2c-0: Added multiplexed i2c bus 6 i2c i2c-0: Added multiplexed i2c bus 7 i2c i2c-0: Added multiplexed i2c bus 8 pca954x 0-0071: registered 8 multiplexed busses for I2C switch pca9548 i2c i2c-0: Added multiplexed i2c bus 9 i2c i2c-0: Added multiplexed i2c bus 10 i2c i2c-0: Added multiplexed i2c bus 11 i2c i2c-0: Added multiplexed i2c bus 12 i2c i2c-0: Added multiplexed i2c bus 13 i2c i2c-0: Added multiplexed i2c bus 14 i2c i2c-0: Added multiplexed i2c bus 15 i2c i2c-0: Added multiplexed i2c bus 16 pca954x 0-0072: registered 8 multiplexed busses for I2C switch pca9548 orion_wdt: Initial timeout 171 sec ipip: IPv4 and MPLS over IPv4 tunneling driver Initializing XFRM netlink socket NET: Registered protocol family 10 Segment Routing with IPv6 sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver NET: Registered protocol family 17 NET: Registered protocol family 15 Registering SWP/SWPB emulation handler registered taskstats version 1 RAMDISK: squashfs filesystem found at block 0 RAMDISK: Loading 13174KiB [1 disk] into ram disk... - \ done. VFS: Mounted root (squashfs filesystem) readonly on device 1:0. devtmpfs: mounted Freeing unused kernel memory: 1024K overlayfs: upper fs does not support xattr, falling back to index=off. overlayfs: upper fs does not support xattr, falling back to index=off. overlayfs: upper fs does not support xattr, falling back to index=off. systemd[1]: System time before build time, advancing clock. systemd[1]: Failed to insert module 'autofs4': No such file or directory systemd[1]: systemd 234 running in system mode. (-PAM -AUDIT -SELINUX -IMA -APPARMOR -SMACK -SYSVINIT -UTMP -LIBCRYPTSETUP -GCRYPT -G NUTLS -ACL -XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN default-hierarchy=hybrid) systemd[1]: Detected architecture arm.
Linux
systemd[1]: Set hostname to <awplus>. random: systemd: uninitialized urandom read (16 bytes read) systemd[1]: Initializing machine ID from random generator. random: systemd: uninitialized urandom read (16 bytes read) systemd[1]: Reached target Timers. [ OK ] Reached target Timers. random: systemd: uninitialized urandom read (16 bytes read) systemd[1]: Listening on udev Control Socket. [ OK ] Listening on udev Control Socket. systemd[1]: Reached target Swap. [ OK ] Reached target Swap. systemd[1]: Created slice System Slice. [ OK ] Created slice System Slice. systemd[1]: Mounting Kernel Debug File System... Mounting Kernel Debug File System... systemd[1]: Listening on Syslog Socket. [ OK ] Listening on Syslog Socket. [ OK ] Listening on /dev/initctl Compatibility Named Pipe. [ OK ] Listening on Journal Socket (/dev/log). [ OK ] Started Forward Password Requests to Wall Directory Watch. [ OK ] Listening on udev Kernel Socket. [ OK ] Listening on Journal Socket. Starting Journal Service... [ OK ] Reached target Sockets. Starting udev Coldplug all Devices... Starting Remount Root and Kernel File Systems... [ OK ] Started Dispatch Password Requests to Console Directory Watch. [ OK ] Reached target Paths. [ OK ] Created slice system-serial\x2dgetty.slice. Starting udev Kernel Device Manager... Starting Apply Kernel Variables... [ OK ] Reached target Slices. [ OK ] Mounted Kernel Debug File System. [ OK ] Started Remount Root and Kernel File Systems. [ OK ] Started Journal Service. Starting Flush Journal to Persistent Storage... [ OK ] Reached target Local File Systems (Pre). Mounting /tmp... [ OK ] Mounted /tmp. Starting Linuxbox Startup... [ OK ] Reached target Local File Systems. Starting Update is Completed... [ OK ] Started udev Coldplug all Devices. [ OK ] Started Applysystemd-journald[650]: Received request to flush runtime journal from PID 1 Kernel Variables. [ OK ] Started Flush Journal to Persistent Storage. Mounting static filesystems... [ OK ] Started udev Kernel Device Manager. [ OK ] Started Update is Completed. [ OK ] [ OK ] Found device /dev/ttyS0. [ OK ] Found device /dev/ttyS1. Attaching to /dev/mtd0... ubi0: attaching mtd0 ubi0: scanning is finished ubi0: empty MTD device detected ubi0: attached mtd0 (name "user", size 1016 MiB) ubi0: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes ubi0: min./max. I/O unit sizes: 4096/4096, sub-page size 4096 ubi0: VID header offset: 4096 (aligned 4096), data offset: 8192 ubi0: good PEBs: 4064, bad PEBs: 0, corrupted PEBs: 0 ubi0: user volume: 0, internal volumes: 1, max. volumes count: 128 ubi0: max/mean erase counter: 0/0, WL threshold: 4096, image sequence number: 446481738 ubi0: available PEBs: 3980, total reserved PEBs: 84, PEBs reserved for bad PEB handling: 80 ubi0: background thread "ubi_bgt0d" started, PID 1039 [ OK ] Mounting file system... [ INFO ] random: fast init done +----------------------------------------------------+ | | mount: mounting ubi0:user on /flash failed: No suc |----+ | h device | | The user flash filesystem is corrupt. | | The system will now erase and re-format the flash | | filesystem. | +----------------------------------------------------+
CP> This is expected since the chip was erased before this boot.
Creating empty flash filesystem image... [ OK ] ubi0: detaching mtd0 ubi0: mtd0 is detached Formatting /dev/mtd0... [ OK ] Attaching to /dev/mtd0... ubi0: attaching mtd0 ubi0: scanning is finished ubi0: attached mtd0 (name "user", size 1016 MiB) ubi0: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes ubi0: min./max. I/O unit sizes: 4096/4096, sub-page size 4096 ubi0: VID header offset: 4096 (aligned 4096), data offset: 8192 ubi0: good PEBs: 4064, bad PEBs: 0, corrupted PEBs: 0 ubi0: user volume: 0, internal volumes: 1, max. volumes count: 128 ubi0: max/mean erase counter: 0/0, WL threshold: 4096, image sequence number: 1680402752 ubi0: available PEBs: 3980, total reserved PEBs: 84, PEBs reserved for bad PEB handling: 80 ubi0: background thread "ubi_bgt0d" started, PID 1074 [ OK ] Creating volume... [ OK ] Updating volume... [ OK ] Re-mounting file system... UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 1087 UBIFS (ubi0:0): start fixing up free space UBIFS (ubi0:0): free space fixup complete UBIFS (ubi0:0): UBIFS: mounted UBI device 0, volume 0, name "user" UBIFS (ubi0:0): LEB size: 253952 bytes (248 KiB), min./max. I/O unit sizes: 4096 bytes/4096 bytes UBIFS (ubi0:0): FS size: 1008189440 bytes (961 MiB, 3970 LEBs), journal size 9404416 bytes (8 MiB, 38 LEBs) UBIFS (ubi0:0): reserved for root: 0 bytes (0 KiB) UBIFS (ubi0:0): media format: w4/r0 (latest is w5/r0), UUID 56D01DE4-B181-42C6-9DA1-02C1C86622EF, small LPT model UBIFS error (ubi0:0 pid 1084): ubifs_read_node: bad node type (9 but expected 0) UBIFS error (ubi0:0 pid 1084): ubifs_read_node: bad node at LEB 10:0, LEB mapping status 1 magic 0x6101831 crc 0x7532a597 node_type 9 (indexing node) group_type 0 (no node group) sqnum 3 len 48 child_cnt 1 level 0 Branches: 0: LEB 10:0 len 160 key (1, inode) CPU: 0 PID: 1084 Comm: mount Not tainted 4.17.0-rc4-at1+ #4 Hardware name: Marvell Armada 370/XP (Device Tree) [<80110f40>] (unwind_backtrace) from [<8010c350>] (show_stack+0x10/0x14) [<8010c350>] (show_stack) from [<805c1474>] (dump_stack+0x88/0x9c) [<805c1474>] (dump_stack) from [<802ccc80>] (ubifs_read_node+0x130/0x284) [<802ccc80>] (ubifs_read_node) from [<802e8ee8>] (ubifs_tnc_read_node+0xcc/0xd4) [<802e8ee8>] (ubifs_tnc_read_node) from [<802d0098>] (ubifs_tnc_locate+0x1c4/0x1ec) [<802d0098>] (ubifs_tnc_locate) from [<802c80f8>] (ubifs_iget+0x98/0x56c) [<802c80f8>] (ubifs_iget) from [<802c88c0>] (ubifs_mount+0x2f4/0x1594) [<802c88c0>] (ubifs_mount) from [<801eefe8>] (mount_fs+0x14/0xa4) [<801eefe8>] (mount_fs) from [<8020a448>] (vfs_kern_mount+0x4c/0xf4) [<8020a448>] (vfs_kern_mount) from [<8020d5fc>] (do_mount+0x184/0xb98) [<8020d5fc>] (do_mount) from [<8020e390>] (ksys_mount+0x8c/0xbc) [<8020e390>] (ksys_mount) from [<80101000>] (ret_fast_syscall+0x0/0x54) Exception stack(0xbda0ffa8 to 0xbda0fff0) ffa0: 00000000 00000000 7ef62f4e 7ef62f60 7ef62f48 00008010 ffc0: 00000000 00000000 7ef62f48 00000015 7ef62f4e 00008010 00000000 000a5f44 ffe0: 76da91b0 7ef62af0 00046020 76da91c0 UBIFS error (ubi0:0 pid 1084): ubifs_iget: failed to read inode 1, error -22 UBIFS (ubi0:0): background thread "ubifs_bgt0_0" stops [FAILED] +----------------------------------------------------+ | | mount: mounting ubi0:user on /flash failed: Invali |----+ | d argument | +----------------------------------------------------+ Checking for last gasp debug output... [ OK ] /sbin/fs-local-setup: line 374: can't create /flash/.configs/upstart.conf: nonexistent directory touch: /flash/.configs/localtime: No such file or directory chmod: /flash/.configs/localtime: No such file or directory mkdir: can't create directory '/flash/.nvs': Read-only file system mount: mounting /flash/.nvs on /nvs failed: No such file or directory [ OK ] Started Linuxbox Startup. [ OK ] Reached target System Initialization. [ OK ] Reached target Basic System. [ OK ] Started Serial Getty on ttyS0. Starting crond... Starting apteryx... [ OK ] Started Serial Getty on ttyS1. Starting syslog-ng... [ OK ] Started inetd. Starting Install test files... [ OK ] Started crond. [ OK ] Started apteryx. Starting StrongSwan IPsec... [ OK ] Started logconf. [ OK ] Started Install test files. [ OK ] Started StrongSwan IPsec. [ OK ] Started syslog-ng. [ OK ] Reached target Multi-User System. [ OK ] Reached target Login Prompts.
linuxbox login: root [root@linuxbox ~]# cat /sys/class/mtd/mtd0/ecc_strength 16 [root@linuxbox ~]# cat /sys/class/mtd/mtd0/ecc_step_size 1024
Are you sure Linux ECC configuration is aligned with the bootloader's?
In this case the bootloader doesn't have any NAND support enabled since this board is always network booting.
It is likely that an older kernel has set this up with ecc-strength=4. Does flash_erase destroy the ecc data as well or is there some other mtd-util to do this from userland?
There's no metadata describing the ECC setup to use. flash_erase should place the NAND is a clean state.
That got me thinking. I ran with the new driver but the following added to the dts
nand-ecc-strength = <4>;nand-ecc-step-size = <512>;After an erase/re-init things were working.
But then if I have nothing (auto-select) or nand-ecc-strength = <8> (which would be "correct" for this chip) in the dts I get the errors above.
Maybe a problem with the 16bits/1024bytes layout, but what's weird is that the driver does not report ECC errors.
Maybe. I've stumbled across little differences between Armada-38x and 98DX4251 before but they are mostly to do with the fact the clock control is moved. I haven't struck anything where the NFC has different behaviour (until now).
The old pxa3xx driver seems happy with the 16bits/1024bytes. Unless it's lying to me and falling back to 16/2048.
On Tue, 8 May 2018 01:38:13 +0000 Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
Hi Boris,
Thanks for picking this up while Miquel is taking a break.
Can you try with the following diff applied?
--->8--- diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index db5ec4e8bde9..ebb1d141b900 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -1194,11 +1194,13 @@ static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, NDCB0_CMD2(NAND_CMD_READSTART);
/* - * Trigger the naked read operation only on the last chunk. - * Otherwise, use monolithic read. + * Trigger the monolithic read on the first chunk, then naked read on + * intermediate chunks and finally a last naked read on the last chunk. */ - if (lt->nchunks == 1 || (chunk < lt->nchunks - 1)) + if (chunk == 0) nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW); + else if (chunk < lt->nchunks - 1) + nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); else nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
Hi Boris,
On 08/05/18 19:59, Boris Brezillon wrote:
On Tue, 8 May 2018 01:38:13 +0000 Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
Hi Boris,
Thanks for picking this up while Miquel is taking a break.
Can you try with the following diff applied?
--->8--- diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index db5ec4e8bde9..ebb1d141b900 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -1194,11 +1194,13 @@ static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk, NDCB0_CMD2(NAND_CMD_READSTART); /*
* Trigger the naked read operation only on the last chunk.* Otherwise, use monolithic read.
* Trigger the monolithic read on the first chunk, then naked read on* intermediate chunks and finally a last naked read on the last chunk. */
if (lt->nchunks == 1 || (chunk < lt->nchunks - 1))
if (chunk == 0) nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);else if (chunk < lt->nchunks - 1)nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW); else nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
Tested-by: Chris Packham chris.packham@alliedtelesis.co.nz
Works for:
Armada-385 + Micron MT29F8G08ABACAWP Armada-385 + Micron MT29F2G08ABAEAWP Armada-385 + Macronix MX30LF2G18AC Armada-98DX4251 + Micron MT29F8G08ABACAWP (previously failed) Armada-98DX3236 + AMD/Spansion S34ML01G2 Armada-98DX3236 + Macronix MX30LF1G18AC
On Thu, 3 May 2018 12:00:27 +0200 Miquel Raynal miquel.raynal@bootlin.com wrote:
One layout supported by the Marvell NAND controller supports NAND pages of 2048 bytes, all handled in one single chunk when using BCH with a strength of 4-bit per 512 bytes. In this case, instead of the generic XTYPE_WRITE_DISPATCH/XTYPE_LAST_NAKED_RW couple, the controller expects to receive XTYPE_MONOLITHIC_RW.
This fixes problems at boot like:
[ 1.315475] Scanning device for bad blocks [ 3.203108] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 3.209564] nand_bbt: error while writing BBT block -110 [ 4.243106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.283106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 5.289562] nand_bbt: error -110 while marking block 2047 bad [ 6.323106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 6.329559] nand_bbt: error while writing BBT block -110 [ 7.363106] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.403105] marvell-nfc f10d0000.flash: Timeout waiting for RB signal [ 8.409559] nand_bbt: error -110 while marking block 2046 bad ...
Fixes: 02f26ecf8c772 ("mtd: nand: add reworked Marvell NAND controller driver") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com
Queued to mtd/fixes.
Thanks,
Boris
Chris,
Can you please give this patch a try? This is very likely to solve your boot issue.
Thanks, Miquèl
drivers/mtd/nand/raw/marvell_nand.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index e4b964fd40d8..db5ec4e8bde9 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -1408,6 +1408,7 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip); struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
- u32 xtype; int ret; struct marvell_nfc_op nfc_op = { .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
@@ -1423,7 +1424,12 @@ marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk, * last naked write. */ if (chunk == 0) {
nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_WRITE_DISPATCH) |
if (lt->nchunks == 1)xtype = XTYPE_MONOLITHIC_RW;elsextype = XTYPE_WRITE_DISPATCH;nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) | NDCB0_ADDR_CYC(marvell_nand->addr_cyc) | NDCB0_CMD1(NAND_CMD_SEQIN);
linux-stable-mirror@lists.linaro.org
-
Boris Brezillon -
Chris Packham -
Miquel Raynal