After fixing the handling of POSTED_INTR_WAKEUP_VECTOR for vCPUs with disabled APICv, take care of POSTED_INTR_VECTOR. The IRTE for an assigned device can trigger a POSTED_INTR_VECTOR even if APICv is disabled on the vCPU that receives it. In that case, the interrupt will just cause a vmexit and leave the ON bit set together with the PIR bit corresponding to the interrupt.
Right now, the interrupt would not be delivered until APICv is re-enabled. However, fixing this is just a matter of always doing the PIR->IRR synchronization, even if the vCPU does not have APICv enabled.
This is not a problem for performance, or if anything it is an improvement. static_call_cond will elide the function call if APICv is not present or disabled, or if (as is the case for AMD hardware) it does not require a sync_pir_to_irr callback. And in the common case where kvm_vcpu_apicv_active(vcpu) is true, one fewer check has to be performed.
Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini pbonzini@redhat.com --- arch/x86/kvm/x86.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index dcefb1485362..eda86378dcff 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4445,8 +4445,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) { - if (kvm_vcpu_apicv_active(vcpu)) - static_call(kvm_x86_sync_pir_to_irr)(vcpu); + static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
return kvm_apic_get_state(vcpu, s); } @@ -9645,8 +9644,7 @@ static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) if (irqchip_split(vcpu->kvm)) kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); else { - if (kvm_vcpu_apicv_active(vcpu)) - static_call(kvm_x86_sync_pir_to_irr)(vcpu); + static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); if (ioapic_in_kernel(vcpu->kvm)) kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); } @@ -9919,10 +9917,12 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
/* * This handles the case where a posted interrupt was - * notified with kvm_vcpu_kick. + * notified with kvm_vcpu_kick. Assigned devices can + * use the POSTED_INTR_VECTOR even if APICv is disabled, + * so do it even if !kvm_vcpu_apicv_active(vcpu). */ - if (kvm_lapic_enabled(vcpu) && kvm_vcpu_apicv_active(vcpu)) - static_call(kvm_x86_sync_pir_to_irr)(vcpu); + if (kvm_lapic_enabled(vcpu)) + static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
if (kvm_vcpu_exit_request(vcpu)) { vcpu->mode = OUTSIDE_GUEST_MODE;
On Wed, Nov 17, 2021, Paolo Bonzini wrote:
After fixing the handling of POSTED_INTR_WAKEUP_VECTOR for vCPUs with disabled APICv, take care of POSTED_INTR_VECTOR. The IRTE for an assigned device can trigger a POSTED_INTR_VECTOR even if APICv is disabled on the vCPU that receives it. In that case, the interrupt will just cause a vmexit and leave the ON bit set together with the PIR bit corresponding to the interrupt.
Right now, the interrupt would not be delivered until APICv is re-enabled. However, fixing this is just a matter of always doing the PIR->IRR synchronization, even if the vCPU does not have APICv enabled.
This is not a problem for performance, or if anything it is an improvement. static_call_cond will elide the function call if APICv is not present or disabled, or if (as is the case for AMD hardware) it does not require a sync_pir_to_irr callback.
The AMD part is not accurate, SVM's sync_pir_to_irr() is wired up to point at kvm_lapic_find_highest_irr(). That can and probably should be fixed in a separate patch,
And I believe apic_has_interrupt_for_ppr() needs to be updated as well.
We can handled both at once by nullifying SVM's hook and explicitly checking for a non-NULL implementation in apic_has_interrupt_for_ppr(), which is the only path that cares about the result of sync_pir_to_irr(), i.e. needs to do the work in the SVM case.
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4388d22df500..1456745cf5c6 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -707,7 +707,8 @@ static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) { int highest_irr; - if (apic->vcpu->arch.apicv_active) + + if (kvm_x86_ops.sync_pir_to_irr) highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); else highest_irr = apic_find_highest_irr(apic); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ccbf96876ec6..470552e68b7e 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4649,7 +4649,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .load_eoi_exitmap = svm_load_eoi_exitmap, .hwapic_irr_update = svm_hwapic_irr_update, .hwapic_isr_update = svm_hwapic_isr_update, - .sync_pir_to_irr = kvm_lapic_find_highest_irr, + .sync_pir_to_irr = NULL, .apicv_post_state_restore = avic_post_state_restore,
.set_tss_addr = svm_set_tss_addr,
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Paolo Bonzini -
Sean Christopherson