The clear-residuals mitigate is a relatively heavy hammer and under some circumstances the user may wish to forgo the context isolation in order to meet some performance requirement. Introduce a generic module parameter to allow selectively enabling/disabling different mitigations.

Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson chris@chris-wilson.co.uk Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Jon Bloomfield jon.bloomfield@intel.com Cc: Rodrigo Vivi rodrigo.vivi@intel.com Cc: stable@vger.kernel.org # v5.7 --- drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gt/intel_ring_submission.c | 4 +- drivers/gpu/drm/i915/i915_mitigations.c | 119 ++++++++++++++++++ drivers/gpu/drm/i915/i915_mitigations.h | 13 ++ 4 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/i915_mitigations.c create mode 100644 drivers/gpu/drm/i915/i915_mitigations.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 4074d8cb0d6e..48f82c354611 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -38,6 +38,7 @@ i915-y += i915_drv.o \ i915_config.o \ i915_irq.o \ i915_getparam.o \ + i915_mitigations.o \ i915_params.o \ i915_pci.o \ i915_scatterlist.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 72d4722441bf..d529608d4456 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -32,6 +32,7 @@ #include "gen6_ppgtt.h" #include "gen7_renderclear.h" #include "i915_drv.h" +#include "i915_mitigations.h" #include "intel_breadcrumbs.h" #include "intel_context.h" #include "intel_gt.h" @@ -920,7 +921,8 @@ static int switch_context(struct i915_request *rq) GEM_BUG_ON(HAS_EXECLISTS(engine->i915));

if (engine->wa_ctx.vma && ce != engine->kernel_context) { - if (engine->wa_ctx.vma->private != ce) { + if (engine->wa_ctx.vma->private != ce && + i915_mitigate_clear_residuals()) { ret = clear_residuals(rq); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_mitigations.c b/drivers/gpu/drm/i915/i915_mitigations.c new file mode 100644 index 000000000000..825af550a11c --- /dev/null +++ b/drivers/gpu/drm/i915/i915_mitigations.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include <linux/kernel.h> +#include <linux/moduleparam.h> +#include <linux/slab.h> +#include <linux/string.h> + +#include "i915_mitigations.h" + +static unsigned long mitigations = ~0UL; + +enum { + CLEAR_RESIDUALS = 0, +}; + +bool i915_mitigate_clear_residuals(void) +{ + return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS); +} + +static int mitigations_parse(const char *arg) +{ + unsigned long new = ~0UL; + char *str, *sep, *tok; + bool first = true; + int err = 0; + + str = kstrdup(arg, GFP_KERNEL); + if (!str) + return -ENOMEM; + + for (sep = strim(str); (tok = strsep(&sep, ","));) { + bool enable = true; + + if (first) { + first = false; + + if (!strcmp(tok, "auto")) { + new = ~0UL; + continue; + } + + new = 0; + if (!strcmp(tok, "off")) + continue; + } + + if (*tok == '!') { + enable = !enable; + tok++; + } + + if (!strncmp(tok, "no", 2)) { + enable = !enable; + tok += 2; + } + + if (*tok == '\0') + continue; + + if (!strcmp(tok, "residuals")) { + if (enable) + new |= BIT(CLEAR_RESIDUALS); + else + new &= ~BIT(CLEAR_RESIDUALS); + } else { + err = -EINVAL; + break; + } + } + kfree(str); + if (err) + return err; + + WRITE_ONCE(mitigations, new); + return 0; +} + +static int mitigations_set(const char *val, const struct kernel_param *kp) +{ + int err; + + err = mitigations_parse(val); + if (err) + return err; + + err = param_set_charp(val, kp); + if (err) + return err; + + return 0; +} + +static const struct kernel_param_ops ops = { + .set = mitigations_set, + .get = param_get_charp, + .free = param_free_charp +}; + +static char *param; +module_param_cb_unsafe(mitigations, &ops, &param, 0400); +MODULE_PARM_DESC(mitigations, +"Selectively enable security mitigations for all Intel® GPUs.\n" +"\n" +" auto -- enables all mitigations required for the platform [default]\n" +" off -- disables all mitigations\n" +"\n" +"Individual mitigations can be enabled by passing a comma-separated string,\n" +"e.g. mitigations=residuals to enable only clearing residuals or\n" +"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n" +"Either '!' or 'no' may be used to switch from enabling the mitigation to\n" +"disabling it.\n" +"\n" +"Active mitigations for Ivybridge, Baytrail, Haswell:\n" +" residuals -- clear all thread-local registers between contexts" +); diff --git a/drivers/gpu/drm/i915/i915_mitigations.h b/drivers/gpu/drm/i915/i915_mitigations.h new file mode 100644 index 000000000000..1359d8135287 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_mitigations.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef __I915_MITIGATIONS_H__ +#define __I915_MITIGATIONS_H__ + +#include <linux/types.h> + +bool i915_mitigate_clear_residuals(void); + +#endif /* __I915_MITIGATIONS_H__ */

-----Original Message----- From: Chris Wilson chris@chris-wilson.co.uk Sent: Saturday, January 09, 2021 7:49 AM To: intel-gfx@lists.freedesktop.org Cc: Chris Wilson chris@chris-wilson.co.uk; Mika Kuoppala mika.kuoppala@linux.intel.com; Kumar Valsan, Prathap prathap.kumar.valsan@intel.com; Abodunrin, Akeem G akeem.g.abodunrin@intel.com; Bloomfield, Jon jon.bloomfield@intel.com; Vivi, Rodrigo rodrigo.vivi@intel.com; Randy Wright rwright@hpe.com; stable@vger.kernel.org Subject: [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT

MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the range [0, n-1] where n is #EU * (#threads/EU) with the number of threads based on plaform and the number of EU based on the number of slices and subslices. This is a fixed number per platform/gt, so appropriately limit the number of threads we spawn to match the device.

v2: Oversaturate the system with tasks to force execution on every HW thread; if the thread idles it is returned to the pool and may be reused again before an unused thread.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024 Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Signed-off-by: Chris Wilson chris@chris-wilson.co.uk Cc: Mika Kuoppala mika.kuoppala@linux.intel.com Cc: Prathap Kumar Valsan prathap.kumar.valsan@intel.com Cc: Akeem G Abodunrin akeem.g.abodunrin@intel.com Cc: Jon Bloomfield jon.bloomfield@intel.com Cc: Rodrigo Vivi rodrigo.vivi@intel.com Cc: Randy Wright rwright@hpe.com Cc: stable@vger.kernel.org # v5.7+

---

drivers/gpu/drm/i915/gt/gen7_renderclear.c | 91 ++++++++++++---------- 1 file changed, 49 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index d93d85cd3027..3ea7c9cc0f3d 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -7,8 +7,6 @@ #include "i915_drv.h" #include "intel_gpu_commands.h"

-#define MAX_URB_ENTRIES 64 -#define STATE_SIZE (4 * 1024) #define GT3_INLINE_DATA_DELAYS 0x1E00 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))

@@ -34,38 +32,57 @@ struct batch_chunk { };

struct batch_vals {

• u32 max_primitives;
• u32 max_urb_entries;
• u32 cmd_size;
• u32 state_size;

• u32 max_threads; u32 state_start;

• u32 batch_size;

• u32 surface_start; u32 surface_height; u32 surface_width;

• u32 scratch_size;
• u32 max_size;

• u32 size;

};

+static inline int num_primitives(const struct batch_vals *bv) {

• /*

• * We need to oversaturate the GPU with work in order to dispatch
  

• * a shader on every HW thread.
  

• */
  

• return bv->max_threads + 2;

+}

static void batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) { if (IS_HASWELL(i915)) {

• bv->max_primitives = 280;
  

• bv->max_urb_entries = MAX_URB_ENTRIES;
  

• switch (INTEL_INFO(i915)->gt) {
  

• default:
  

• case 1:
  

• 	bv->max_threads = 70;
  

• 	break;
  

• case 2:
  

• 	bv->max_threads = 140;
  

• 	break;
  

• case 3:
  

• 	bv->max_threads = 280;
  

• 	break;
  

• }
  

  bv->surface_height = 16 * 16; bv->surface_width = 32 * 2 * 16; } else {

• bv->max_primitives = 128;
  

• bv->max_urb_entries = MAX_URB_ENTRIES / 2;
  

• switch (INTEL_INFO(i915)->gt) {
  

• default:
  

• case 1: /* including vlv */
  

• 	bv->max_threads = 36;
  

• 	break;
  

• case 2:
  

• 	bv->max_threads = 128;
  

• 	break;
  

• }
  

Do we really need to hardcode max number of threads per gt/platform? Why not calculating the number of active threads from the no_of_slices * 1024? - Also, is "64" not the minimum number of threads supported?

Thanks, ~Akeem