Commit 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h"), claimed L2 misses were unsupported, due to them not being found in its referenced documentation, whose link has now moved [1].

That old documentation listed PMCx064 unit mask bit 3 as:

"LsRdBlkC: LS Read Block C S L X Change to X Miss."

and bit 0 as:

"IcFillMiss: IC Fill Miss"

We now have new public documentation [2] with improved descriptions, that clearly indicate what events those unit mask bits represent:

Bit 3 now clearly states:

"LsRdBlkC: Data Cache Req Miss in L2 (all types)"

and bit 0 is:

"IcFillMiss: Instruction Cache Req Miss in L2."

So we can now add support for L2 misses in perf's genericised events as PMCx064 with both the above unit masks.

[1] The commit's original documentation reference, "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors", originally available here:

https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0F...

is now available here:

https://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Model...

[2] "Processor Programming Reference (PPR) for Family 17h Model 31h, Revision B0 Processors", available here:

https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf

Cc: stable@vger.kernel.org Cc: Alexander Shishkin alexander.shishkin@linux.intel.com Cc: Arnaldo Carvalho de Melo acme@kernel.org Cc: Borislav Petkov bp@alien8.de Cc: H. Peter Anvin hpa@zytor.com Cc: Ingo Molnar mingo@kernel.org Cc: Janakarajan Natarajan Janakarajan.Natarajan@amd.com Cc: Jiri Olsa jolsa@redhat.com Cc: Linus Torvalds torvalds@linux-foundation.org Cc: Martin Liška mliska@suse.cz Cc: Namhyung Kim namhyung@kernel.org Cc: Peter Zijlstra peterz@infradead.org Cc: Suravee Suthikulpanit Suravee.Suthikulpanit@amd.com Cc: Thomas Gleixner tglx@linutronix.de Cc: x86-ml x86@kernel.org Cc: linux-kernel@vger.kernel.org Reported-by: Babu Moger babu.moger@amd.com Tested-by: Babu Moger babu.moger@amd.com Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h") Signed-off-by: Kim Phillips kim.phillips@amd.com --- arch/x86/events/amd/core.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index a7752cd78b89..dede714b46e8 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -246,6 +246,7 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, + [PERF_COUNT_HW_CACHE_MISSES] = 0x0964, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287,