Add support for Tx De-Emphasis, Tx Swing and Rx equalization definition needed on some ipq8064 based device (Netgear R7800 for example). This cause a total lock of the system on kernel load.

Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver Signed-off-by: Ansuel Smith ansuelsmth@gmail.com Cc: stable@vger.kernel.org # v4.5+ --- drivers/pci/controller/dwc/pcie-qcom.c | 47 ++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a4fd5baada34..da8058fd1925 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -46,6 +46,9 @@

#define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -77,6 +80,18 @@ #define DBI_RO_WR_EN 1

#define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) ((x) << 24)

#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -97,6 +112,12 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *phy_reset; struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + u32 tx_deemph_gen1; + u32 tx_deemph_gen2_3p5db; + u32 tx_deemph_gen2_6db; + u32 tx_swing_full; + u32 tx_swing_low; + u32 rx0_eq; };

struct qcom_pcie_resources_1_0_0 { @@ -234,8 +255,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + struct device_node *node = dev->of_node; int ret;

+ of_property_read_u32(node, "qcom,tx-deemph-gen1", + &res->tx_deemph_gen1); + of_property_read_u32(node, "qcom,tx-deemph-gen2-3p5db", + &res->tx_deemph_gen2_3p5db); + of_property_read_u32(node, "qcom,tx-deemph-gen2-6db", + &res->tx_deemph_gen2_6db); + of_property_read_u32(node, "qcom,tx-swing-full", + &res->tx_swing_full); + of_property_read_u32(node, "qcom,tx-swing-low", + &res->tx_swing_low); + of_property_read_u32(node, "qcom,rx0-eq", &res->rx0_eq); + res->supplies[0].supply = "vdda"; res->supplies[1].supply = "vdda_phy"; res->supplies[2].supply = "vdda_refclk"; @@ -368,9 +402,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* enable PCIe clocks and resets */ qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);

+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(res->tx_deemph_gen1) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(res->tx_deemph_gen2_3p5db) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(res->tx_deemph_gen2_6db), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(res->tx_swing_full) | + PCS_SWING_TX_SWING_LOW(res->tx_swing_low), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(res->rx0_eq), pcie->parf + PCIE20_PARF_CONFIG_BITS); + /* enable external reference clock */ - qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, - BIT(16)); + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, + PHY_REFCLK_USE_PAD, PHY_REFCLK_SSP_EN;

ret = reset_control_deassert(res->phy_reset); if (ret) {