On Mon, Feb 14, 2022 at 11:18:08AM +0200, Ville Syrjala wrote:

From: Ville Syrjälä ville.syrjala@linux.intel.com

adlp+ adds some extra bits to the QGV point mask. The code attempts to handle that but forgot to actually make sure we can store those bits in the bw state. Fix it.

Cc: stable@vger.kernel.org Cc: Stanislav Lisovskiy stanislav.lisovskiy@intel.com Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support") Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com

---

drivers/gpu/drm/i915/display/intel_bw.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 46c6eecbd917..0ceaed1c9656 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -30,19 +30,19 @@ struct intel_bw_state { */ u8 pipe_sagv_reject;

• /* bitmask of active pipes */
• u8 active_pipes;
• /*
  • Current QGV points mask, which restricts
  • some particular SAGV states, not to confuse
  • with pipe_sagv_mask.
  */

• u8 qgv_points_mask;

• u16 qgv_points_mask;

Weird, that this went unnoticed. Don't we have static analyzer for such purposes? Wonder if it should catch and warn about this, because in intel_bw_atomic_check we have u32 bitmask, which is then getting packed in 8 bit field. Probably bitmask type width used in intel_bw_atomic_check should match that one, so that there would be less room for confusion.

Reviewed-by: Stanislav Lisovskiy stanislav.lisovskiy@intel.com

unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES];

• /* bitmask of active pipes */
• u8 active_pipes;
• int min_cdclk;

}; -- 2.34.1